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Reconfigurable Radio Design

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Page 1: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Reconfigurable Radio Design

Page 2: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

• Reconfigurable Architecture– Reconfigurable Chip design example– Hardware Reconfiguration

• Introduction to Software RADIO– What is the Software RADIO ?– Advantage of the Software RADIO– Physical Layer of a Radio Modem/Software Defined Radio Modem– Software Defined RADIO Project– Example of Development Tool/Configurable Resource

• Methodology of Software RADIO– Technical Challenge

– Multi Mode and Reconfigurable Terminals

– Components

– SDR Functional Blocks Description

Page 3: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Semiconductor Revolutions

TTL

custom

standard

1957

1967

1977LSI,MSI

µproc.,memory

1987

1997ASICs,accel’s

1st design crisis

2nd design crisishardware

software

2007

reconfigurable

instruction

streamsdata

streams

structured

VLSI design

“Mainstream Silicon Applicationis switching every 10 Years”Makimoto’s Wave

coarsegrain

FPGAs

Page 4: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Bro

adca

stin

g, U

biqu

itou

s

Health, H

uman, Bio

Next Wave: Endless Possibilities

D-TV

CISMobile

Recorder

Health

HCI Bio

Data Broadcasting

RFID

Automotive & Robotics

Telematics UnmannedDriving Robot

Page 5: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Why Reconfigurable System?

• GPP 와 재구성 h/w 를 포함 • 목적 : 전력 감축 및 유연성

1. 동적인 환경에 따른 Quality of Service 를 제공

2. 알고리즘 진화에 따른 유연한 구조

3. 개발 및 유지 보수해야 하는 플랫폼 감소 Reconfigurable Hardware

A

D

B

C

E

A B D C E

A B D D C C E E

Task 1

X

Z

W

Y

Task N

H I J H I J W

XY

ZW

XY

Z

Page 6: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Energy Efficiency of Reconfigurability

– system architecture– communication protocol– O/S and applications– Partitioning of functions between wireless

device and services on the network– The mobiles must be flexible enough to

accommodate a variety of multimedia services and communication capabilities and adapt to various operating conditions in an (energy) efficient way

Page 7: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

S/W configurable platform 의 필요성

– Doing More by Doing Less : 다양한 표준을 다룰 수 있는 능력이 필요 (AM, FM, GSM, UMTS, digital broadcasting standards, analog and digital television and other data links.

– A fully software reconfigurable multi-channel broadband sampling receiver for standards in the 100 MHz band

Page 8: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Gilder’s versus Moore’s law

97 9 9 01 03 05 07

Log

Gro

wth

Processor PerformanceW

AN/MAN B

andw

idth

100

10,000

1M

2x/3-6 months

2x/18 months

1000 x

Greg Papadopoulos, Sun Microsystems

Page 9: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

The Ideal Information Companion

U M TS

G S MD E C T

B luetooth

802.11

ONE phone for many Standards

ONE PDA for many Standards

ONE WLAN for many Standards ONE Information Appliance

Page 10: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Future mobile communications

Mobility

vehicle

pedestrian

static

GSM

3G cellular

WirelessLAN

4G cellular

IntelligentTransportSystems

Millimeter-waveLAN

HAPS

Data rate

10k 2M 50M 156M 622M

Advancedwirelessaccess

2G 3G 4G 5G

2000 2010 2020

High data rateHigh mobilitySystem roamingSeamless connections tobroadband networks

Page 11: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Heterogeneous wireless networks

by Havinga, [email protected]

There exist many wireless communication networks– frequency bands– requirements on mobility– transmission speed and quality

• Examples:– Static: wireless LANs (802.11), Bluetooth, Radio

Local Loop– Pedestrian: DECT, PHS– Vehicle: 2/3G cellular, pagers, broadcast TV/radio

Page 12: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Future wireless communication

• Two trends will have major impact– Wide proliferation of various wireless

access networks• Each with their own preferred type of

service• Different quality: data rates, latency,

mobility support, ..

– Software radio technologies• Programmable radios, Tunable front-ends

Page 13: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Heterogeneous networks, why?

• Due to roaming the network changed – e.g. from indoor wireless LAN to outdoor cellular

radio• There is coverage from multiple wireless net

works Possibility to select the most appropriate netw

ork for a given application, based on for example• Service classification• User requested QoS parameters• Available network capacity (bandwidth, latency)• Energy consumption needed

Page 14: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Heterogeneous network architecture

• Goal design a flexible and open architecture suitable for a variety o

f different wireless access technologies, for applications with different QoS demands, and different protocols.• Key requirements

– Different access technologies (Software Defined Radio)– Heterogeneous network support (use combination of

networks)– Mobility management (seamless handover)– Wireless system discovery– Selection of efficient configuration– Simple, scalable, low cost– Energy efficient (always on)– Secure– Compatible/interoperable with existing and future work– Quality of Service support (end-to-end, and local applicable)

Page 15: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Evolution of the Cell Phone• Two co-existent 3-G cellular standards:

– Wideband CDMA• Also called UMTS, UTRA, IMT-2000.• Standardized by 3GPP.• Evolution of the GSM backbone.

– cdma2000• Standardized by 3GPP2.• Evolved from IS-95 CDMA (cdmaONE).

• Common traits:– 2 GHz PCS band (licensed).– Variable asymmetric data rates for multimedia:

• ~144 kbps to vehicles.• ~ 2 Mbps to fixed locations near base station.

– Software-defined-radio (SDR) implementation.

Page 16: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Wireless Networking Hierarchy

LAN: IEEE 802.11& HIPERLAN

PAN: Bluetooth, IEEE 802.15

MAN:IEEE 802.16

Page 17: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Standardization of Wireless Networks

• Wireless networks are standardized by IEEE.• Under 802 LAN MAN standards committee.

ApplicationPresentation

SessionTransportNetwork

Data Link

Physical

ISOOSI7-layermodel

Logical Link Control

Medium Access (MAC)

Physical (PHY)

IEEE 802standards

Page 18: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

• Ideal 한 목표 : 채널 변복조 waveform 을 Software 를 이용 .• TX:source encoder, up-conversion of baseband signal to carry freque

ncy • RX:carry phase recovery, symbol or PN code timing recovery

• 개방형 구조 (Open Architecture)• Radios that are flexible and easily configurable by software

• 다중 대역 , 다중 모드

• Radios based on virtual components (ie. system-on-a-chip)– 대부분의 기능들이 소프트웨어 -programmable, 하드웨어 -

재구성가능한 프로세서 엘리먼트에서 소프트웨어에 의해 실현– Configurable-ASIC, DSP 칩 , 마이크로프로세서 칩 , FPGA,

다른 programmable-DSP

Page 19: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Multi-Mode Info ReceiverConventional Heterodyne

GSM 1800

BT / 802.11

UMTS

GSM 1800

BT / 802.11 LO1

UMTS

Legend

BT / 802.11

2G Cellular

3G Cellular

Low-Pass0.200-MHz BW

LO2

10-MHz Low-Pass

10-MHz Low-Pass

10-MHz Low-Pass

FDD Mode 1

FD

D M

od

e 2

LO4

LO5

LO6

5.0-MHz BW

1.25-MHz Ch l

1.25-MHz Ch 2

1.25-MHz Ch 3

LO3

10-MHz Low-Pass

1.0-MHz BW Low-Pass

LO7

Page 20: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Programmable Channel Filter

I

Q

Multi-Mode Info Receiver Software Defined Radio

LO

A/D Converter

GSM 1800

BT / 802.11

UMTS

GSM 1800

BT / 802.11

UMTS

Page 21: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Design Issues in SDR

•Design of fast and efficient analog-digital converters

•Flexibility at the RF front-end

•Effective data management procedures, resource allocation

•Smooth reconfigurability of the hardware

Page 22: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

• Multiple personalities: 개발 및 유지 / 보수해야 하는 제품 플랫폼 수 감소– One platform supports any physical layer, protocol stack– Lower System maintenance & upgrade cost

• No hardware replacement or frequent upgrade

• Flexibility: 체계적으로 스케일될 수 있는 제품구조– 새로이 진화되어 가고 있는 capacity 수용

• Backward Compatibility• 미래 안정적 (Future-Proof) 시스템 개발• Time-to-Market 최소화

Page 23: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Disadvantages

• Higher power consumption than dedicated ASIC approach

• More MIPS required• Higher cost (today)

Page 24: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Current SDR users

• Military– Consolidating a stack of radios– Bridging between radio networks

• Cellular base stations– Avoid “fork lift upgrades”– Multiple standards on same system– New features to market quicker

Page 25: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Emerging SDR uses

• Personal communication devices– Cellular / Paging / Wireless LAN(s)

• PC based “generic transceiver”– Radio / TV– Emerging unlicensed RF band apps

Page 26: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

What is “free/open software?”

• “Free as in liberty”– User has access to the source– User is free to modify and is encouraged to co

ntribute the modifications back to the community

• A culture of innovation• Various licenses: GNU General Public Licen

se (GPL), Mozilla, Artistic License.

Page 27: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

How to develop SW radio

• Proprietary software for each hardware platform

• Standardization of a common hardware platform

• Resident compilers and/or real-time standard operating system

Page 28: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Who uses free software?

• World wide community of users • Publicly traded companies support or

distribute free software: IBM, Red Hat, Mandrake

• Linux• Apache web server• Not a fringe activity

Page 29: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

What is GNU Radio?Eric Blossom [email protected]

Blossom Research +1 831 917 3428798 Lighthouse Ave., Suite 109

Monterey, CA 93940 USA

• It’s a free software defined radio• A platform for experimenting

with digital communications• A platform for signal processing

on commodity hardware

Page 30: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Vision

• Transmit and receive any signal• Create a practical environment for

experimentation & product delivery• Expand the “free software ethic”

into what were previously hardware intensive arenas

Page 31: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

What H/W is required?

• Commodity PC• RF front end (e.g., TV tuner module)• Multi-channel applications / wide B/W:

– High speed A/D (20 – 25 Msamples/sec)• Single channel / narrow bandwidth:

– SoundBlaster, AC97 codec, etc.

Page 32: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

SDR ATSC receiver is practical!

• Commodity PC:– Dual processor Athlon 1800+ MP– 512 MB RAM / 120 GB disk– $1300– Can do:

• 6 * 10^9 integer ops / sec• 4 * 10^9 FIR filter taps / sec

Page 33: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

ATSC computational requirements

• 1080i TSP decode takes about ½ of a single CPU

• Naïve equalizer: about 2.5 * 10^9 taps/s– Smart s/w version: about 0.6 * 10^9 taps/s

• Viterbi decoder: 10^6 decisions / sec.– Highly amenable to SIMD implementation– Short constraint length

Page 34: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Open source hardware too!

• General purpose SDR PCI peripheral:– Tuner module $20– 25 Msample/sec A/D converter $12– Spartan II FPGA (100k gates) $18– Misc analog, SRAM, etc $10– PWB $10– Assembly & Test $10

• Total cost to manufacture: $80

Page 35: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

GNU Radio resources

• Home page (links to source code)http://www.gnu.org/software/gnuradio

• Mailing [email protected]

• Archivehttp://mail.gnu.org/mailman/listinfo/discuss-gnuradio

• Open source hardware– http://www.opencores.org/projects/pci– PCI bridges, ethernet, memory controllers, etc.

Page 36: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

SDR Evolution

• Next Generation: HIPERLAN/2, 3G Cellular – OFDM, CDMA

– Code Domain Channelization

– Wide Band, Frequency-Shared Medium

– Friendly Interference Suppressed Via Orthogonal Chipping Codes with ~30 dB Processing Gain

– Software-centric, Can Vary Channel Characteristics with Application and Environment

Page 37: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

SDR solution 으로 5 단계Tier

0전통적인 하드웨어 구현

Tier 1

SCR(software controlled radios)

소프트웨어로 다중 하드웨어 요소에 대한 제어 특징을 구현

Tier 2

SDR(software defined radios)

소프트웨어로 변조와 기저대역 처리를 구현하고 , 다중 주파수 RF 는 고정된 기능의 하드웨어로 구현

Sand-Bridge(ARM+4DSP’s)

Tier 3

ISR(Ideal Software radio)

안테나에서 아날로그 변환 기능을 갖는 RF 구현을 통해 프로그램 능력을 확장

Tier 4

USR(Ultimate software radio)

디지털 처리 능력에 추가하여 , 빠른 ( 수 millisecond 이내 ) 통신 프로토콜 전환 능력까지 제공

Page 38: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Granularité de la reconfigurationSébastien PILLEMENT - ENSSAT/LASTI

• Reconfiguration au niveau système– Lx, C62 (décomposition en cluster)

• Reconfiguration au niveau fonctionnel– Pleiades, RaPiD, DART(2001)

• Reconfiguration au niveau opérateur– Chameleon, Piperench, Morphosys(2000)

• Reconfiguration au niveau porte• Napa, GARP, FPGA

Page 39: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

The gain size of operationsin Reconfigurable System

Architectures

– Fine gained operations : Multiply and addition

– Medium gained operations : reconfigurable modules

– Course gained operations : CPU, host

Page 40: Reconfigurable Radio Design Reconfigurable Architecture –Reconfigurable Chip design example –Hardware Reconfiguration Introduction to Software RADIO

Design Space of Reconfigurable ArchitecturesRECONFIGURABLE ARCHITECTURES

(R-SOC)

FINE GRAIN(FPGA)

MULTI GRANULARITY(Heterogeneous)

COARSE GRAIN(Systolic)

Processor +Coprocessor

Tile-BasedArchitecture

Coarse Grain Coprocessor

Fine GrainCoprocessor

IslandTopology

Hierarchical Topology

LinearTopology

HierarchicalTopology

MeshTopology

• Chameleon• REMARC• Morphosys

• Pleiades• Garp• FIPSOC• Triscend E5• Triscend A7• Xilinx Virtex-II Pro• Altera Excalibur• Atmel FPSIC

• Xilinx Virtex• Xilinx Spartran• Atmel AT40K• Lattice ispXPGA

• Altera Stratix• Altera Apex• Altera Cyclone

• Systolic Ring• RaPiD• PipeRench

• DART• FPFA

• RAW• CHESS• MATRIX• KressArray• Systolix Pulsedsp

• aSoC• E-FPFA

Lilian BossuetLESTER LabUniversité de Bretagne SudLorient, France