• Real number : X• Machine representation: XM

– Due to limited digits– Let ulp= unit of least position– Then XM X XM +ulp

– Error exists: e= XM X < ulp– Overflow or Underflow

Machine Representation

• Positive binary number system:– X=(xn-1, xn-2, …, x0)=xi2i, xi0,1

• Signed-magnitude:– xn-1 sign bit, others magnitude

• Complement– 2’s Complement– 1’s Compelement

Number System

• Let R= given constant, Y: n-bit– Complement of Y = RY– Check if (Y) = RY– then ((Y))=R (R Y)=Y O.K.

• Complement– 2’s (Radix) Complement: R= 2n

– 1’s (Diminished-Radix) Complement: R=2n ulp

Complement Representation

• 2’s Complement– R= 2n, Y: n-bit, Y= 2n Y=Y’+1– Y’= (1,1, …,1) Y– Example: Y=(0110), Y=(1010)

• X=(xn-1, xn-2, …, x0) = xn-1 2n-1 + xi2i for i= 0, 1, …, n-2

Radix Complement

• 1’s Complement– R= 2n 1, Y= 2n Y 1=Y’– Y’= (1,1, …,1) Y– Example: Y=(0110), Y=(0101)

• X=(xn-1, xn-2, …, x0) = xn-1 (2n-1 1)+ xi2i for i= 0, 1, …, n-2

Diminished-Radix Complement

ExampleSM 1’s C 2’sC

3 011 011 0112 010 010 0101 001 001 0010 000,100 000,111 000 1 101 110 111 2 110 101 110 3 111 100 101 4 100

• SM: (2n1 1) Y (2n 1 1)– Two Zeros: (00…0) & (10…0)

• 1’s C: (2n1 1) Y (2n 1 1)– Two Zeros:(00…0) & (11…1)

• 2’s C: (2n1 1) Y 2n 1

Ranges

• Operations:– ADD (M=0); SUB (M=1)– SM: Sign-bit (SA), Overflow (=OV), End-

around-carry (=C), magnitude >0– 1’s C: Overflow, End-around-carry– 2’s C: Overflow– Complement Using XOR gate

Addition/Subtraction

• Ex 1: A +B=2+1= (010)+(001)=3 (010)+(001)M+M=(010)+(001)+0= (011)

• Ex2: A B=21= (0010)(0001)= 1(010)+(001)M+M = (010) + (110) + (001)

= 1(001)• Ex3 A +B=2+2= 4=OV

(010)+(010)M+M = (100)= 4

2’C ADD/SUB (1)

• Occurs when Sign bits: P add P = NN add N = P

• OV=Cn Cn-1

2’C ADD/SUB Overflow

An-1Bn-1Cn-1 CnSn-1

000 00001 01010 01011 10100 01101 10110 10111 11

• Only consider A+B case: A B=A+( B)• Let |A|=E & |B|=F 2n-1> E, F 0• Case 1: A, B 0 2n> E+F 0

IF E+F 2n-1 OV=1 (Chk OV)• Case 2: A,B <0 A= 2n E, B = 2n F

A+B=2n+2n (E +F) Cn=1 (neglect)neglect Cn A+B= 2n (E +F) Chk OV

2’C ADD/SUB Proof(1)

• Case 3: A 0, B<0 B = 2n FA+B= 2n +(EF)= 2n (F E)E F Cn=1 (neglect) & Sign bit=0F E Cn=0 & Sign bit=1

• Case 4: B 0, A <0 Similar to Case 3A+B= 2n (EF)= 2n + (F E)E F Cn=0 & Sign bit=1F E Cn=1 (neglect) & Sign bit=0

2’C ADD/SUB Proof(2)

2’C ADD/SUB Circuit

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Cn

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OV

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+ Cn-1

• Ex 1: A +B=2+1= (010)+(001)=3 (010)+(001)M+C=(010)+(001)+0= (011)

• Ex2: A B=21= (010)(001)= 1(010)+(001)M+C = (010) + (110) =1(000)

= (000)+(001)=(001)• Ex3 A +B=2+2= 4=OV

(010)+(010)M+C = (100)= 3

1’C ADD/SUB (1)

• Same as 2’C• OV occurs when

Sign bits: P add P = NN add N = P

• OV=Cn Cn-1

1’C ADD/SUB Overflow

An-1Bn-1Cn-1 CnSn-1

000 00001 01010 01011 10100 01101 10110 10111 11

• Only consider A+B case: A B=A+( B)• Let |A|=E & |B|=F 2n-1> E, F 0• Case 1: A, B 0 Same as 2’C

IF E+F 2n-1 OV=1 (Chk OV)• Case 2: A,B <0 A= 2n E 1, B = 2n F 1

A+B=2n+2n (E +F) 2 Cn=C=1 (neglect)Add end-around carry A+B= 2n (E +F) 1 Chk OV

1’C ADD/SUB Proof(1)

• Case 3: A 0, B<0 B = 2n F 1• A+B= 2n +(EF) 1= 2n (F E) 1

E >F C=1 (neglect 2n , 1) & A+B=E F>0F E C=0 & Sign bit=1 (may have 0)

• Case 4: B 0, A <0 Similar to Case 3A+B= 2n (EF) 1= 2n + (F E) 1E F C=0 & Sign bit=1F > E C=1 (neglect 2n , 1) & A+B= F E

1’C ADD/SUB Proof(2)

1’C ADD/SUB Circuit

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Cn

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OV

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+ Cn-1

End-Around-Carry Oscillation?

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An-1Bn-1Cn-1 CnSn-1

000 00001 01010 01011 10100 01101 10110 10111 11

• Ex 1: A B=21= (0010)(0001)= 1 Init. Sign P= SA (SB M)=01=1Mag. (010)+(001)P=(010)+(110)=1(000)Add C (end-arnd-crry): (000)+(001)=(001)Final Mag. Indicator Q=P(C)’=0Final Sign S= (SA C)v((SBM)C’)= 0v0 =0Answer= (S, (Mag) Q)=(0001)

SM ADD/SUB (1)

• Ex 2: A B=12= (0001)(0010)= 1 Init. Sign P= SA (SB M)= 01=1Mag. (001)+(010)P=(001)+(101)=0(110)Add C (end-arnd-crry): (110)+(000)=(110)Final Mag. Indicator Q=P(C)’=1Final Sign S= (SAC)v((SBM)C’)= 0 v 1 =1Answer= (S, (Mag) Q)=(1001)

SM ADD/SUB (2)

• Ex 3: (0010)+(0111)= 2+7=9= OV Init. Sign P=00=0Mag. (010)+(111)P=(010)+(111)=1(001)Add C (end-arnd-crry): (001)+(001)=(010)OV=P’C=1

SM ADD/SUB (3)

• A B=A+( B) need (n-1)-bit AdderInit Sign P=0 for (SA=(SBM)); P=1 otherwiseOV occurs only at P=0Let |A|=E and |B|=F (mag. E, F 0) C

• Case 1: P=0,If (E+F P)=E+F < 2n1 C=0, No OVOtherwise C=1 and OV OV=P’C=1

SM ADD/SUB Proof(1)

• Case 2: P=1, then E+(FP)= E+F’= E+(2n F1)=2n+(E F)1 if E > F C=1 Sign=SA

• (E F)1+C= (E F); Neglect 2n =C=1otherwise (F E, Sign =(SBM)) C=0 Q=P

C’=1• 2n+( E F)1+C= 2n (F E) 1• (Mag) Q= 2n (2n (F E) 1 ) 1= (F E)

SM ADD/SUB Proof(2)

• Sign= SAC v (SBM)C’

SM ADD/SUB Proof(3)

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MUX0 1

OV Q

P