rd53 status report – july 2014 l. demaria - report on rd53 - cmstk week 22-07-20141

L. Demaria - Report on RD53 - CMSTK week 22-07-2014 1

RD53 Status Report – July 2014

L. Demaria - Report on RD53 - CMSTK week 22-07-2014

2RD53: the international context for CHIPIX65 ~ 100 members, 19 Institutes (2 new institutes have joined)

Bari, Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico, Padova, Perugia, Pisa, Prague IP/FNSPE-CTU, PSI, RAL, Torino, UC Santa Cruz.

2 institutes requesting to join: LAL/OMEGA, Sevilla

Spokes persons: Maurice Garcia-Sciveres, LBNL (ATLAS), Jorgen Christiansen, CERN (CMS) [2 year terms]

Collaboration Board (CB chair: LD, Torino) Regular CB meetings

MOU document APPROVED

Management board: Spokes persons, IB chair, WG conveners Monthly meetings

R.Beccherle newly appointed as IO-WG convener

Technical Working Groups have started WG conveners

Regular WG meetings

First official RD53 collaboration meeting (pre-RD53 meeting in Nov. 2012)

CERN April 10-11, 64 participants: https://indico.cern.ch/event/296570

https://indico.cern.ch/event/296570


3RD53 MoU

Few countries ready to sign through FUNDING Agency: Netherland, Italy, France, UK

Other Institutes sign with local authority

For few Institute there might be a problem USA Laboratories – DOE will

not sign any MoU right now

Feedback needed from PSI


4RD53 Institutes

Groups in the process of joining:

• Sevilla/Santander (CMS)• UCSB (CMS)• LAL/Omega (ATLAS)

9 ATLAS8 CMS2 CMS/ATLAS


5

TSMC / CERN Contract

Finally the Contract has been signed ! It took a long time (first estimate I heard was spring 2013, then became autumn 2013)


6


RD53 Outlook

2014: Release of CERN 65nm design kit. RD53

eagerly awaiting NDA issues to be resolved.

Detailed understanding of radiation effects in 65nm

Radiation test of few alternative technologies.

Spice models of transistors after radiation/annealing

IP/FE block responsibilities defined and appearance of first FE and IP designs/prototypes

Simulation framework with realistic hit generation and auto-verification.

Alternative architectures defined and efforts to simulate and compare these defined

Common MPW submission 1: First versions of IP blocks and analog FEs

2015: Common MPW submission 2: Near final

versions of IP blocks and FEs.

Final versions of IP blocks and FEs: Tested prototypes, documentation, simulation, etc.

IO interface of pixel chip defined in detail

Global architecture defined and extensively simulated

Common MPW submission 3: Final IPs and FEs, Initial pixel array(s)

2016: Common engineering run: Full sized

pixel array chip.

Pixel chip tests, radiation tests, beam tests , ,

2017: Separate or common ATLAS – CMS final pixel

chip submissions.

7


8RD53 WG1 (Radiation test/qualification): Summary

• CERN test structures (65nm nMOS & pMOS transistors)

CERN: 10-keV X ray (CERN), till 200 Mrad(SiO2)

CPPM: 10-keV X ray (CERN), till 1Grad(SiO2) , 20 & 100 ºC annealing

Padova: 3-MeV proton (Padova), till 1Grad(SiO2), 20 & 100 ºC annealing (31-st March, 21-22 May 2014)

• TSMC test structures - FNAL layout (65 nm nMOS & pMOS transistors)

Fermilab: Co-60 γ ray, -20 ºC irradiation, till 1Grad(SiO2)

0 10 100 1,000 10,000

-20

0

20

40

60

80

Core nMOSFETs: Shift of Vth during irradiation and annealing

After 1-week 100-degreeannealing

After 2-week room-temperature annealing

600_60 480_60 360_60 240_60 120_60

Shi

ft of

Vth (

mV

)

Dose (Mrad(SiO2))

0 10 100 1,000 10,000

0

20

40

60

80

100

120

140

Core pMOSFETs: Shift of |Vth| during irradiation and annealing

After 1-week 100-degreeannealing

After 2-week room-temperature annealing

1u_60 600_60 480_60 360_60 240_60 120_60

Shi

ft of

|Vth| (

mV

)

Dose (Mrad(SiO2))Results from Padova

See Steven today’s presentation


9RD53 WG1 (Radiation test/qualification): Outlook

• CERN:

Annealing studies on Ring oscillator & Shift register & SRAM

• CPPM:

New test interface and software. Hardware compatible to low temperature operation at CERN X-ray machine

• Padova:

10-keV X ray irradiation of 65 nm CERN test structures

Setup of low temperature operation at Padova 3-MeV proton environment

• Fermi lab:

Data analysis and annealing tests of 65 nm transistors (2-week Co-60 γ ray irradiation just finished)

• Others…


10Analog WG

Evaluation, design and test of appropriate low power analog pixel Front-Ends

Convener: Valerio Re, Bergamo/Pavia

Activities and status Analog front-end specifications

Planar, 3D sensors, capacitance, threshold, charge resolution, noise, deadtime, ,

Alternative architectures –implementations to be compared, designed and tested by different groups TOT, ADC, Synchronous, Asynchronous, Threshold adjust, Auto

zeroing, etc.

Design / prototyping of FE’s ongoing

Plans Prototyping and test (with radiation) different FEs

Some FEs have already been prototyped

Others will be prototyped after the summer

Test, comparison and choice of most appropriate FE(s)

Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab, LBNL, Prague IP/FNSPE-CTU, Torino.

Krummenacher – TOT examples

Noi

se (e

- )Ikrum (nA)

28μm

15μ

m


11Simulation/verification WG

Simulation and verification framework for complex pixel chips

Convener: Tomasz Hemperek, Bonn

Activities and status Simulation framework based on system Verilog and UVM

(industry standard for ASIC design and verification) High abstraction level down to detailed gate/transistor level

Benchmarked using FEI4 design

First basic version of framework available on common repository Internal generation of appropriate hit patterns

Used for initial study of buffering architectures in pixel array

Integration with ROOT to import hits from detector simulations and for monitoring and analysing results.

Plans Refine/finalize framework with detailed

reference model of pixel chip

Import pixel hit patterns from detector Monte-Carlo simulation

Modelling of different pixel chip architectures and optimization

Verification of final pixel chip

Bonn, CERN, Perugia

Buffer occupancy comparison between simulation and analytical statistical model


12IP WG

Make IP blocks required to build pixel chips. ABOUT 30 IP-block identified

Convener: Jorgen Christiansen, CERN

Activities and status List defined and assigned to groups Defining how to make IPs appropriate for integration into mixed signal design

flow for full/final pixel chips CERN design flow

Design of IP blocks have started

IMPORTANT first IP-review made in July

IP-REVIEW expert PANEL defined

Plans Common IP/design repository Prototyping/test of IP blocks 2014/2015 IP blocks ready 2015/2016

~All RD53 institutes


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IP-block schedule


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1) I/O: Evaluation and definition of I/O protocols supporting 2Gbps or higher serial links, command based triggering up to 1MHz rate and minimum dead-time. - 80Mbps or higher serial input, with command decoder to configure and

operate the chip. Evaluation of a slow control protocol.

Command and Clock should be encoded on a single line.

- 2Gbps Serial Output links will require to evaluate different output data formats and compression alternatives.

- A duplex solution where all I/O takes place on a single serial connection should be considered. Investigation of link redundancy schemes to be eventually used on less data demanding layers.

2) Interfaces: Evaluation of compatibility with defined interfaces such as LPGBT.

3) IP blocks related to I/O: interface driver, clock recovery, clock multiplier methods, LVDS driver and receivers. [Work to be shared with the IP group]

4) Off chip connectivity: Calculation, Simulation and Test of transmission performance with realistic interconnects. I/O should not stop at the chip pads but extend to the system immediately outside the chip. High speed cables and protocols and even test interfaces. Therefore we should develop a specification for the system around it and a test setup.

I/O groupResponsabile R. Beccherle


15Top level WG

Global architecture and floor-plan issues for large mixed signal pixel chip

Convener: Maurice Garcia-Sciveres, LBNL

Activities and status Global floorplan issues for pixel matrix

50x50um2 – 25x100um2 pixels with same pixel chip ATLAS – CMS has agreed to initially aim for this

Global floor-plan with analog and digital regions

Appropriate design flow Column bus versus serial links Simplified matrix structure for initial pixel array test chips

Plans Submission of common simplified pixel matrix test chips

Evaluation of different pixel chip (digital) architectures Using simulation frameworks from simulation WG.

Final integration of full pixel chip

Bonn, LBNL, other institutes will soon be active


16Summary

RD53 has gotten a good start Organization structure put in place Technical work in WGs have started

The development of such challenging pixel chips across a large community requires a significant organisation effort.

Radiation tolerance of 65nm most important to be determined Design work has started in 65nm (FEs, IPs) - MORE info will come from

circuits irradiation Operating temperature and Annealing effects/scenario to be

understood

RD53 is now a recognized collaboration requested to report in relevant HEP/pixel meetings, conferences and workshops: ATLAS/CMS meetings ACES2014: https://aces.web.cern.ch/aces/aces2014/ACES2014.htm Front-end electronics workshop: http://indico.cern.ch/event/276611/overview Pixel/Vertex

Funding for RD53 work starts to materialize in institutes

CMS and ATLAS rely fully on RD53 for their pixel upgrades

https://aces.web.cern.ch/aces/aces2014/ACES2014.htm

https://aces.web.cern.ch/aces/aces2014/ACES2014.htm

http://indico.cern.ch/event/276611/overview

http://indico.cern.ch/event/276611/overview


17

BACKUP SLIDES


18

Focused R&D: Pixel Upgrades Phase1 upgrades: Additional pixel layer, ~4 x hit rates

ATLAS: Addition of inner B layer with new 130nm pixel ASIC (FEI4)

CMS: New pixel detector with modified 250nm pixel ASIC (PSI46DIG)

Phase2 upgrades: Installation: ~ 2022 Final CHIP ready for ~2017-18 Relies fully on significantly improved performance from next

generation pixel chips

CMS & ATLAS phase 2 pixel

upgrades

ATLAS Pixel IBL

CMS Pixel phase1

100MHz/cm2

400MHz/cm2

1-2GHz/cm2


19

Phase 2 pixel challenges ATLAS and CMS phase 2 pixel upgrades very

challenging Very high particle rates: 500MHz/cm2

Hit rates: 1-2 GHz/cm2 (16 higher than current pixel detectors)

Smaller pixels: ¼ - ½ (25 – 50 um x 100um) Increased resolution

Improved two track separation (jets)

Increased readout rates: 100kHz -> 1MHz Low mass -> Low power

Very similar requirements (and uncertainties) for ATLAS & CMS

Unprecedented hostile radiation: 10MGy(1Grad), 1016 Neu/cm2 Hybrid pixel detector with separate readout chip and

sensor. Phase2 pixel will get in 1 year what we now get in 10

years Participation in first/second level trigger ?

A. 40MHz extracted clusters and shape (outer layers) ?

B. Region of interest readout for second level trigger ?

Very complex, high rate and radiation hard pixel readout chips required

rd53 status report – july 2014 l. demaria - report on rd53 - cmstk week 22-07-20141

Documents

rd53 cmstk week

rd53 meeting

demaria report

rd53 outlook2014

cern cms

chipix65 rd53 status

release of cern

psi rd53 institutesl