~ Pergamon Solid-State E/ectronics Vol. 37. Nos 4-6, pp. 1001-1004, 1994

Copyright ~ 1994 Elsevier Science Ltd Printed in Great Britain, All rights reserved

0038-1101/94 $6.00+ 0.00

QUASI ONE-DIMENSIONAL IN-PLANE-GATE FIELD-EFFECT-TRANSI STOR

U. MEINERS l, H. BRUGGER I, B. E. MA1LE l, C. Wt)LK j and F. Koch: t Daimler-Benz AG, Forschungszentrum Ulm, D-89081 Ulm, Germany and

2Physik-Department, TU Miinchen, D-85748 Garching, Germany

Abstraet--A new type of a quasi one-dimensional planar field-effect-transistor (FET) with two lateral and symmetric in-plane-gate electrodes (IPG) is realized. The vertical layer sequence consists of a GaAs/AIGaAs heterostructure and a 6-doped pseudomorphic InGaAs quantum well with a high-density two-dimensional electron gas (2DEG). The device configuration results in a strong lateral concentration of the confining electric field in the 2DEG plane. The fabricated devices operate excellently at room temperature with maximum currents (IDs) above 0.3 mA and transconductance (gin) values of 0.2 mS. Perfect pinch-off is achieved by a negative gate-voltage. Devices with planar arrays of quasi one-dimen- sional channels exhibit 1DS > 6 mA and gm= 5 mS. A PMMA electron beam lithography process followed by a selective isolation implantation is used for the fabrication of IPG-FET devices.

I. INTRODUCTION

Low dimensional transport properties are intensively investigated for future electronic and optoelectronic device applications. In a one-dimensional electron- gas ( IDEG) system a drastic suppression of the scattering rate was predicted theoretically by Sakaki[l]. The expected mobilities should be well beyond the values of a corresponding two-dimen- sional electron-gas (2DEG) system. One of the many novel device structures being investigated today is a quasi - lDEG field-effect-transistor (FET) with a lat- eral in-plane-gate (IPG) electrode configuration which was first proposed and demonstrated by Wieck and Ploog[2]. The expected reduced scattering rate in one-dimensional channels and the inherent low gate/channel-capacitance of the IPG structure makes this type of device very promising for high speed operation. The fully planar device configuration and the simple fabrication process offers the possibility of in situ epitaxial regrowth for multi-functional three- dimensional integration. IPG-FETs have already been realized by trench etching isolation with reactive ion etching[3] and resistive p-type barrier isolation by focused-ion-beam (FIB) implantation of Ga ions[4-6].

In this paper we report about a novel IPG-FET and a selective isolation implantation technique for fabricating planar device structures. Starting from an MBE-grown AIGaAs/GaAs heterostructure with a pseudomorphic InGaAs 2DEG-layer quasi - lDEG channels are formed by two closely spaced isolation barriers. The fabricated devices operate excellently at room temperature. Current levels of > 0 . 3 m A and transconductance values of 0.2 mS are realized on single-channel devices. These are to our knowledge

the highest ever reported values on one-dimensional FETs. Perfect pinch-off is achieved at a gate voltage of VGs = - 2 V. On IPG-FETs with multiple quasi IDEG channels device source-drain currents above 6 mA and maximum transconductance values of 5 mS are realized. The electrical isolation of the gate-elec. trodes from the channel region is realized by a selective dual energy implantation with single charged boron ions. The achieved resistance of > 109 f~/sq, is higher than the corresponding value of the used semiinsulating substrate and yields to a very low gate leakage current density and to a high break-down voltage.

2. LAYERED STRUCTURE AND DEVICE FABRICATION

A schematic illustration of the device layout is shown in Fig. I together with a cross-sectional view of the intrinsic part of the device. The vertical layer sequence consists of an MBE-grown pseudomorphic GaAs/InGaAs/AIGaAs heterostructure with a high- density 2DEG. Details about the epitaxial layers are summarized in Table 1. To improve carrier confine- ment and to enhance the 2DEG electron density in the quantum well (QW) a pseudomorphic InGaAs layer was used as a channel material. The InGaAs QW is 6-doped with a nominal Si concentration of 2 × 10 ~2 cm -2. A thin top-side and moderately doped AIGaAs barrier region is incorporated for a strong 2DEG confinement. A final, thin and highly doped GaAs cap-layer is used for the fabrication of low- resistance ohmic contacts. A surface-depleted hetero- structure is used for device fabrication in order to avoid any parallel conductance through the cap layers. The 2DEG carrier density (n~) and mobil- ity (ttH) were measured by Hall effect. Typical

1001

1002

quasi 1 DEG

Gate Gate Ohmic ~--J ] ' / ' ":~"=~" '"=~"'v I~--~ C°ntacts

l,V,= 2 DEG Isolation Lines

Fig. I. Schematics of the IPG-FET device. The quasi one-dimensional channel conductance is controlled by a

lateral electric field via two symmetric gate electrodes.

U. MEINERS et al.

0.4

values are n, = 1.7 x 10 ~2 cm 2 and/all = 2060 cm2/Vs at 300 K.

As shown in Fig. 1 the IPG-FET devices are defined by wet chemically etched mesa squares (12 x 12 #m) which contain source (S), drain (D) and two symmetric gate (G) electrodes. The ohmic con- tacts are fabricated by photolithography and stan- dard alloyed NiGeAu metallization. The quasi one-dimensional current channel is realized in the centre of the mesa by a small spacing between two thin V-shaped isolation lines along the mesa diagonal. The isolation regions are fabricated in the following way: the wafers are covered with a 0.6/am thick polymethyl methacrylate (PMMA) resist layer. E-beam lithography is used for patterning the PMMA layer without a spatial dose variation to correct proximity effects. The resist pattern acts as a mask for the following implantation process. A dual implantation by boron ions is used with two different energies of 25 and 80keV and dose values of 5 x l0 ~-" and 5 x 10 H cm -2, respectively, for the isolation. A high resistance behaviour is achieved by damage-induced carrier trapping in the implanted regions. The measured sheet resistance on test structures is beyond 109~/sq. which is higher than the corresponding resistance of the used semi-insulating GaAs-substrate. The ion ener- gies and dose values are optimized with the help of

Table l, MBE layer sequence used for the fabrication of IPG-FET devices

Layer Material Thickness Si-doping

Cap GaAs 10nm 5 x 1018cm -3 Barrier A1025Ga075As 20nm 5 x 1017cm -3 Quantum well Ino2GaosAs 12nm 2 x 1012cm -2 Buffer GaAs 750 nm Undoped Superlattice AIAs/GaAs 2 nm/2 nm Undoped

The substrate temperature was 620 C up to the growth of the buffer layer and was reduced to a value of 530°C for the growth of the final heterostructure layers.

IPG-FET (Single Channel) VGS 6/) #R68212 ~ +0.5

0.3 IPG-S 0.0

< g02o, ~ -05 0,1 -1.0

-1.5 0 - , , , 20 0 1 2 3 4 5

VDS (V)

Fig. 2. Room temperature I/V characteristics of a single- channel IPG-FET in the dark.

a Monte-Carlo simulation[7] to achieve extremely high resistances.

Realized isolation line widths (w~) are in the range between 100 nm and 1.1/~m. The quasi one-dimen- sional channel width (web) is varied between 200 nm and 2.0/am. Outside the channel region wider iso- lation lines are used to minimize the capacitance and to reduce the leakage current as can be seen in Fig. 1. The effective isolation line width is expected to be larger than the geometrical width wi due to lateral straggling effects during the implantation and due to lateral depletion zones between the implanted regions and the channel. The 0.6/~m thick PMMA resist absorbs completely the high energy boron ions and protects the underlying semiconductor material to be damaged. For the fabrication of multi-channel devices a series of single-channels is connected in parallel by use of an airbridge technology. Details about the process technology are published else- where[8].

3. EXPERIMENTAL RESULTS

A typical transistor room temperature current/ voltage (I/V) curve is shown in Fig. 2. The IPG-FET device consists of only one single IPG-FET with a nominal width of Wch = 2.0 #m and an isolation line width of w~ = 0.4#m. The channel is nearly totally pinched-off by a gate voltage of Vos = - 2 V. A very low gate leakage current of < 70 nA is measured even for lids = 6 V and VGs = - 2 . 5 V. This is attributed to the excellent resistivity of the gate isolation region. The d.c. I/V performance was measured by a HP 4145B parameter analyser with the device in the dark. The IPG-FET exhibits a maximum measured source/drain current (IDs) of above 0.3 mA in the saturation range and a maximum transconductance (gin) of 200 pS at a gate voltage of VGs ~ 0 V. These are to our knowledge the highest ever reported values for an IPG-FET device.

The devices realized by the reported selective iso- lation implantation technique operate in a depletion mode. The transistor can be slightly enhanced by a positive gate voltage. The excellent controllability of

Quasi one-dimensional IPG-FET 1003

the channel conductance is attributed to the QW- doped 2DEG structure. By applying a negative gate voltage the electric field is directed in the plane of the 2DEG towards the quasi one-dimensional channel as can be seen schematically in the lower part of Fig. 1. In the proposed surface-depleted vertical layer se- quence there exist no free charges in the AIGaAs and GaAs layers and therefore the conductance is strictly limited to the thin 2DEG QW layer. This yields to a nearly perfect lateral field-effect.

Experiments on conventional modulation-doped 2DEG samples have shown significantly lower transconductance values and reduced maximum cur- rent levels of the IPG-FET device. Only for wch ~< l #m a complete depletion is achieved by a negative gate voltage. For W~h > ! /am a gate/drain breakthrough occurs before pinch-off. Therefore a more effective lateral field-effect is expected in QW- doped structures in comparison with modulation- doped heterostructures.

The maximum channel current and the device transconductance are directly influenced by the spac- ing of the insulating barriers which determines the width of the channel region. In Fig. 3 the measured functional dependence of IDS (VDs "~- 4 V, VGs = 0) and gm on the nominal channel width (W~h) is shown. The curves are obtained from devices with a constant isolation line width of w~ = 0.4/am and the measure- ment performed in the dark. With increasing number of carriers in the channel also the transconductance increases steadily with wider w¢h. At a nominal width of w¢h ~ 350 nm the channel is completely depleted even for VGs = 0 V. Therefore the effective electrical width of the channel is expected to be 350 nm smaller than the nominal one. This is attributed to the lateral straggling of the boron ions during the implantation process and due to lateral depletion zones between the isolated regions and the conductive channel. Additional experiments on the dependence of los and gr, on the isolation width have shown that w~ has only a minor influence on the device performance. An IPG-FET device with web = 0.6/am and w i = 0.6/am

350 Boron I r t~ lm3t~iOl l - "/~' t , - " e 2OO

Asoo , , j, , , , -- v ' " ..... ~"

8 250 j ~ / y " I 150 - - :: : 2 D E G . )~" / "

200 ,,~ .......

~- ,'" " .... : " loo~ ~150 &" ," • ~ T = 3 0 0 K

,~ ,oo 8= ca 350 n m # " , Iv" t. gm ,,-. ,- • i o s 5 0 ¢~

% - ' ';,oo"'" ~o 12'oo I~o 2o~ o Channel Width w= (nm)

Fig. 3. Measured source/drain-currents at Vns = 4 V and VGs = 0 V and maximum transconductance values of single- channel IPG-FETs as a function of the channel width in the

dark. The isolation barriers are w~ = 0.4 gin.

IPG-FET (Multi Channel) Vc, s (v) 0.5

#R836/1 6 c~..4s-i , ~ 0.0

Z , "

• --~ -1.0 2

-1.5

0 ~ - -2.0 0 1 2 3 4 5

VDS (V) Fig. 4. Room temperature I / V characteristics of a multi-

channel IPG-FET (planar array of 48 channels).

exhibits an enhancement of gm by about 20% if the isolation width is reduced to w~ = 100 nm.

In the saturation range of the operating transistor the observed linear dependence of IDS on Web can simply be described by the following formula[4]:

IDS=e X ns x W*h X t,~t , (1)

with the electronic charge e, the 2DEG carrier density n, ,w*h = (wch -- 350 rim) as the effective electronic channel width and the saturation velocity v,~,. From the experimental data in Fig. 3 and the measured two-dimensional carrier density n s = 1.7 x 10 ~2 cm -2 a saturation velocity of v~t= 0.9 x 107cm/s is ob- tained from eqn (1). This value is close to the expected saturation velocity in GaAs material at high electric fields (~ 10 7 cm/s).

In Fig. 4 the I / V performance of a multi-channel device with 48 single channels in parallel is demon- strated. Maximum current levels above 6mA are observed. The electrical connection of individual quasi one-dimensional channels is realized by micro- airbridges in a coplanar design. The maximum ob- served transconductance is 5 mS. Perfect pinch-off is achieved for gate voltages VGS = --2.5 V. The indi- vidual channels are fabricated with Wch = 0.8/am and w~ = 0.6 gm. The current level and the transconduc- tance value of the multi-channel device directly scales with the number of the quasi-lDEG channels con- nected in parallel. This demonstrates the high per- formance of the used technology in fabricating this new type of FET device, Also the gate leakage current of the multi-channel device is < 1 #A at an applied gate voltage of VGS = --2 V and VDS = 5 V. A maxi- mum source/drain voltage of VDs=9V at VGs = - 3 V can be applied before gate-drain break- through occurs. Due to the intrinsic current limi- tations of 1DEG FETs a parallel conducting matrix-array arrangement is necessary to push the current in the mA-range for real device applications, where higher power levels are required.

The maximum available speed of the IPG-FET device is expected to be limited by extrinsic parasitic components and internal capacitances (CGD). There-

1004 U. MEINERS et al.

fore the overall dimensions of IPG-FET devices (especially the multi-channel configuration) should be kept as small as possible and a low loss connecting transmission line network is necessary to minimize extrinsic capacitances and resistors. Otherwise the inherent advantage of this novel quasi-I DEG FET (a very small gate capacitance) is dominated and limited by extrinsic effects. A detailed analysis on speed limiting effects in IPG-FET devices is performed by high frequency characterization experiments and will be published elsewhere.

4. CONCLUSION

A selective isolation implantation technique is used for a successful fabrication of a fully planar quasi one-dimensional FET with in-plane gates. A strong lateral electric field concentration is achieved by a QW-doped 2DEG layer sequence. Highest room tem- perature transconductance values of 0.2 mS and maximum channel currents of > 0.3 mA are realized on single-channel devices. The high performance of

the used technology is demonstrated on devices with a planar array of parallel conducting channels yield- ing IDs > 6 mA and gm= 5 mS.

Acknowledgement--The work was partially supported by the Bundesministerium for Forschung und Technologie (Bonn, Germany) under contract number 01 BM 120/7.

REFERENCES

1. H. Sakaki, Japan. J. appl. Phys. 19, L735 (1980). 2. A. D. Wieck and K. Ploog, Appl. Phys. Lett. 56, 928

(1990). 3. J. Nieder, A. D. Wieck, P. Grambow, H. Lage,

D. Heitmann, K. v. Klitzing and K. Ploog, Appl. Phys. Lett. 57, 2695 (1990).

4. A. D. Wieck and K. Ploog, Appl. Phys. Lett. 61, 1048 (1992).

5. Y. Hirayama, Appl. Phys. Lett. 61, 1667 (1992). 6. J. A. Adams, L. M. Templeton, E. V. Kornelson and

S. P. McAlister, Proc. Int. Semiconductor Device Res. Syrup., Charlottesville, U.S.A. 445 December (1991).

7. J. Ziegler, J. Biersack and V. Littmark. Doping and Range of Solids. Pergamon Press, New York (1985).

8. U. Meiners, B. E. Maile and H. Brugger, to be pub- lished.