Quadrature Phase Shift Keying

Quadrature Phase Shift Keying (QPSK) is a form of Phase Shift Keying in which two bits are taken at a time and modulated, selecting one of four possible carrier phase shifts (0, 90, 180, or 270 degrees). QPSK allows the signal to carry twice much information than ordinary PSK, using the same bandwidth. QPSK is used for satellite transmission of MPEG2 video, cable modems, videoconferencing, cellular phone systems, and other forms of digital communication over an RF carrier.

HARDWARE IMPLEMENTATION

Design a 555 clock generator at a frequency of 12 kHz. Construct a divide by 4 Johnson counter using JK flip flops to generate four phases of square waves. The four phases are given to four second order LPFs to obtain two sine waves (+sine, -sine) and two cosine waves (+cosine, -cosine). Finally, those four signals are given to the 4:1 multiplexer (4052). Design a 3-bit PRBS generator using 4013-D Flip Flops. The clock for this data generator is from Q1 of Johnson counter as shown in the block diagram. The select lines of 4052 are connected to the PRBS generator. The 4052output is the desired QPSK signal.

BLOCK DIAGRAM

S1 S0 Y CARRIER PHASE

0 0 X0 SINE

0 1 X1 -SINE

1 0 X2 COS

1 1 X3 -COS

CLOCK FROM IC 555

R17

1k

R1810k

C9

0.01uf

R4

DC 7

Q 3

GN

D1

VC

C8

TR2 TH 6

CV5

IC 555

555

C100.01uF

CLOCK SIGNAL OUTPUT

U(VCC) +12 V

OUTPUT WAVEFORM

The clock signal can be generated by IC 555, operating in the Astable mode. The frequency of that clock signal can be calculated by

f= 1/t

t=0.69 RC

t=0.69 (10k) (0.01uf)

f=14.492 kHz

JOHNSON COUNTER (DIVIDE BY FOUR)

The Johnson counter (÷ by 4) can be designed using JK Flip Flop as shown in figure to generate the four phases of square waves.

OUTPUT WAVEFORM

CMOS JK FLIP FLOP (4027)

CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master slave flip-flops. Each flip-flop has provisions for individual J, K, Set Reset, and Clock input signals. Buffered Q and ̅Q̅ ̅ signals are available as outputs. The CD4027BMS is supplied in these 16-lead outline packages:

SECOND ORDER LOW PASS FILTER

The second order Low pass filter can be constructed using op-amp as shown in figure, to convert the square wave into sine waveform. We need to convert the square wave of four different phases, so, we can use LM 324 (Quad op-amp), which consists of four op-amps within a single DIP chip.

QUAD OP AMP (LM324)The LM324 series has quad op-amps with true differential inputs. The quad amplifier can operate at supply voltages as low as 3.0 V or as high as 32 V. FEATURES

Short Circuited Protected Outputs True Differential Input Stage Single Supply Operation: 3.0 V to 32 V (LM224, LM324, LM324A) or + 16V Four Amplifiers Per Package

PINOUT OF LM324

SQUARE WAVE INPUT FROM JOHNSON COUNTER

SINUSOIDAL OUTPUT

3

26

74 1 5

U3

741

R9

1.5k

R10

1.5k

R11

560

R12

1k

C50.1uf

C6

0.1uf

+12 V (V+)

-12 V (V-)

C7

0.1uf

OUTPUT WAVEFORM OF LM324 (PIN NUMBER 1 AND 7)

OUTPUT WAVEFORM OF LM324 (PIN NUMBER 8 AND 14)

OUTPUT WAVEFORM

PRBS DATA GENERATOR

CLOCK SIGNAL INPUT FROM Q1 OF JOHNSON COUNTER

D5 Q 1

CLK3

Q 2

R4

S6 IC1:A

4013

D9 Q 13

CLK11

Q 12

R10

S8 IC1:B

4013

D5 Q 1

CLK3

Q 2

R4

S6 IC2:A

4013

1

23

IC:A

4030

OUTPUT WAVEFORM OF CLOCK AND PRBS

CMOS 4:1 MULTIPLEXER (4052)

The CD4052 analog multiplexers demultiplexers are digitally controlled analog switches. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3−15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0−5V. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs.

Features: Wide range of digital and analog signal levels: digital 3 to 15V, analog to 15Vp-p

( +7.5V). Logic level conversion for digital addressing signals of 3 – 15V (VDD − VSS = 3 – 15V)

to switch analog signals to 15 Vp-p (VDD − VEE = 15V). Very low quiescent power dissipation under all digital-control input and supply

conditions: 1 μ W (typ.) at VDD − VSS = VDD − VEE = 10V. Binary address decoding on chip.

X012

X114

X215

X311

Y01

Y15

Y22

Y34

A10

B9

INH6

X 13

Y 3

IC

4052

FROM PIN 1 OF LM324FROM PIN 7 OF LM324FROM PIN 8 OF LM324FROM PIN 14 OF LM324

FROM PRBS

QPSK OUTPUT

Based on the selection lines the IC 4052 selects the appropriate input as shown in the waveform.

COMPLETE CIRCUIT DIAGRAM

QAM

R17

1k

R18

10k

C9

0.01

uf

R4

DC

7

Q3

GND 1VCC8

TR2

TH6

CV

5

IC 5

55

555

C10

0.01

uF

U(V

CC

) +12

V

J6

Q1

CLK

3

K5

Q2

S7 R 4

IC 4

027:

A

4027

J10

Q15

CLK

13

K11

Q14

S9 R 12

IC 4

027:

B

4027

3 26

7 415

U1

741

R1

1.5k

R2

1.5k

R3

560

R4

1k

C1

0.1u

f

C2

0.1u

f

+12

V (V

+)

-12

V (V

-)

3 26

7 415

U2

741

R5

1.5k

R6

1.5k

R7

560

R8

1kC3

0.1u

f

C4

0.1u

f

U2(

V+)

U2(

V-)

3 26

7 415

U3

741

R9

1.5k

R10

1.5k

R11

560

R12

1kC5

0.1u

f

C6

0.1u

f

U3(

V+)

U3(

V-) 3 2

6

7 415

U4

741

R13

1.5k

R14

1.5k

R15

560

R16

1kC7

0.1u

f

C8

0.1u

f

U4(

V+)

U4(

V-)

X012

X114

X215

X311

Y01

Y15

Y22

Y34

A10

B9

INH

6

X13

Y3

U5

4052

D5

Q1

CLK

3

Q2

R 4S6 IC1:

A

4013

D9

Q13

CLK

11

Q12

R 10S8 IC1:

B

4013

D5

Q1

CLK

3

Q2

R 4S6 IC2:

A

4013

123

IC:A

4030

QPS

K

OU

TPU

T

Quadrature Amplitude Modulation, QAM utilizes both amplitude and phase components to provide a form of modulation that is able to provide high levels of spectrum usage efficiency.

QAM, Quadrature Amplitude Modulation is in analogue transmissions, AM stereo transmissions, and data applications. It is able to provide a highly effective data compression and it is used in cellular phones, Wi-Fi and all high speed data communications systems.

QAM is a signal in which two carriers shifted in phase by 90 degrees (i.e. sine and cosine) are modulated and combined. As a result of their 90° phase difference they are in quadrature and this gives rise to the name. Often one signal is called the In-phase or “I” signal, and the other is the quadrature or “Q” signal.

The resultant overall signal consisting of the combination of both I and Q carriers contains of both amplitude and phase variations. In view of the fact that both amplitude and phase variations are present it may also be considered as a mixture of amplitude and phase modulation.

HARDWARE IMPLEMENTATION

Refer the Block diagram. First of all, we have to obtain four different amplitude levels of sine signal by applying the same input signal to the 4 op amps with different gain output. The op amps provides signal with four different amplitude levels and the same is applied to op amps in next stage to get 90 degree phase shift of those 4 signals. All the 8 signals are applied to the 8:1 multiplexer. The select lines are connected with PRBS data generator for selecting the inputs randomly. The clock signal for the PRBS is generated by 555 timer, operating in Astable mode. Finally we will get the output as 4 different amplitudes as well as 2 different phase shifts.

S2 S1 S0 Y0 0 0 X00 0 1 X10 1 0 X20 1 1 X31 0 0 X41 0 1 X51 1 0 X61 1 1 X7

To generate the sine wave with four different amplitudes, we have to use four op-amps with different gains. The gain of an op-amp can be adjusted by varying the feedback resistance RF.

GAIN = RF / RIN and RP = RIN // RF

OP AMP WITH GAIN =1

3

26

74 1 5

IC1741

Sine input

U1(+12V)

U1(-12V)

RIN

10k

RF

10k

RP

5k

1V Sine output

OP AMP WITH GAIN =2

3

26

74 1 5

IC1741

Sine input

U1(+12V)

U1(-12V)

RIN

10k

RF

20k

RP

8.2k

2V Sine output

OP AMP WITH GAIN =3

3

26

74 1 5

IC1741

Sine input

U1(+12V)

U1(-12V)

RIN

10k

RF

30k

RP

8.2k

3V Sine output

OP AMP WITH GAIN =4

3

26

74 1 5

IC1741

Sine input

U1(+12V)

U1(-12V)

RIN

10k

RF

40k

RP

8.2k

4V Sine output

OUTPUT WAVEFORMS OF FOUR OP-AMPS

Instead of using four number of IC 741, we can use LM 324, which is having four op-amps in one single chip. So that we can reduce number of IC pins as well as component occupying space.

OUTPUT WAVEFORMS OF FOUR OP-AMPS OPERATED AS PHASE SHIFTER

OP AMP AS PHASE SHIFTER

3

26

74 1 5

IC1741

Sine input

U1(+12V)

U1(-12V)

RIN

10k

RF

10k

RP

5k

-Sine output

Finally, all the 8 sine signals are applied to the 8:1 multiplexer(IC 4051), and select lines are connected from PRBS to achieve QAM output.

QAM WAVEFORM

QAM applications

QAM is in many radio communications and data delivery applications. However some specific variants of QAM are used in some specific applications and standards.

For domestic broadcast applications for example, 64 QAM and 256 QAM are often used in digital cable television and cable modem applications. In the UK, 16 QAM and 64 QAM are currently used for digital terrestrial television using DVB - Digital Video Broadcasting. In the US, 64 QAM and 256 QAM are the mandated modulation schemes for digital cable as standardized by the SCTE in the standard ANSI/SCTE 07 2000.

In addition to this, variants of QAM are also used for many wireless and cellular technology applications. Here the link conditions can vary and accordingly the order of the QAM modulation used can normally be altered dynamically with the level of error correction to achieved the best throughput. This means balancing the QAM order with the level of error correction against the prevailing link conditions. As data rates have risen and the demands on spectrum efficiency have increased, so too has the complexity of the link adaptation technology. Data channels are carried on the cellular radio signal to enable fast adaptation of the link to meet the prevailing link quality and ensure the optimum data throughput, balancing transmitter power, QAM order, and forward error correction, etc.

Minimum Shift Keying 

Minimum shift keying, MSK, is a form frequency modulation, based on a system called continuous-phase frequency-shift keying. Minimum shift keying (MSK) offers advantages in terms of spectral efficiency when compared to other similar modes, and it also enables power amplifiers to operate in saturation enabling them to provide high levels of efficiency.

It is found that PSK waveform has sharp phase changes as shown in figure. These transitions potentially create signals that have sidebands extending out a long way from the carrier, and this creates problems for many radio communications systems, as any sidebands outside the allowed bandwidth cause interference to adjacent channels and any radio communications links that may be using them.

MSK, minimum shift keying has the feature that there are no phase discontinuities and this significantly reduces the bandwidth needed over other forms of phase and frequency shift keying.

The problem can be overcome in part by filtering the signal, but is found that the transitions in the data become progressively less sharp as the level of filtering is increased and the bandwidth reduced. To overcome this problem GMSK is often used and this is based on Minimum Shift Keying,

FIG. 1 MSK Modulation

3 26

7 415

U1

741

R1

10k

1.5

KH

z

R2

10k

+5V

-5V

R3

10k

3 26

7 415

U2

741

R4

10k

R5

10k

R6

10k

+5V

-5V

750

Hz

90' P

S

D5

Q1

CLK

3

Q2

R 4S6

U3:

A

4013

D9

Q13

CLK

11

Q12

R 10S8

U3:

B

4013

D5

Q1

CLK

3

Q2

R 4S6

U4:

A

4013

A B C D

1.5

KH

z (C

LK)

D9

Q13

CLK

11

Q12

R 10S8

U4:

B

4013

D5

Q1

CLK

3

Q2

R 4S6

U6:

A

4013

D9

Q13

CLK

11

Q12

R 10S8

U6:

B

4013

123

U7:

A

4030

X013

X114

X215

X312

X41

X55

X62

X74

A11

B10

C9

INH

6

X3

U5

4051

Fig. 2. MSK Modulation

MSK is a particularly effective form of modulation where data communications is required. Although QAM and PSK are used for many other systems, MSK is able to provide relatively efficient spectrum usage. As it is a form of frequency modulation, this enables RF power amplifiers to operate in saturation, thereby enabling them to operate as efficiently as possible. If amplitude variations are present these need to be preserved and amplifiers cannot run in saturation and this significantly limits the efficiency levels attainable.Procedure:

1. Generate PRBS data and clock pulses of 1.5 KHz.2. Split the even and odd mode streams of PRBS data using splitter circuit which is shown in Fig.1

3. Using two function generators to generate 1:2 ratio frequency like 750Hz (fLow), 1.5KHz (fHigh) individually

4. The low frequency should have 90 degree phase shift while generation.5. Use inverting op-amp for generating 180o phase shift of fLow and fHigh

6. From the splitter circuit, connect the odd and even streams (S0 and S1) to the address pins of 4051 (S0,S1)

7. From the op-amps and function generator, there will be 4 different inputs to the multiplexer. Like fLow and fHigh and their inverted phase.

8. Follow the table below and connect the inputs of multiplexer accordingly

Even 0 1 0 1Odd 0 0 1 1

Signal frequency High Low Low HighSignal

Polarization-ve -ve +ve +ve

9. The MSK O/P should be as shown in Fig. 2. The waveform should have no kinks or discontinuities in the MSK waveform.

Model Waveform

Alternate Mark Inversion (AMI)Look at the figure. In AMI, the ZEROs in the input stream are undisturbed and sent as ZEROs. Whenever the input is ONE, the alternate ONEs are inverted with respect to each other. In other words, the first ONE in the input is sent as a +1 and the second ONE is sent as a -1 and so on.

AMI (Alternate Mark Inversion) is a synchronous clock encoding technique which uses bipolar pulses to represent logical 1 values. It is therefore a three level system. A logical 0 is represented by no symbol, and a logical 1 by pulses of alternating polarity. The alternating coding prevents the build-up of a d.c. voltage level down the cable. This is considered an advantage since the cable may be used to carry a small d.c. current to power intermediate equipment such as line repeaters.

HARDWARE IMPLEMENTATION

The RZ data output from AND gate is fed to a AMI flip flop. The successive ONEs at the clock toggle the flip flop. The zeros will not toggle the flip flop.

It is obvious, for all odd ones (1, 3, 5, etc) Q will be ONE and for all even ones (2, 4, 6, etc) ̅Q̅ will be ONE. Thus odd ONEs stream and even ONEs streams are separated.

1

23

IC1:A4081CLOCK FROM 555

DATA FROM PRBS RZ DATA

D5 Q 1

CLK3

Q 2

R4

S6 IC2:A

4013

X1 Y 2

C13

IC3:A 4066

X11 Y 10

C12

IC3:B 4066

X4 Y 3

C5

IC3:C 4066

X8 Y 9

C6

IC3:D 4066

R210k

R3

11k

R4

11k

+5V

-5V

AMI OUTPUT

Switches IC3-A and IC3-B are deal with “Odd ONEs” Stream. Switches IC3-C and IC3-D are deal with “Even ONEs” Stream. IC3 –A and IC3-B form an AND gate and IC3-C and IC3-D form another AND gate. The output will be a +5V pulse if the RZ data AND “Odd ONEs” stream is ONE. The output will be -5V pulse if the RZ data AND “Even ONEs” stream is ONE.

Manchester Encoding

Manchester encoding uses inversion at the middle of each bit interval for both synchronization and bit representation. In the IEEE 802.3 standard a negative to positive transition represents binary 1 whereas a positive to negative transition represents binary 0.

HARDWARE IMPLEMENTATIONIn the Manchester coding, for every input bit, there is a transition (high-to-low or low-to-high) in the centre of the bit duration. In our implementation for input bit 1, a low-to-high transition will happen and for input 0, a high-to-low transition will happen.

Fig 1. Logic ‘1’ &’0’ scheme

Model Waveform

Fig 2. 15 Bits PRBS Data Generation

Fig.3 Manchester Encoding

For an input bit as 1, the Manchester coder output has a –ve going transition (1 to 0) in the middle of the data

Similarly for an input 0, the Manchester coder output has +ve going transition (0 to 1) in the middle of the data