power gating design implementation with tapless cells

Power Gating Design Implementation With Tapless Cells –

What You Need To Know

Kaijian Shi Synopsys Professional Services

Dallas, USA

[email protected]

David Tester

Structured Custom

Cambridge, UK

[email protected]

ABSTRACT

65nm and beyond CMOS designs are commonly implemented with tapless library cells which do

not have built-in well taps. To maintain proper transistor back biasing and prevent latch-up,

special tap cells need to be inserted at intervals satisfying the tap rules. In power-gating designs,

the tap cell insertion becomes complicated due to not only co-existence of always-on and power-

gated domains but also different supply voltages applied to different domains. This paper

describes a domain-based tap insertion methodology and implementation techniques to ease the

complicity and minimize risks of incorrect tap insertions in power gating designs.

mailto:[email protected]

SNUG 2011 Power Gating Design Implementation With Tapless Cells

Table of Contents

1. Introduction ........................................................................................................................... 3

2. Tapless design and conventional tap insertion method......................................................... 3

3. Tap insertion requirements in power-gating designs ............................................................ 5

1. ALWAYS-ON TAP CELL ........................................................................................................ 5

2. ALWAYS-ON WELL TAP POWER CONNECTIONS .................................................................... 6

4. Challenges in tap insertions in power-gating designs ........................................................... 6

1. DOMAIN-BASED TAP TYPE SELECTION ................................................................................ 6

2. DOMAIN-BASED TAP POWER LOGIC CONNECTIONS .............................................................. 6

3. DOMAIN-BASED TAP POWER PHYSICAL CONNECTIONS ........................................................ 7

4. OFF-GRID TAP INSERTION AND POWER CONNECTIONS ......................................................... 8

5. Domain-based tap type selection method ............................................................................. 8

6. Domain-based tap cell logic PG connection method ............................................................ 9

7. Domain-based tap cell physical PG connection method..................................................... 10

8. Off-grid tap insertion and power connections .................................................................... 12

9. Results ................................................................................................................................. 13

10. Summary ............................................................................................................................. 14

11. References ........................................................................................................................... 15

12. Author biographies.............................................................................................................. 15


1. Introduction

65nm and beyond CMOS designs are commonly implemented with tapless library cells for low

cost in silicon area. The tapless cells do not have built-in taps that connect n-well and p-substrate

to the power and ground rails. To prevent latch-up and maintain proper transistor back biasing,

special tap cells are inserted in the layout at the required interval to connect n-wells to VDD and

p-substrate to VSS based on tap rules defined in the technology DRC file.

In a traditional single voltage domain design standard cells are all connected to VDD and VSS

rails that are always active when the chip is powered on. As the result, the tap insertion in

traditional design was relatively easy and could be done reliably by the ICC tap insertion flow.

However, the tap cell insertion becomes complicated in power-gating designs which often

contain both always-on and shutdown blocks where power can be turned off. For a power-gating

block, special taps (always-on taps) are required to prevent latch-up and maintain proper

transistor back biasing when power supplies to the standard cells in the block are turned off,

while Power-Management (PM) cells in the block are active. Also, the tap cells need to be

logically and physically connected to the correct power supplies to ensure power integrity. As

the result, a domain-based PM tap insertion flow becomes both necessary and critical in a tapless

power-gating design until such an automated flow is implemented in ICC in the future. This

paper describes the domain-based tap insertion method and implementation techniques which

have been integrated in our low-power design flow and have been used successfully in a number

of production low-power designs.

In the rest of the paper, the normal tap design and tap insertion method are outlined first. Then,

special requirements for tap insertion in power-gating designs are outlined. Design of always-on

taps and challenges in the PM tap insertion are explained. Next, the domain-based PM tap

insertion method is described in detail with supporting scripts and an example is provided to

demonstrate the method.

2. Tapless design and conventional tap insertion method

In conventional CMOS designs, the n-wells of PMOS transistors are connected to the VDD

supply and the p-substrate of NMOS transistors is connected to the VSS supply to implement the

necessary transistor back bias connectivity and prevent potential latch-up problems. Until sub-

65nm, such well connections were often implemented by well taps contained within logic cells in

standard cell libraries. This simplified the DRC aspect of design closure since well and substrate

connections were taken care of in the standard cells and hence transparent to front-end chip

designers.

In 65nm and beyond, the well and substrate taps in the standard cells become a considerable area

overhead. To reduce area and silicon cost, library vendors remove taps from the standard cells.

Consequently “tapless” standard cells are commonly used in sub-65nm production designs.


To maintain required transistor back bias and prevent latch-up, n-well in a standard cell is

extended at cell boundary to form continuing wells when the standard cells (including filler cells)

are abutted in the design. The wells are connected to VDD and VSS supplies by tap cells inserted

at interval based on the tap rule defined by the technology to get well bias and prevent latch-up.

The tap cell is a simple standard cell which has an n-well tap connected to VDD rail and a p-

substrate tap connected to VSS rail as shown in Fig. 1.

Figure 1 – Typical Standard Cell Library Tap Cell

When integrated in the design, the tap cell VDD and VSS rails are aligned with the rails of the

design, as shown in Fig. 2, to connect VDD and VSS power supplies along the standard cell row.

Substrate and n-well connections are provided by taps within the tap cells. Tap insertion in

normal SOC design is not complicated since EDA tools usually provide a facility to insert the tap

cells and guarantee meeting tap rules defined in the technology DRC runset. In ICC, this is done

by the command add_tap_cell_array. Power connections of the taps are automatically provided

through the cell row VDD and VSS rails.

Figure 2 – Standard Tap Cell Implementation Example


3. Tap insertion requirements in power-gating designs

Power-gating design has become popular in sub-65nm designs to combat the increasingly large

leakage power from arising from technology scaling as transistor oxide thickness has decreased.

In the power-gating design, a power domain (usually containing several functional blocks) can

be shut down while other domains within the device are active.

In the power-gated block, VDD rails are controlled by switch cells and these power rails will be

floating when the switch cells are turned off. In the conventional tap insertion method, the n-

well connectivity is obtained through the tap cell VDD rail connections as shown in Fig. 1. Since

the power gated VDD rail is floating, the bias voltage for the n-well is not controlled (since the

local VDD voltage will decrease over time) and will lead to back-bias problems such as leakage

and latch-up for the transistors in the power-gated domain. Consequently, the conventional tap

insertion method is no longer appropriate in the power-gating design. To maintain n-well bias in

the power-gated block, we need a different tap cell (always-on tap cell), always-on power

supplies to the taps and a modified tap methodology.

1. Always-on tap cell

Since the local VDD power supply are not available in shutdown mode for the power-gated

block, we need an always-on tap cell that has a global, dedicated always active VDD power

supply connected to the n-wells. This is done by creating always-on well tap pins that can be

connected to chip always-on VDD and VSS supplies. In the VDD gated power-gating design,

only n-well tap pin is needed. The p-substrate can still connected to VSS rail to maintain well

bias as the VSS rail remains connected in the shutdown mode for the power-gated block. An

example of such an always-on tap cell for VDD gated design is shown in Fig. 3. where the n-well

tap is no long connected to the VDD rail in the cell. It becomes a pin that connects to the chip

power supply.

Figure 3 – Always-On Tap Cell


2. Always-on well tap power connections

Having the always-on tap cells inserted within the shutdown blocks, the next task is to connect

their well tap pins to always-on power supplies. The power and ground rails that provide the

power supplies to standard cells in the power-gated domain can no longer be used for tap power

supply because they would be turned off in the shutdown mode. Consequently, an always-on tap

grid needs to be created to acomplish the required tap power connections. Moreover, the tap cells

are often inserted at irregular grid pattern in complex design to satisfy the tap rules. This results

in challenges in the always-on tap power connections to ensure that all the tap cells are

connected to the always-on power supplis. The details of the challenges are described in the

following sections.

4. Challenges in tap insertions in power-gating designs

The special tap insertion requirements for power-gated blocks and the co-existence of active and

powered-down blocks in a same design impose a number of challenges in the tapless power-

gating design. These challenges are outlined below.

1. Domain-based tap type selection

Normal taps (as shown in Fig 1) should be inserted in always-on power domains since tap

connections to n-well and substrate are implemented through the local VDD and VSS power rail

connections. For power-gated domains, always-on tap cells (as shown in Fig 2) must be used to

maintain n-well bias when the domain is in the shutdown mode and the local VDD net is not

connected to the global VDD net. Currently, P&R layout tools rely on the user to define and

implement such domain-based tap insertion. It is desirable to automate the tap selection based on

the domain types.

2. Domain-based tap power “logic“ connections

In physical synthesis, tap power connections need to be defined in terms of “logic“ connections

and physical connections. The physical connections are in the form of metal connections that

supply electric current to the devices while the “logic“ connections are used to define power

connection information with device pins. Such information, imclunding VDD and VSS supply

names, voltage levels and association, is needed for domain-based physical synthesis and power

network generations. The power “logic“ connections are defined by specifying device pin names

and connected power net names. In the always-on domains, the tap power pins are connected to

the domain power nets. In the power-gated domains, the VDD pin of the always-on tap cells is

connected to the domain switched VDD which is mapped to the power rails in the domain power

grid. The n-well tap pin (VDDC) of the tap cells must be connected to the always-on power net.

This multi-PG connection requirement imposes a challenge in ICC due to the power connection

limitation in add_tap_cell_array and the physical only cells power hookup in

derive_pg_connection as outlined below.


Case 1: Use connection_power_name option in add_tap_cell_array to define PG

connections (pre-2010.12)

add_tap_cell_array \ -master_cell_name $tap_cell \

-distance $tap_pitch \

-ignore_soft_blockage true \

-pattern every_other_row \

-voltage_area $va \

-tap_cell_identifier $pd \

-offset $offset \

-skip_fixed_cells false \

-fill_boundary_row false \

-fill_macro_blockage_row true \

-connect_power_name vdd

ICC hooks up both VDD and VDDC pins of the always-on taps to the global power supply net

VDD. This is due to command limitation that only one power connection option is available in

the command while the always-on tap needs two power connnections.

Case 2: Do not connect power in add_tap_cell_array and then use derive_pg_connection to

do logic connections

add_tap_cell_array … (without -connect_power_name option) derive_pg_connection

In this case, the tap insertion did not hook up tap power pins as instructed. The hook up is done

by the following command derive_pg_connection. Unfortunately, derive_pg_connection connects power pins of the physical only cells to domain primary power net which is the

switched vdd in the power-gated domain. Consequently, both VDD and VDDC pins of the

always-on taps are connected to switched supply vdd. This is incorrect.

The issue is getting worse in ICC2010.12 where add_tap_cell_array automatically connects all

power pins to domain primary power even if the always-on supply net VDD is defined in option

"-connect_power_name" due to a tool bug.

It is worth noting that the tap cells are physical cells which do not have signal pins nor a logical

function.Consequently, they are not compiled into standard cell libraries like other power-

management cells for physical synthesis.

3. Domain-based tap power physical connections

The always-on tap power physical connections are also challenge. Since always-on power grid

may not close to the always-on taps, the power routes from the always-on taps to the always-on

grid could result in considerable impact on signal routing. Good planning considering both the

tap insertions and tap power connections is needed to address the issue.


4. Off-grid tap insertion and power connections

Off-grid taps are often inserted in designs containing macros in order to satisfy the n-well and

substrate tap spacing rules in the DRC deck. In the example shown in Fig. 4 containing RAM

macros those taps inserted in the RAM channel and right side of the RAM block boundary are at

a half of the tap pitch to properly connect to the n-well tap and substrate tap connectivity of the

standard cells in the regions. The off-grid taps do not have an always-on power supply, because

they are not covered by the always-on tap grid which is commonly built alinged with taps at the

tap pitch. Consequently, we need facilities to detect the off-grid taps and provide always-on

power routes to connect their power pins correctly. Currently, ICC does not provide such

facilities.

Figure 4 – Off Grid Tap Cells and Power Connections

5. Domain-based tap type selection method

A tcl script was written to implement a method to select correct type of tap cells for every power

domain based on the domain type. Due to customer flow proprietary constraints, the method is

outlined by the pseudo-code below. The proc select_tap {domain} {

if { [sizeof_collection [get_power_switch –of $domain]] > 0 } {

if 9 track standard_cell domain {

return 9 track always-on tap cell

} else {

return 11 track always-on tap cell

}

} else { # non-pm domain

if 9 track standard_cell domain {


return 9 track normal tap cell

} else {

return 11 track normal tap cell

}

}

}

foreach domain $domain-list {

set tap_cell [select_tap $domain]

insert_tap_cells $tap_cell $domain

}

6. Domain-based tap cell logic PG connection method

The logic PG connections of normal taps in non-shutdown domains can be done correctly by

derive_pg_connection. However, the logic PG connections of always-on taps in power gated

domains are problematic due to the co-existence of switched and always-on VDD pins, as

described in section 4. Two methods have been developed to solve the problems.

In the first method, we do not specify any logic connection option in add_tap_cell_array.

Consequently, all tap cell power and ground pins remain unconnected after the tap insertion.

Then, we perform a multiple pass derive_pg_connection to resolve the issue described above in

derive_pg_connection and complete the tap cell logic PG connections. The first pass connects

the tap always-on VDD pins (VDDC) to the always-on supply net (vdd). The second pass

connects taps’ switched VDD pins (VDD) to the domain switched-vdd net. The remaining PG

pins are connected by the final derive_pg_connection. For the taps cells that have back bias

pins (VNW, VPW), the pins are connected to vdd and vss supply nets respectively.

proc always_on_tap_pg_connect {domain} {

add_tap_cell_array -voltage_area $domain.voltage_area \ … more options …

(without -connect_power_name option)

derive_pg_connection -cells $always_on_tap_cells \ -power_net vdd -power_pin VDDC \

-ground_net vss -ground_pin VSS

derive_pg_connection -cells $always_on_tap_cells \ -power_net vdd -power_pin VNW \

-ground_net vss -ground_pin VPW

derive_pg_connection -cells $always_on_tap_cells \ -power_net $domain.switched_vdd -power_pin VDD

derive_pg_connection -cells $always_on_tap_cells

}

foreach domain $domain-list {

if it is a shutdown domain {

always_on_tap_pg_connect $domain

}

}


In the second method, we define tap power connection by the ”-connect_power_name vdd” option

in add_tap_cell_array to get logic PG connections in the tap insertion. To resolve the issue that

both always-on and switched VDD pins are connected to the switched-vdd net due to the

command limitation that only one power connection is allowed, we disconnect the always-on pin

connections and reconnect them to the always-on power supply.

proc always_on_tap_pg_connect {domain} {

add_tap_cell_array -voltage_area $domain.voltage_area \

-connect_power_name $domain.switched_vdd \

… more options …

disconnect_net $domain.switched_vdd $always_on_tap_VDDC_pins derive_pg_connection -cells $always_on_tap_cells \

-power_net vdd -power_pin VDDC

}

The first method decouples the logic PG connection from tap insertion. The issue of logic PG

connection due to the derive_pg_connection limitation is resolved by the multi-pass

workaround. However, this method does not work in ICC 2010.12 release where

add_tap_cell_array will perform logic connection regardless if the connect_power_name

option is defined or not. Unfortunately, the connections are incorrect as both VDD and VDDC

pins are connected to switched-vdd. The second method still works in ICC 2010.12 release, as it

will reconnect the incorrectly connected pin.

7. Domain-based tap cell physical PG connection method

Having resolved the issues in “logic” PG connections, we need to create the metal connections to

the tap cells for routing the power supplies. For a non-shutdown domain, this is not an issue, as

the PG pins of the normal taps are aligned with PG rails. The physical PG connections are done

through rail connections at tap insertion. For the shutdown domains, always-on taps’ p-substrate

tap connection is still connected via rail connection. However, the always-on power physical

connection to the taps’ VDDC pins requires custom power routes, because the VDDC pins are

not aligned to rails. Two methods are described below each has advantages and shortcomings.

The first method leverages ICC feature of net mode PG routing using preroute_standard_cells.

preroute_standard_cells -mode net -nets \

-port_filter_mode select -port_filter VDDC \

-cell_master_filter_mode select \

-cell_master_filter $always_on_tap_master_cell \

-h_width $tap_route_h_width \

-do_not_route_over_macros

In the method, the VDDC pins of the always-on taps are routed to the always-on vertical straps

close to the taps, as shown by the green horizontal routes in Fig. 5., by the net mode

preroute_standard_cell.


Figure 5 – always-on tap pg routing method 1

The default width of the route is the minimum metal width defined in the technology file. Since

taps consume little current, the minimum width should be fine to satisfy IR-drop and EM

constraints provided no other cells were connected to the routes. If needed, the route width can

be change by the h_width option in preroute_standard_cell.

The advantage of the method is that it is simple to implement. However, the net mode routes

result in noticeable routing resource usage due to metal routes of every tap pins to the vertical

always-on power straps, especially when the vertical straps are not close by. This shortcoming is

overcome by the second method.

In the second method, a custom always-on tap grid is built to leverage the always-on power

connection at switch cell VDDC pins that are available next to the tap cells. The objective of the

method is to minimize power routing impact on signal routing. Taps VDDC pins are via

connected to the lower layer vertical straps which connect at 6 rows internval to the switch cell

VDDC pins to get always-on VDD supply. The pseudo-code of the method is described below.

proc always_on_tap_pg_route {domain} {

create vertical lower layer straps within domain voltage area at

tap pitch and aligned with the tap array columns

foreach tap_array_column { foreach switch cell close to the tap_array_column { create a horizontal lower layer stub to connect the switch

always-on pin and vertical tap strap

}

}

}


The clip in Fig. 6 illustrates the custom always-on tap physical connections of the method.

Figure 6 – always-on tap pg routing method 2

The advantage of the method is the low utilization of lower layer horizontal routing resources

which are valuable to signal routing. However, the method relies on the ability to leverage

existing always-on power routes at switch cells close-by. Therefore, it is not such a flexible

approach as the first method. Moreover, the tap pitch might have to be adjusted to make the taps

aligned with the switch horizontal pitch to ensure short stub connections between the taps and

the switches.

8. Off-grid tap insertion and power connections

The always-on tap physical PG connection methods described above take care of the taps

inserted in the regular tap grid. However, they do not handle well the off-grid taps such as those

inserted in the narrow channels between macros. This issue has been resolved by the developed

method that detects the off-grid always-on taps and creates additional custom physical

connections to those taps.

We detect the off-grid taps by checking the metal connections of taps’ VDDC pins, after tap grid

creation. Then, we sort the off-grid taps into column bins. For each column of the off-grid taps, a

vertical always-on power strap is added next to the column and the VDDC pins of the taps in the

column are connected to the strap by either the net mode preroute_standard_cell method or

the custom stub method described in the previous section. The method is outlined below.


proc detect_off_grid_always_on_taps {

foreach tap $always_on_taps {

if no metal strap at next layer over the VDDC pin of the tap { append the tap to collection off_grid_always_on_taps }

} return $off_grid_always_on_taps }

proc fix_off_grid_always_on_taps {

set off_grid_taps [detect_off_grid_always_on_taps]

set sorted_off_grid_taps [sort_collection $off_grid_taps

bbox_llx bbox_lly]

foreach tap_column in $sorted_off_grid_taps { create vertical always-on strap next to the column

} preroute_standard_cells -mode net -nets \ -port_filter_mode select -port_filter VDDC \

-cell_master_filter_mode select \

-cell_master_filter $always_on_tap_master_cell \

-h_width $tap_route_h_width \

-do_not_route_over_macros

}

9. Results

The methods described in the paper have been implemented in a UPF DC/ICC flow for

production low-power design. Three chips have been successfully taped out using the UPF flow.

To illustrate the methods, a small design was created which has an always-on domain at bottom-

left corner and a shutdown domain which takes the rest of the design and in rectilinear shape.

The domain-based tap insertion and PG grid generation methods were applied to the design

transparently as it has been integrated into the UPF flow and fully automated. The results are

shown in Fig. 7. In the always-on domain, normal taps were selected and inserted. Simple cell

rail connections completed the task of physical PG connections of the taps. In the shutdown

domain, the always-on taps were inserted at 60um pitch defined by the tap rule. A column of off-

grid taps were inserted at a half tap pitch in the middle of the domain to satisfy the tap

requirement in the standard cell region from right side of the always-on domain. The custom

always-on tap grid method was used in this case to leverage existing always-on grids on the

switch cells. The vertical straps were correctly created over the all taps including the off-grid

taps. The horizontal stubs were also inserted connecting the vertical straps to the switch always-

on power pins to get power supply to the taps.


Figure 7 – An example of domain based tap insertion and PG connection

10. Summary

Most sub-65nm production SOC designs are implemented with tapless library cells for silicon

area efficiency. The tap cell insertion flow becomes complicated and risk-prone in power-gating

designs where always-on and shutdown blocks co-exist and different types of tap cells need to be

implemented in different domains accordingly. Furthermore, the logic and physical PG

connections of these tap cells becomes no longer straight forward and could result in chip failure

if not implemented correctly. This paper addresses these challenges in the tapless power-gating

design by a domain-based tap insertion method and implementation techniques including

domain-based tap type selection, always-on tap logic PG connection and PG grid generation, and

off-grid tap detection and fix. The method and implementation techniques have been integrated

into a UPF DC/ICC flow and have been used successfully in a number of production low-power

designs.


11. References

IC Compiler user manual.

12. Author biographies

Kaijian Shi is Principal Consultant in Synopsys Professional Services Group, specializing in

low-power design methodology and implementation. He has successfully completed more than

14 commercial low-power designs. Dr. Shi co-authored the book “Low Power Methodology

Manual for System-on-Chip Design”. He has published 53 papers in journals and international

conferences. He also gave a number of talks and tutorials on low-power design methodologies.

Dr. Shi holds a Ph.D. degree from University of Kent at Canterbury, UK since 1994. He was

Chairman of IEEE Dallas Section in 2006 and Chairman of IEEE Circuits and System Society

Dallas Chapter in 2004. He was workshop chair and then publicity chair of IEEE SoC

Conference 2008-2011, program committee members of IEEE ISVLSI (2006-2008) and

technical program track chair of DesignCon (2004-2008).

David Tester has 15+ years of complex SOC, PMIC and RFIC experience in various hands-on

semiconductor development and executive management positions with Air, Symbionics,

Conexant, LSI Logic and Dialog based both in the UK and US. He founded his first start-up Air

in 2006 and delivered the first LBS optimized GPS receiver to market in 2009, having raised

$10M of VC investment from Pond Ventures and built a world-class systems, silicon and

software team. His high volume, standard product, consumer IC background spans both digital

and analog silicon development – ranging from system level through semi-custom digital to full-

custom analog and digital transistor level design. He has participated in the development of over

20 semiconductor products for the location, wireless voice, wireless data, digital TV and PC

graphics markets. He holds a degree in Engineering from the University of Hull, UK. He is a

Fellow of the IET, a Senior Member of the IEEE and holds fifteen granted system, silicon and

software patents.

power gating design implementation with tapless cells

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