power dissipation cmos

Power Dissipation

CMOS

Outline

bull Motivation to estimate power dissipationbull Sources of power dissipationbull Dynamic power dissipationbull Static power dissipationbull Metricsbull Conclusion

Need to estimate power dissipation

Power dissipation affectsbull Performance bull Reliabilitybull Packagingbull Costbull Portability

Where Does Power Go in CMOS

bull Dynamic Power Consumption

bull Short Circuit Currents

bull Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles

EN CL Vdd 2 n N =

n(N) the number of 0-gt1 transition in N clock cycles

EN the energy consumed for N clock cycles

Pavg N lim

ENN-------- fclk

= n N N------------

N lim

CL

Vdd 2

fclk=

0 1

n N N------------

N lim=

Pavg =0 1 C

LVdd

2 fclk

bullDue to charging and discharging of capacitance

Activity factors of basic gates

bull AND

bull OR

bull XOR

BABA pppp )1(

)]1)(1(1)[1)(1( BABA pppp

)2)](2(1[ BABABABA pppppppp

Dynamic Power dissipation

bull Power reduced by reducing Vdd f C and also activitybull A signal transition can be classified into two categories

a functional transition and a glitch

Glitch Power Dissipation

bull Glitches are temporary changes in the value of the output ndash unnecessary transitions

bull They are caused due to the skew in the input signals to a gatebull Glitch power dissipation accounts for 15 ndash 20 of the

global powerbull Basic contributes of hazards to power dissipation arendash Hazard generationndash Hazard propagation


bull P = 12 CLVdd (Vdd ndash Vmin) Vmin min voltage swing at the output

bull Glitch power dissipation is dependent on ndash Output loadndash Input patternndash Input slope


bull Hazard generation can be reduced by gate sizing and path balancing techniques

bull Hazard propagation can be reduced by using less number of inverters which tend to amplify and propagate glitches

Short Circuit Power Dissipation

bull Short circuit current occurs during signal transitions when both the NMOS and PMOS are ON and there is a direct path between Vdd and GND

bull Also called crowbar currentbull Accounts for more than 20 of total power dissipationbull As clock frequency increases transitions increase

consequently short circuit power dissipation increasesbull Can be reduced ndash faster input and slower outputndash Vdd lt= Vtn + |Vtp|

bull So both NMOS and PMOS are not on at the same time

Static Power Consumption

Vin=5V

Vout

CL

Vdd

Istat

Pstat = P(In=1)Vdd Istat

bull Dominates over dynamic consumption

bull Not a function of switching frequency

Wasted energy hellipShould be avoided in almost all cases

Static Power Dissipation

bull Power dissipation occurring when device is in standby modebull As technology scales this becomes significantbull Leakage power dissipationbull Componentsndash Reverse biased p-n junctionndash Sub threshold leakagendash DIBL leakagendash Channel punch throughndash GIDL Leakagendash Narrow width effectndash Oxide leakagendash Hot carrier tunneling effect

Leakage Current

New Problem Gate Leakage

1048708Now about 20-30 of all leakage and growing1048708Gate oxide is so thin electrons tunnel thru ithellip1048708NMOS is much worse than PMOS

Principles for Power Reductionbull Prime choice Reduce voltagendash Recent years have seen an acceleration in

supply voltage reductionndash Design at very low voltages still open question

(06 hellip 09 V by 2010)bull Reduce switching activity Logic synthesis Clock gatingbull Reduce physical capacitancendash Proper Device Sizingndash Good layout

Factors affecting leakage power

bull Temperaturendash Sub-threshold current increases exponentially

bull Reduction in Vtbull Increase in thermal voltage

ndash BTBT increases due to band gap narrowingndash Gate leakage is insensitive to temperature change


bull Gate oxide thicknessndash Sub-threshold current decreases in long channel transistors and

increases in short channelndash BTBT is insensitivendash Gate leakage increases as thickness reduces

Solutions

bull MTCMOSbull Dual Vtbull Dual Vt domino logicbull Adaptive Body Biasbull Transistor stacking

Metrics

bull Power Delay productbull Energy Delay Productndash Average energy per instruction x average inter instruction

delaybull Cunit_area

ndash Capacitance per unit area

Summary

1048708Power Dissipation is already a prime design constraint1048708Low-power design requires operation at lowest possible voltage and clock speed 1048708Low-power design requires optimization at

Conclusion

bull Power dissipation is unavoidable especially as technology scales down

bull Techniques must be devised to reduce power dissipationbull Techniques must be devised to accurately estimate the power

dissipationbull Estimation and modeling of the sources of power dissipation

for simulation purposes

Power Dissipation

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Outline

bull Motivation to estimate power dissipationbull Sources of power dissipationbull Dynamic power dissipationbull Static power dissipationbull Metricsbull Conclusion






bull Leakage






EN CL Vdd 2 n N =



Pavg N lim

ENN-------- fclk

= n N N------------

N lim

CL

Vdd 2

fclk=

0 1

n N N------------

N lim=

Pavg =0 1 C

LVdd

2 fclk



bull AND

bull OR

bull XOR

BABA pppp )1(

)]1)(1(1)[1)(1( BABA pppp





















Vin=5V

Vout

CL

Vdd

Istat







Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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bull Leakage






EN CL Vdd 2 n N =



Pavg N lim

ENN-------- fclk

= n N N------------

N lim

CL

Vdd 2

fclk=

0 1

n N N------------

N lim=

Pavg =0 1 C

LVdd

2 fclk



bull AND

bull OR

bull XOR

BABA pppp )1(

)]1)(1(1)[1)(1( BABA pppp





















Vin=5V

Vout

CL

Vdd

Istat







Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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EN CL Vdd 2 n N =



Pavg N lim

ENN-------- fclk

= n N N------------

N lim

CL

Vdd 2

fclk=

0 1

n N N------------

N lim=

Pavg =0 1 C

LVdd

2 fclk



bull AND

bull OR

bull XOR

BABA pppp )1(

)]1)(1(1)[1)(1( BABA pppp





















Vin=5V

Vout

CL

Vdd

Istat







Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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bull AND

bull OR

bull XOR

BABA pppp )1(

)]1)(1(1)[1)(1( BABA pppp





















Vin=5V

Vout

CL

Vdd

Istat







Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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Vin=5V

Vout

CL

Vdd

Istat







Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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Leakage Current













Solutions


Metrics




Summary


Conclusion





Power Dissipation

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Solutions


Metrics




Summary


Conclusion





Power Dissipation

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Metrics




Summary


Conclusion





Power Dissipation

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Summary


Conclusion





Power Dissipation

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Conclusion





Power Dissipation

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power dissipation cmos

Engineering

b p p p p p p p p

glitch power dissipation

total power dissipation

b p p p p1

power dissipationcmos

theglobal power basic

xora b

slower output vdd