past and future trends 0f integrated circuit …past and future trends 0f integrated circuit...

Past and Future Trends 0f Integrated Circuit Technology

October 25, 2010

Hiroshi Iwai, 1

@Prithvi Narayan Campus, Trivhuvan Univ.,Pokhara, Nepal

Frontier Research CenterTokyo Institute of Technology

Founded in 1881, Promoted to Univ. 1929Tokyo Institute of Technology

International StudentsInternational Students

Asia 847Europe 78 North America 12

South America 24Oceania 5

Africa 16

Total 982

Country Students

China 403

S. Korea 130

Indonesia 64

Thailand 55

Vietnam 60

Malaysia 28

(As of May. 1, 2005)

• There were many inventions in the 20th century:

Airplane, Nuclear Power generation, Computer,

Space aircraft, etc

• However, everything has to be controlled by electronics

• Electronics

Most important invention in the 20th century

• What is Electronics: To use electrons,

Electronic Circuits

Importance of Electronics

Lee De Forest

Electronic Circuits started by the invention of vacuum tube (Triode) in 1906

Cathode(heated) Grid

Anode(Positive bias)

Thermal electrons from cathodecontrolled by grid bias

Same mechanism as that of transistor

First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament

Today's pocket PCmade of semiconductor has much higher performance with extremely low power consumption

dreamed of replacing vacuum tube with solid‐state device

7

J.E.LILIENFELD

J. E. LILIENFELD

DEVICES FOR CONTROLLED ELECTRIC CURRENTFiled March 28, 1928

8

ElectronSemiconductor

Gate Electrode

Gate InsulatorNegative bias

Positive bias

Capacitor structure with notch

No current

Current flows

Electricfield

9

Source Channel Drain

0V

N+-Si P-Si

N-Si

0V

1V

Negative

Source Channel DrainN-Si1V

N+-Si P-Si

Surface Potential (Negative direction)

Gate Oxd

ChannelSource Drain

Gate electrode

S D

G

0 bias for gate Positive bias for gate

Surface

Electron flow

10

However, no one could realize MOSFET operation for more than 30 years.

Because of very bad interface property between the semiconductor and gate insulator

Even Shockley!

11

Very bad interface property between the semiconductor and gate insulator

Even Shockley!

eGe

GeO Electric Shielding

CarrierScattering

Interfacial Charges

Drain Current was several orders of magnitude smaller than expected

12

1947: 1st transistor W. Bratten,

W. ShockleyBipolar using Ge

However, they found amplification phenomenon when investigatingGe surface when putting needles.This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism)

J. Bardeen

13

1958: 1st Integrated Circuit Jack S. Kilby

Connect 2 bipolar transistors in theSame substrate by bonding wire.

14

1960: First MOSFET by D. Kahng and M. Atalla

Top View

Al Gate

Source

Drain

Si

Si

断面

Al

SiO2

Si

Si/SiO2 Interface is extraordinarily good

15

1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

16

MOS LSI experienced continuous progress for many years

1960s IC (Integrated Circuits) ~ 10

1970s LSI (Large Scale Integrated Circuit) ~1,000

1980s VLSI (Very Large Scale IC) ~10,000

1990s ULSI (Ultra Large Scale IC) ~1,000,000

2000s ?LSI (? Large Scale IC) ~1000,000,000

Name of Integrated Circuits Number of Transistors

17

Gate ElectrodePoly Si

Gate InsulatorSiO2

Drain

SiSubstrate

Source

Channel N‐MOS (N‐type MOSFET)

Gate ElectrodePoly Si

Gate InsulatorSiO2

SubstrateSi

Use Gate Field Effect for switching

ee

18

19

CMOS

Complimentary MOS

Inverter

PMOS

NMOS

When NMOS is ON, PMOS is OFFWhen PMOS is ON, NMOS is OFF

CMOS Technology: Indispensible for our human society

Al the human activities are controlled by CMOS

living, production, financing, telecommunication, transportation, medical care, education, entertainment, etc.

Without CMOS:

world economical activities immediately stop.

Cellarer phone dose not exists

Needless to say, but….

There is no computer in banks, and

20

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI ULSI

10 cm cm mm 10 µm 100 nm

In 100 years, the size reduced by one million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.

10-1m 10-2m 10-3m 10-5m 10-7m

Downsizing of the components has been the driving force for circuit evolution

21

Downsizing1. Reduce Capacitance

Reduce switching time of MOSFETsIncrease clock frequency

Increase circuit operation speed2. Increase number of Transistors

Parallel processingIncrease circuit operation speed

Thus, downsizing of Si devices is the most important and critical issue.22

Downsizing contribute to the performance increase in double ways

2323

Scaling Method: by R. Dennard in 1974

1

1Wdep

1 1

I

00 V 1

X , Y , Z : K, V : K, Na : 1/K

K

K

KWdep

Wdep V/Na: K

KI00 KV

I : K

K=0.7 for example

Wdep: Space Charge Region (or Depletion Region) Width

Wdep has to be suppressedOtherwise, large leakagebetween S and D

Leakage current

S D

By the scaling, Wdep is suppressed in proportion,and thus, leakage can be suppressed.

Good scaled I-V characteristics

Potential in space charge region ishigh, and thus, electrons in source areattracted to the space charge region.

2424

Drive current

Power per chip

Integration (# of Tr)

Scaling K : K=0.7 for example

Id = vsatWgCo (Vg‐Vth)

N

K‐1(αK‐2)K (K1 )2= α

Switching speed KK/K= K

Id per unit Wg = Id / Wg= 1

Wg (tox –1)(Vg‐Vth)= Wgtox

‐1(Vg‐Vth)= KK‐1K=Kin saturation

Co: gate C per unit area

Cg = εoεoxLgWg/tox

Id per unit Wg

Clock frequency

K

1

τ

Id

K

Id/µm

f 1/K f = 1/τ = 1/K

N α/K2

P α

Gate capacitance Cg K

Chip area Achip α

Lg, WgTox, Vdd

Geometry &Supply voltage

K

KK/K = K

τ= CgVdd/Id

α: Scaling factor

α/K2

fNCV2/2

= 1/K2 , when α=1

= 1, when α=1

Downscaling merit: Beautiful!

In the past, α>1 for most cases

2525

k= 0.72 =0.5 and α =1

Vdd 0.7Single MOFET

Lg 0.7Id 0.7Cg 0.7P (Power)/Clock

0.73 = 0.34 τ (Switching time) 0.7

Chip N (# of Tr) 1/0.72 = 2

P (Power)

k= 0.7 and α =1

Vdd 0.5Lg 0.5Id 0.5Cg 0.5P (Power)/Clock

0.53 = 0.125 τ (Switching time) 0.5

1/0.7 = 1.4f (Clock)1

N (# of Tr) 1/0.52 = 4

P (Power)1/0.5 = 2f (Clock)1

2626

10 -3

10 -2

10 -1

10 0

10 1

10 2

1970 1980 1990 2000

MPU Lg (µm)X

j (µm)

Minimum logic Vdd (V)

Id/µm(mA/µm)

tox (µm)

10 -3

10 -1

10 1

10 3

1970 1980 1990 2000

chip size （mm2）

Number of tr

ansistors

power (W

)

MIPSclock frequency (MHz)

Id/µm

Id

1 101

10‐1K (10 –2) f 1/K(10 2) 103

P α(10 1) 105

N α/K2(10 5) 104Achip α 101

Change in 30 years

Lg K 10 ‐2tox K(10 –2) 10‐2

Vdd K(10 –2) 10‐1

Idealscaling

RealChange

Idealscaling

RealChange

Idealscaling

RealChange

= fαNCV2

Past 30 years scaling

N, f increaseMerit:

Demerit: P increase

Vdd scaling insufficient

Additional significantincrease inId, f, P

Actual past downscaling trend until year 2000

Vd scaling insufficient, α increased N, Id, f, P increased significantly

Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268

Late 1970’s 1µm: SCE

Early 1980’s 0.5µm: S/D resistance

Early 1980’s 0.25µm: Direct‐tunneling of gate SiO2

Late 1980’s 0.1µm: ‘0.1µm brick wall’(various)

2000 50nm: ‘Red brick wall’ (various)

2000 10nm: Fundamental?

Period Expected Cause limit(size)

Many people wanted to say about the limit. Past predictions were not correct!!

27

Historically, many predictions of the limit of downsizing.

VLSI text book written 1979 predict that 0.25 micro‐meter would be the limit because of direct‐tunneling current through the very thin‐gate oxide.

29C. Mead L. Conway

VLSI textbook

Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide ..... begin to make the devices of smaller dimension unworkable.

30

Potential Barrier

Wave function

Direct‐tunneling effect

31

G

SD

Gate Oxide

Gate OxideGate Electrode

Si Substrate

Direct tunneling leakage current start to flow when the thickness is 3 nm.

Direct tunnelingcurrent

Direct tunneling leakage was found to be OK! In 1994!

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

‐0.4

0.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

‐0.1

0.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

‐0.02

0.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

‐0.4

0.0 0.5 1.0 1.5

Vd (V)

Id (m

A / μ

m)

Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm

Gate electrode

Si substrate

Gate oxide

MOSFETs with 1.5 nm gate oxide

32

G

S D

Lg

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

1.6

1.2

0.8

0.4

0.0

-0.40.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.4

0.3

0.2

0.1

0.0

-0.10.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.08

0.06

0.04

0.02

0.00

-0.020.0 0.5 1.0 1.5

Vd (V)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A/ μ

m)

Vg = 2.0V

1.5 V

1.0 V

0.5 V

0.0 V

0.03

0.02

0.01

0.00

0.01

-0.40.0 0.5 1.0 1.5

Vd (V)

Id (m

A/ μ

m)

Lg = 10 µm Lg = 5 µm Lg = 1.0 µm Lg = 0.1µm

Gate leakage: Ig ∝ Gate Area ∝ Gate length (Lg)

Id

Drain current: Id ∝ 1/Gate length (Lg)

Lg small, Then, Ig small, Id large, Thus, Ig/Id very small

33

G

S D

Ig Id

Never Give Up!

There would be a solution!

Think, Think, and Think!

Or, Wait the time!Some one will think for you

No one knows future!

Do not believe a text book statement, blindly!

34

Qi Xinag, ECS 2004, AMD35

5 nm gate length CMOS

H. Wakabayashi et.al, NEC

IEDM, 2003

Length of 18 Si atoms

Is a Real Nano Device!!

5 nm

36

Tunnelingdistance

3 nm

Atomicdistance

0.3 nm

Below this, no one knows future!

What is the limit prediction now!

37

Limit for MOSFET operation

Ultimate limitation

10 ‐5

10 ‐4

10 ‐3

10 ‐2

10 ‐1

100

101

102

1970 1990 2010 2030 2050

MPU LgJunction depthGate oxide thickness

Direct-tunneling

ITRS Roadmap(at introduction)

Wave length of electron

Distance between Si atomsSize (µ

m), Voltage(V)

Min. V supply

10 nm3 nm

0.3 nm

ULTIMATELIMIT

However,Gate oxide thickness2 orders magnitude smallerClose to limitation!!

Lg: Gate length downsizing will continue to another 10‐15 years 38

By Robert Chau, IWGI 2003

0.8 nm Gate Oxide Thickness MOSFETs operates!!

0.8 nm: Distance of 3 Si atoms!!

39

So, we are now in the limitation of downsizing?

Do you believe this or do not?

40

There is a solution!To use high‐k dielectrics

Thin gate SiO2Thick gate high‐k dielectrics

Almost the same electric characteristics

However, very difficult and big challenge!Remember MOSFET had not been realized without Si/SiO2!

K: Dielectric Constant

Thick

Small leakageCurrent

41

42

Historical trend of high-k R& D

1st FET LSIPMOS NMOS CMOS

IC

Gate insulator

Gate electrode

1960 1970 1980 1990 2000 05

MOSFETGate Stackin production

SiO2 SiOxNy

DoublePoly SiAl N+Poly Si

Silicide above Poly Si electrode TiSi2 CoSi2WSi2MoSi2 NiSi

MOSFET

DRAM Capacitor

NV Memory

Analog/RF

Al2O3, ZrO2

Ni3Si4 Stack NO(Ni3Si4/SiO2)

R&D for high-k

NO, AO (Al2O3/SiO2)

Recent new high-kPure Si Period

(O)NO, Ni3Si4

(O)NO, Ni3Si4Ta2O5 , Al2O3,

Ta2O5 ,

R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)

●

● Gas or liquidat 1000 K

●H

○Radio activeHe

● ● ● ● ● ●Li BeB C N O F Ne

① ● ● ● ●Na Mg Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ① ● ● ● ●K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ① ① ① ① ● ●Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe● ③ ① ① ① ① ① ● ● ● ● ① ① ○ ○ ○Cs Ba ★

HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn

○ ○ ○ ○ ○ ○ ○ ○Fr Ra ☆ Rf Ha Sg Ns Hs Mt

○La Ce Pr Nd PmSmEu Gd Tb Dy Ho Er TmYｂ Lu○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

★

☆

Candidates

● ●Na Al Si P S Cl Ar

② ① ① ① ① ① ① ① ① ① ● ● ● ●K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr● ① ① ① ① ① ● ① ①

○ ○ ○ ○ ○ ○Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr

★

☆

②

③

Unstable at Si interfaceSi + MOX M + SiO2①

Si + MOX MSiX + SiO2

Si + MOX M + MSiXOY

Choice of High-k elements for oxide

HfO2 based dielectrics are selected as the first generation materials, because of their merit in1) band-offset, 2) dielectric constant3) thermal stability

La2O3 based dielectrics are thought to be the next generation materials, which may not need a thicker interfacial layer

43

44

PMOS

High‐k gate insulator MOSFETs for Intel: EOT=1nm

EOT: Equivalent Oxide Thickness

45

0 V

1.1 V

V > 1 Ve

V > 1 Vh

OxideSi

CB

VB

-6

-4

-2

0

2

4

6

Ene

rgy

(eV

)

SiO2

4.4

3.5

1.1

2.4

1.8

0.3

3.0

-0.1

2.3

Si3N4Ta2O5

SrTiO3

BaZrO3

ZrO2

Al2O3

Y2O3

La2O3

ZrSiO4HfSiO4

4.9

2.82.3

2.6 3.4

1.51.5

3.43.3

1.4

3.4

0.8

Si HfO2

1.9

2.1

LaAlO3

J Robertson, J Vac Sci Technol B 18 1785 (2000)

Band Offsets Calculated value

Dielectric constantSiO2; 4Si3N4: ~ 7Al2O3: ~ 9

Y2O3; ~10Gd2O3: ~10

HfO2; ~23La2O3: ~27

HfO2 was chosen for the 1st generationLa2O3 is more difficult material to treat

0 10 20 30 40 50Dielectric Constant

4

2

0

-2

-4

-6

SiO2

Ban

d D

isco

ntin

uity

[eV]

Si

kB *φ : Figure of Merit of High-k

T. Hattori, INFOS , 2003

SiO2 3.9AlxSiyOz(Ba,Sr)TiO3 200-300BeAl2O4 8.3-9.43CeO2 16.6-26CeHfO4 10-20CoTiO3/Si3N4EuAlO3 22.5HfO2 26-30Hf silicate 11La2O3 20.8LaScO3 30La2SiO5MgAl2O4

NdAlO3 22.5PrAlO3 25Si3N4 7SmAlO3 19SrTiO3 150-250Ta2O5 25-24Ta2O5-TiO2TiO2 86-95TiO2/Si3N4Y2O3 8-11.6YxSiyOzZrO2 22.2-28Zr-Al-OZr silicate(Zr,Sn)TiO4 40-60

C.A. Billmann et al.,, MRS Spring Symp., 1999,R.D.Shannon, J. Appl. Phys., 73, 348, 1993S. De Gebdt, IEDM Short Coyuse, 2004

Dielectric constant value vs. Band offset (Measured)

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

0 0.5 1 1.5 2 2.5 3

EOT ( nm )

Cur

rent

den

sity

( A

/cm

2 )Al2O3HfAlO(N)HfO2HfSiO(N)HfTaOLa2O3Nd2O3Pr2O3PrSiOPrTiOSiON/SiNSm2O3SrTiO3Ta2O5TiO2ZrO2(N)ZrSiOZrAlO(N)

Gate Leakage vs EOT, (Vg=|1|V)

La2O3

HfO2

47

48

1837184018431846Binding energy (eV)

Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC


Inte

nsity

(a.u

)

Si sub.

Hf SilicateSiO2

500 oC

SiOx-IL

HfO2

W

1 nm

k=4

k=16

SiOx-IL growth at HfO2/Si Interface

HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2

Phase separator

SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction

Oxygen supplied from W gate electrode

XPS Si1s spectrum

D.J.Lichtenwalner, Tans. ECS 11, 319

TEM image 500 oC 30min

H. Shimizu, JJAP, 44, pp. 6131

49

La-Silicate Reaction at La2O3/Si

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~14

k=23


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC


Inte

nsity

(a.u

)

as depo.

300 oC

La-silicate

Si sub.

500 oC

La2O3 + Si + nO2→ La2SiO5, La2Si2O7,

La9.33Si6O26, La10(SiO4)6O3, etc.

La2O3 can achieve direct contact of high-k/Si

XPS Si1s spectraTEM image

Direct contact high-k/Si is possible

EOT = 0.48 nm

Transistor with La2O3 gate insulator

Our results

50

Direct contact of high-k/Si with La-silicate foramtion

※EOT:Equivalent oxide thickness

Foramtion of high-k quality La-silicate using the reaction of La2O3 and Si substrate

Originality

Si

High-k

SiOx intefaciallayer (0.5~0.7nm)

EOT scaling→limitted by IL

Si

High-k

Si

High-k

silicate

Issues in Dit, realiabilityµeff, etc.

High-k/SiO2/Si Direct contact of high-k/Si Direct contact of high-k/Siwith high quality silicate

Nice FET operation→EOT scaling

thin layer of silicate at high-k/Si interface

High quality La-silicate

La2O3

La-silicate

W

1 nm

k=8~14

k=23

La2O3 + Si + nO2→ La2SiO5, La9.33Si6O26, La10(SiO4)6O3, La2Si2O7, etc.

La2O3/Si after 500 oC 30min

Proper oxygen atom supply to form high quality Si-rich La-silicate

SiSiO2

HfO2

Si

La2O3

・HfO2 formesSiO2 at interface

・µeff degradation・defects in silicate(hysteresis)・large Dit (1013cm-2/eV)

La-richsilicateLa2SiO5

K. Kakushima, et al., ESSDERC ’08, Edinburgh

Si-richsilicatek=8~14

La-rich Si-rich

0.00E+00

5.00E-05

1.00E-04

1.50E-04

2.00E-04

2.50E-04

3.00E-04

3.50E-04

-0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2-0.4 0 0.4 0.8 1.2

0.1

0.2

0.30.35

Gate voltage (V)

Tran

scon

duct

ance

(mS)

Vd=50mV

W/L=50/2.5µm

0.00.00E+00

5.00E-05

1.00E-04

1.50E-04

2.00E-04

2.50E-04

3.00E-04

3.50E-04

-0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2-0.4 0 0.4 0.8 1.2

0.1

0.2

0.30.35

Gate voltage (V)

Tran

scon

duct

ance

(mS)

Vd=50mV

W/L=50/2.5µm

0.0

11%up

EOT=0.48nm

FET operation of EOT=0.37nm

0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1

Dra

in c

urre

nt (m

A) 3.5

2

1

0

3

(a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm

W/L=2.5/50µmPMA 300oC (30min)

Vth=-0.04V Vth=-0.03V Vth=-0.02V

14%up4%up

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

compensation regioninsufficient

W/L=50/2.5µm

0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1

Dra

in c

urre

nt (m

A) 3.5

2

1

0

3

(a) EOT=0.37nm (b) EOT=0.43nm (c) EOT=0.48nm

W/L=2.5/50µmPMA 300oC (30min)

Vth=-0.04V Vth=-0.03V Vth=-0.02V

14%up4%up

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

0 0.2 0.4 0.6 0.8 1Drain voltage (V)

compensation regioninsufficient

W/L=50/2.5µm

EOT scaling below 0.5nm is still useful

Direct contact of high-k/Si using La2O3/silicate

K. Kakushima, et al., Microelectron. Reliab., 50, 790 (2010)

Improvement in both drain current and transconductance

(2) Direct high-k/Si using La-silicate/Si with high µeff

0

50100

150200

250

300350

400

0 0.2 0.4 0.6 0.8 1Eeff(MV/cm)

µ eff(

cm2 /V

s)

universal

0.0E+00

5.0E-05

1.0E-04

1.5E-04

2.0E-04

2.5E-04

3.0E-04

3.5E-04

4.0E-04

-0.8 -0.4 0.0 0.4 0.8 1.2 1.61.0E-10

1.0E-09

1.0E-08

1.0E-07

1.0E-06

1.0E-05

1.0E-04

1.0E-03

0.0E+00

1.0E-03

2.0E-03

3.0E-03

4.0E-03

5.0E-03

6.0E-03

0 0.2 0.4 0.6 0.8 1

00.20.40.60.811.2

Ids

(A)

Vd (V) Vg (V)

Ids

(A)

EOT=1.26 nmVth=-0.08 VSS=66.4mV/dec

L/W=2.5/50µm

W/La2O3/La-silicate/nFET, 500oC for 30min

Fairly nice properties can be achieved even with direct high-k/Si interface (EOT~1.2)

High peak µeff of 300cm2/Vs with 500oC annealing→ nice proerties of Si-rich La-silicate/Si interface

EOT=1.26nm

K. Kakushima, et al., ESSDERC ’08, Edinburgh

(3) Origin of degradations at EOT<1.3nm

1012 1013100

1000

200

300400500

Ns0.5

µadd

EOT = 1.69 nm

EOT = 0.93 nm

Ns (cm-2)µ e

ff, µ

add

(cm

2 /Vs)

2000

Coulomb scattering from high-k at EOT<1.3nm

Additional scattering of ~Ns0.5

←remote Coulomb scattering (Coulomb scattering in bulk Si ∝Ns

1)

Inversion density,

-1.4-1.2

-1-0.8-0.6-0.4-0.2

00.2

EOT (nm)

La2O3/silicate nFET, W/L=50µm/2.5µm

1011

1012

Dit

(cm

-2/e

V)

507090

110130150170

S.S

(mV/

dec)

V fb,

V th

(V) Vth

0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2

Charge pumping @500kHz

Vfb

K. Kakushima, et al., Solid-State Electron., 54, 715 (2010)

Matthiessen’s rule

Defects from metal electrode

metal

Si sub.

EOTlim

density defects

effectivedistance

interface trap generation

high-kVo defect

metal defect metal

Vo

Metal atom diffusions to degrade the µeffin EOT<1.3nm

0

100

200

300

400

0.6 1.2 1.80EOT (nm)

µ eff

(cm

2 /Vs)

W/La2O3/silicate nFETAnnealed at 500 oC

peak µeff

µeff @ 0.8 MV/cm

W/L=50/2.5µm

EOTlim

nice Silicate/Siproperties

K. Kakushima, et al., Solid-State Electron., 54, 715 (2010)

Low Dit at high-k/Si interface at EOT>1.3nm

57

Vfb

(V)

-0.5-0.4-0.3-0.2-0.1

00.10.2

0.8 1.0 1.2 1.4 1.6 1.8 2.0

w/ Mg

w/o Mg

PMA500oC

EOT (nm)

W

Si

La

W

Si 2nm

a.u.

Mg

TEM EDX

Gate Metal Induced Defects Compensation

Suppression of aggressive shift in Vfb

Metal GateMgO

La2O3Si

58

Challenge for thinning High‐k

W/HfO2

µ eff

(cm

2 /Vs)

EOT (nm)

500 oC annealed

0.4 1.0 1.6

350

250

50

150

100

200

300

0W/La2O3 @300oC

W/La2O3Open: peak mobilityFill: 0.8MV/cm

EOT=0.5nm

1.41.20.80.6

500 oC annealedW/HfO2

µ eff

(cm

2 /Vs)

EOT (nm)

500 oC annealed

0.4 1.0 1.6

350

250

50

150

100

200

300

0W/La2O3 @300oC

W/La2O3Open: peak mobilityFill: 0.8MV/cm

EOT=0.5nm

1.41.20.80.6

500 oC annealed

µ eff( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universal

µ eff( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universal

PMA500oC

Metal GateMgO

La2O3Si

Degradation of mobility

Some solution

(5) µeff recovery with Mg incorportationVf

b(V

)

-0.5-0.4-0.3-0.2-0.1

00.10.2

0.8 1.0 1.2 1.4 1.6 1.8 2.0

w/ Mg

w/o Mg

PMA500oC

EOT (nm)µ ef

f( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universal

µ eff( c

m2 /V

s)

050

100150200250300350

0 0.2 0.4 0.6 0.8 1.0

w/ Mg (EOT=1.09nm)

w/o Mg (EOT=1.04nm)

universal

PMA500oC

Eeff (MV/cm)

Incorprotation of Mg into La-silicate can recover the µeff

Suppression of Vfb shift at small EOT

µeff recovery

Mg incorporation into La-silicate

T. Koyanagi, K. Tachi, K. Okamoto, K. Kakushima, et al, Jpn. J. Appl. Phys., 48, 05DC02 (2009)

PreparationRoom

E-Beam Evaporation8 different target

Flash LampAnnealMicro to mille-seconds

Sputter for metal5 different target

Robot room

Cluster tool for high-k thin film deposition

61

Si Nanowire FET

62

Introduction of SiNW FETs

DrainDrain

SourceSource

GateGate

NanowireNanowire BOXBOX

DrainDrain

SourceSource

GateGate

NanowireNanowire BOXBOX

Effective electrostatic control of 1-D channel due to the gate all-around structure.

Low Ioff can be achieved.

Source DrainGate Gate

SourcePlanar FET

Multi Gate FET

Nanowire FETSource Drain

Gate

UTB SOI FET

63

Toward a Reduction of Power Supply Voltage

Gate Voltage (V)

Dra

in C

urre

nt (l

in.) Vd: high

Dra

in C

urre

nt (l

og.)

Vd: low

SiNW FET

Conventional FET

SiNW FET

Conventional FET

Higher drivability

Reduction of VDDand low power consumption

Lower IOFF

Vth Vth

Required ION can be achieved with lower overdrive voltage.

Capacity for reduction of Vth

required ION

1

10

100

1000

10000

0 1000 2000 3000 4000

bulkFinFETSiNWFETGeNWFETITRS(Planer)ITRS(SOI)ITRS(DG)

Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)

1

10

100

1000

10000

0 1000 2000 3000 4000


1

10

100

1000

10000

0 1000 2000 3000 4000


Bulk

DG

dia~3nm

dia~10nm

ITRS (SOI)

ITRS (DG)

ITRS(Bulk)

Si Nanowire

Ion (uA/um)

Ioff

(nA

/um

)Off Current

64

Nanowire FETNanowire FET

Nanowire FET

ITRS 2009

Multiple Gate (Fin)FET

Bulk → Fin → Nanowire

Siナノワイヤ

FinBulk or SOI

Si Nanowire

66

Si nanowire FET as a strong candidate

1. Compatibility with current CMOS process

2. Good controllability of IOFF

3. High drive current

1D ballisticconduction

Multi quantumChannel High integration

of wires

k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図

Quantum channelQuantum channel


k

E

量子チャネル

量子チャネル量子チャネル量子チャネル

バンド図



Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

Off電流のカットオフ

Gate:OFFDrain Source

cut-off

Gate: OFFdrainsource

Wdep

1

Leakage current

S D

Increase the Number of quantum channels

Energy band of Bulk Si

Eg

By Prof. Shiraishi of Tsukuba univ.

Energy band of 3 x 3 Si wire

4 channels can be used

Eg

67

Maximum number of wires per 1 µm

Surrounded gate type MOS

Front gate type MOS 165 wires /µm

33 wires/µm

High-k gate insulator (4nm)Si Nano wire (Diameter 2nm)

Metal gate electrode(10nm)

Surrounded gate MOS

30nm

6nm6nm pitchBy nano-imprint method

30nm pitch: EUV lithograpy

68

Device fabrication

Si/Si0.8Ge0.2superlatticeepitaxy on SOI

Anisotropicetchingof these layers

Isotropicetchingof SiGe

Gate depositions S/D implantationSpacer formationActivation annealSalicidation

BOXSi

SiGeSi

SiGeSi

SiGeSiN

BOX BOX

BOX

Gate

BOX

Gate

Gate etchingStandardBack-Endof-LineProcess

HfO2 (3nm)TiN (10nm)Poly-Si (200nm)

C. Dupre et al.,IEDM Tech. Dig., p.749, 2008

7

SiN HM

Process Details :

The NW diameteris controllabledown to 5 nm by self limited oxidation.

( )

Cross-section

50nm

SiN HM

Wire direction : <110>50 NWs in parallel3 levels vertically-stackedTotal array of 150 wires EOT ~2.6 nm

NWs

8

3D-stacked Si NWs with Hi-k/MG

BOX

500 nm

Sou

rce

Dra

in

Gate

Top view

<110>

SiNW Band structure calculation

Cross section of Si NW

[001] [011] [111]D=1.96nm D=1.94nm D=1.93nm

First principal calculation,

Si nanowire FET with 1D Transport[001] [011] [111]0.86 0.94 0.89

OrientationDiameter (nm)

[001] [011] [111]3.00 3.94 1.93

OrientationDiameter (nm)

ZG G GZ ZWave Number

ZG G GZ ZWave Number

Ener

gy (e

V)

0

-1

0

1

Ener

gy (e

V)

0

-1

0

1

(a)

(b)

Small mass with [011]

Large number of quantum channels with [001]

10 nm diameter Si(100)NW（ 2341 atoms）

20 nm diameter Si(100)NW （ 8941 atoms ）

Atomic models of a Si quantum dot and Si nanowires

6.6 nm diameter SiQD（ 8651 atoms）

2 6

26

( , , ) ( , , )n m nm

x y z C x m x y zx

ψ ψ=−

∂≈ + ∆

∂ ∑

1( ) ( ) ( ) ( )

Mesh

m n m i n ii

d x y zψ ψ ψ ψ=

≈ ∆ ∆ ∆∑∫ r r r r r

Real-Space Finite-DifferenceSparse MatrixFFT free (FFT is inevitable in the conventional plane-wave code)

Kohn-Sham eq. (finite-difference)

3D grid is divided by several regionsfor parallel computation.

Higher-order finite difference

Integration

MPI_ISEND, MPI_IRECV

MPI_ALLREDUCE

RSDFT – suitable for parallel first-principles calculation -

MPI ( Message Passing Interface ) library

)()()(ˆ)]([21 2 rrrr nnn

PPnlocs vv φεφρ =⎟

⎠⎞

⎜⎝⎛ ++∇−

CPU0

CPU8CPU7CPU6

CPU5CPU4CPU3

CPU2CPU1

Higher-order finite difference pseudopotential methodJ. R. Chelikowsky et al., Phys. Rev. B, (1994)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

|Vnew-Vold|^2

50403020100iteration

Convergence behavior for Si10701H1996

e.g.) The system over 10,000 atoms → Si10701H1996(7.6 nm diameter Si dot)

Massively Parallel Computing

Computational Time (with 1024 nodes of PACS-CS)

6781 sec. × 60 iteration step = 113 hour

Based on the finite-difference pseudopotential method (J. R. Chelikowsky et al., PRB1994)

Highly tuned for massively parallel computers

Computations are done on a massively-parallel cluster PACS-CS at University of Tsukuba.

(Theoretical Peak Performance = 5.6GFLOPS/node)

with our recently developed code “RSDFT”

Iwata et al, J. Comp. Phys., to be publishedReal-Space Density-Functional Theory code (RSDFT)

Grid points = 3,402,059Bands = 22,432

1.0

0.9

0.8

0.7

0.6

0.5

(eV

)

-0.6

-0.4

-0.2

0.0

(eV

)

1.2

1.1

1.0

0.9

0.8

0.7

(eV

)

-0.8

-0.4

0.0

0.4

(eV

)

3.4

3.2

3.0

2.8

2.6

(eV

)

-1.5

-1.0

-0.5

0.0

0.5

(eV

)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-12 -10 -8 -6 -4 -2 0 2(eV)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-12 -10 -8 -6 -4 -2 0 2(eV)

1.0

0.8

0.6

0.4

0.2

0.0DO

S ( S

tate

s / e

V a

tom

)

-10 -8 -6 -4 -2 0 2 4 6(eV)

Band Structure and DOS of Si(100)NWs (D=1nm, 4nm, and 8nm)

D = 4 nmSi341H84（425 atoms)KS band gap = 0.81eV

D=4nm D=8nmD=1nm

D=8 nmSi1361H164 (1525 atoms) KS band gap=0.61eV

D=1 nmSi21H20（41 atoms)KS band gap=2.60eV

KS band gap of bulk (LDA) = 0.53eV

Band structure of 8-nm-diameter Si nanowire near the CBM

1.0

0.9

0.8

0.7

0.6

0.5

(eV

)

0.300.250.200.150.100.050.00

･KS band gap = 0.608 eV (@Γ)

kz

kx

ky

82 meV (96 meV)

kx

Each band is4-dgenerate. 23 meV (24 meV)

)()()(22 2

2

*

2

2

2

2

2

*

2

rr Φ−=Φ⎥⎦

⎤⎢⎣

⎡

∂∂

−⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

+∂∂

− CBMlt zmyxm

εεhh

Effective mass equation

The band structure can be understood thatelectrons near the CBM in the bulk Si are Confined within a cylindrical geometry.

Si12822H1544（14,366 atoms）･10nm diameter、3.3nm height、(100)･Grid spacing：0.45Å (~14Ry)･# of grid points：4,718,592･# of bands：29,024･Memory：1,022GB～2,044GB

Si12822H1544

Top View Side View

Si nano wire with surface roughness

SiNW Band compact model

Landauer Formalism for Ballistic FET

From xmax to xmin

[ ][ ]∑

⎭⎬⎫

⎩⎨⎧

−+−+

⎟⎟⎠

⎞⎜⎜⎝

⎛=

i BiD

BiSi

BD TkE

TkEgqTkGI

/)(exp1/)(exp1ln

0

00 µ

µ

µS

µD

xO xmax xmin

Qf

Qb

k

Energy

µSµD

E0

E1

E2min

E2max

qVD

E2min

Qf

Qb

0

5

10

15

20

25

30

35

40

0 0.1 0.2 0.3 0.4 0.5

Drain Bias (V)

Current (uA)

IV Characteristics of Ballistic SiNW FET

T=1KT=300K

Vg-Vt=1.0 V

0.7 V

0.3 V

0.05 V

Small temperature dependency35µA/wire for 4 quantum channels

Model of Carrier Scattering

ChannelOpticalPhonon

Initial ElasticZone

Optical PhononEmission Zone

ε~kBT

ε*

Source

TransmissionProbability : Ti

Elastic Backscatt.Elastic Backscatt.＋（Optical Phonon Emission）

x00x

V(x)

F(0)

G(0)

Linear Potential Approx. ： Electric Field E

TransmissionProbability to Drain

To Drain

0Drain fromInjection )0()0()0()(

=⎟⎟⎠

⎞−=

FGFT ε

Résumé of the Compact Model

.)( 0

G

bfStG C

QQ

qVV

+=

−−−

µµα

.

22

ln

2

⎪⎭

⎪⎬⎫

⎪⎩

⎪⎨⎧

−+

++=

oxox

oxox

oxG

ttrttr

Cεπ

0 1 1 ( ( ))( ) ( ) ( )1 exp 1 exp 1 exp

f b i i ii i S i S i D

B B B

q dkQ Q g T k dkk k kk T k T k T

επ ε µ ε µ ε µ

∞

−∞ −∞

⎤⎡ ⎧ ⎫⎥⎢ ⎪ ⎪

⎪ ⎪ ⎥⎢+ = − −⎨ ⎬ ⎥⎢ ⎧ ⎫ ⎧ ⎫ ⎧ ⎫− − −⎪ ⎪+ + + ⎥⎢ ⎨ ⎬ ⎨ ⎬ ⎨ ⎬⎪ ⎪⎢ ⎥⎩ ⎭ ⎩ ⎭ ⎩ ⎭⎣ ⎩ ⎭ ⎦

∑ ∫ ∫

.ln

2

⎟⎠⎞

⎜⎝⎛ +

=

rtr

Cox

oxG

επDDS qV=− µµ

Unknowns are ID, (µS-µ0), (µD-µ0), (Qf+Qb)

[ ]( , ) ( , )i s D ii

qI g f f T dε µ ε µ επ

= −∑ ∫h

( )0

00 0 0 0 0

2( )

2 ln

D qET

qExB D D qE mD Bε

εε

=+⎛ ⎞+ + + ⎜ ⎟

⎝ ⎠

PlanarGate

GAA

(Electrostatics requirement)

(Carrier distributionin Subbands)

I-VD Characteritics (RT)

Electric current ２０～25 µANo satruration at Large VD

0

5

10

15

20

25

30

35

40

45

0 0.1 0.2 0.3 0.4 0.5 0.6

Drain Bias [V]

Current [uA]

VG-Vt=0.1V,Bal.

VG-Vt=0.1V,Qbal

VG-Vt=0.4V,Bal.

VG-Vt=0.4V,Qbal.

VG-Vt=0.7V,Bal.

VG-Vt=0.7V,Qbal.

VG-Vt=1.0V,Bal.

VG-Vt=1.0V,Qbal.

SiNW FET Fabrication

SiNW FET Fabrication

Sacrificial Oxidation

SiN sidewall support formation

Ni SALISIDE Process (Ni 9nm / TiN 10nm)

S/D & Fin Patterning

Gate Oxidation & Poly-Si DepositionGate Lithography & RIE EtchingGate Sidewall Formation

30nm

30nm

30nm

Oixde etch back

Standard recipe for gate stack formationBackend

(a) SEM image of Si NW FET (Lg = 200nm) (b) high magnification observation of gate and its sidewall.

88

Fabricated SiNW FET

30nm

Poly-Si

SiN

Nanow

ire

SiN support

SiNW

Lg=65nm, Tox=3nm

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

Dra

in C

urre

nt (µ

A)

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

0.8 V

0.6 V

0.4 V

0.2 V

(a)

10-12

Gate Voltage (V)

pFET nFET

(b)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

-1.0 -0.5 0.0 0.5 1.00

10 20 30 40 50 60 70

Dra

in C

urre

nt (µ

A)

Drain Voltage (V)

Vg-Vth=1.0 V

Vg-Vth= -1.0 V

0.8 V

0.6 V

0.4 V

0.2 V

(a)

10-12

Gate Voltage (V)

pFET nFET

(b)

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

Dra

in C

urre

nt (A

)

Vd=-50mV

Vd=-1V

Vd=50mV

Vd=1V

On/Off>106、60uA/wire

Recent results to be presented by ESSDERC 2010 next week in Sevile

Wire cross-section: 20 nm X 10 nm

010203040506070

1 10 100 1000Gate Length (nm)

I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V

括弧内は寸法を示す

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


(12)

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

010203040506070


I ON

(µA

/ w

ire)

nMOSpMOS

(5)

(5)

(10)

(10)(12)

(12x19)

(12)

(12x19)

(13x20)

(9x14)(10)

(10)

(10)

(8)

(8)

(16)

(13)

(34)

(3)(3)

(30)

(19)

VDD: 1.0~1.5 V


(12)

本研究で得られたオン電流

(10x20)102µA

Our Work

Bench Mark

Bench MarkBench MarkThis work Ref[11] Ref[12] Ref[13] Ref[14] Ref[15] Ref[4]

NW Cross-section (nm) Rect. Rect. Rect. Cir. Cir. Elliptical Elliptical NW Size (nm) 10x20 10x20 14 10 10 12 13x20

Lg (nm) 65 25 100 30 8 65 35EOT or Tox (nm) 3 1.8 1.8 2 4 3 1.5

Vdd (V) 1.0 1.1 1.2 1.0 1.2 1.2 1.0Ion(uA) per wire 60.1 102 30.3 26.4 37.4 48.4 43.8

Ion(uA/um) by dia. 3117 5010 2170 2640 3740 4030 2592Ion(uA/um) by cir. 1609 2054 430 841 1191 1283 825

SS (mV/dec.) 70 79 68 71 75 ~75 85DIBL (mV/V) 62 56 15 13 22 40-82 65

Ion/Ioff ~1E6 >1E6 >1E5 ~1E6 >1E7 >1E7 ~2E5

Ref[11] by Stmicro Lg=25nm,Tox=1.8nmThis work Lg=65nm,Tox=3nm

Y. Jiang, VLSI 2008, p.34H.-S. Wong, VLSI 2009, p.92S. Bangsaruntip, IEDM 2009, p.297C. Dupre, IEDM 2008, p. 749S.D.Suk, IEDM 2005, p.735G.Bidel, VLSI 2009, p.240

SiナノワイヤFET

Planer FETS. Kamiyama, IEDM 2009, p. 431P. Packan, IEDM 2009, p.659

1.2～1.3V

1.0～1.1V

Lg=500～65nm

IIONON/I/IOFF OFF Bench markBench mark

This work

95

1. Increase of Inversion Carrier Density

0 .E + 0 0

1 .E + 1 9

2 .E + 1 9

3 .E + 1 9

4 .E + 1 9

5 .E + 1 9

6 .E + 1 9

0 2 4 6 8Distance from SiNW Surface (nm)

6543210

角の部分

平らな部分

電子濃度(x1019cm-3)Electron Density

Edge portion

Flat portion

97

Evaluation of Inversion carrier extracted using advanced split-CV measurement

Higher inversion carrier density was obtained with smaller dimensions.

The result of two-dimensional simulation in the previous slide supports these experimental results.

0.E+00

5.E-15

1.E-14

2.E-14

0 20 40 600 20 40 600

5

10

15 Th

e am

ount

of

Inve

rsio

n C

arrie

r@

V g-V

th=1

.0V

(fC)

(a)

0.E+00

5.E-07

1.E-06

2.E-06

2.E-06

0 20 40 60 80 100 1200 20 40 60 SOI 0

1

2

1.5

0.5

Inve

rsio

n C

arrie

rD

ensi

ty@

V g-V

th=1

.0V

(µC

/cm

2 )

(b)

Peripheral Length (nm)

A(10x9)

B(12x19)C(12x28) A(10x9)

B(12x19)

C(12x28)

(hNWxwNW)nm2 (hNWxwNW)nm2

Peripheral Length (nm) H. Irie et al., Solid State Devices and Materials, 2005.

64 channels

98

2. Enhancement of Effective Carrier Mobility

0

2000

4000

6000

8000

10000

12000

2008 2010 2012 2014 2016 2018 2020 2022 2024 2026

Year

I ON

(µA/

µm)

SiNW (12nm×19nm)

MGFDbulk

ION∝Lg-0.5×Tox

-1(20)

(11)

(33)

(15)

(26)

今回用いたIONの仮定

1µm当たりの本数

コンパクトモデルの完成

S/D寄生抵抗低減技術

pMOSの高性能化

低EOT実現技術

Compact model

Small EOT for high-k

P-MOS improvement

Low S/D resistance

# of wires /1µm

Assumption

ITRSNan

owire

Primitive estimation !

Our roadmap for R &D Source: H. Iwai, IWJT 2008

Current Issues

III-V & Ge NanowireHigh-k gate insulatorWire formation technique

CNT:

Width and Chirality control Growth and integration of CNT

Graphene:Graphene formation technique Suppression of off-current

Very small bandgap or no bandgap (semi-metal)

Control of ribbon edge structure which affects bandgap

Chirality determines conduction types: metal or semiconductor

100

Si NanowireControl of wire surface property

Compact I-V model

Source Drain contactOptimization of wire diameter

Brain Ultra small volumeSmall number of neuron cellsExtremely low power

Real time image processing(Artificial) Intelligence3D flight control

Sensor

InfraredHumidityCO2

Mosquito

Dragonfly is further highperformance

System andAlgorism becomes more important!

But do not know how?

past and future trends 0f integrated circuit …past and future trends 0f integrated circuit...

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