UNIVERSITY OF ENGINEERING

AND MANAGEMENT

PROJECT

REPORT

BY

SOUDIP SINHA

ROY

VERY LARGE SCALE

INTEGRATION ( VLSI )

NAME OF PROJECT: PARRAL

ADDEER BRANCH: ECE

DATE : 22/01/2015

Acknowledgement

This project would not have been possible without the

kind support and help of many individual organization.

First of all I would like to express my lot of thanks to all

of them.

I’m highly thankful to Prof. Arindam Chakrabarti,

Angshuman Roy,Madhusudhan Baida and Prabir Kumar

Das for their guidance and constant supervisation as

well as providing information regarding the project. And

I’ve completed my project by a huge avocation.

I would like to express my gratitude towards my

parents & the all members of Institute Of Engineering

And Managemnet for their kind co-operation and

encouragement for the completation of my project.

I would like to express my special acknowledgement

to the industry persons for giving me such attention

and their valuable time.

My application is also goes to my collegious in

developing the project and people who’ve helped me

out as their abalities.

Abstruct

A Very Large Scale Integration device is just the

sattlement of a very large number of transistors. So,

now in the present market this technology is very

crucial. Let me speak something about this. VLSI

technology is used in almost very aspect of industry to

expand and enhance the efficiency. By mid eighties, the

transistor count on a single chip had already exceeded

1000 and hence came the age of Very Large Scale

Integration or VLSI. Though many improvements have

been made and the transistor count is still rising, further

names of generations like ULSI are generally avoided. It

was during this time when TTL lost the battle to MOS

family owing to the same problems that had pushed

vacuum tubes into negligence, power dissipation and

the limit it imposed on the number of gates that could

be placed on a single die. Here the millions of million

transistors ( ex : 1*1 area 80 millions ) are assembled

inside the circuit. For that a huge power o/p we can get

from single IC chip. This thing is also implemented with

the help of some softwares and some different types of

languages. And on the basic pogramable logic

controlling system this kind of devices are mainly

constructed. It is very much usefull for eatch and every

digitial circuits we can see severaly in market.

INDEX

PARALLEL ADDER

o Introduction

o Types of adder

o Basic adder unit

Half adder

Full adder

Ripple carry adder

Carry skip adder

VLSI PROJECT

o Title

o Block Diagram

o Program Code

Sub-module

Main-module

Test module

o Output

o Discussion

APPENDIX

BIBLIOGRAPHY

PARALLEL ADDER

INTRODUCTION:

The saying goes that if you can count, you can control. Addition is a fundamental operation

for any digital system, digital signal processing or control system. A fast and accurate operation

of a digital system is greatly influenced by the performance of the resident adders. Adders are also

very important component in digital systems because of their extensive use in other basic digita l

operations such as subtraction, multiplication and division. Hence, improving performance of the

digital adder would greatly advance the execution of binary operations inside a circuit

compromised of such blocks. The performance of a digital circuit block is gauged by analysing its

power dissipation, layout area and its operating speed.

TYPES OF ADDER:

In this lecture we will review the implementation technique of several types of adders and

study their characteristics and performance. These are:

Ripple carry adder,

Carry look-ahead adder,

Carry skip adder,

Manchester chain adder,

Carry select adders,

Pre-Fix Adders,

Multi-operand adder,

Carry save Adder,

Pipelined parallel adder,

For the same length of binary number, each of the above adders has different performance

in terms of Delay, Area, and Power. All designs are assumed to be CMOS static circuits and they

are viewed from architectural point of view.

BASIC ADDER UNIT:

The most basic arithmetic operation is the addition of two binary digits, i.e. bits. A

combinational circuit that adds two bits, according the scheme outlined below, is called a half

adder. A full adder is one that adds three bits, the third produced from a previous addition

operation. One way of implementing a full adder is to utilizes two half adders in its

implementation. The full adder is the basic unit of addition employed in all the adders studied here.

Half Adder:

A half adder is used to add two binary digits together, A and B. It produces S, the sum of

A and B, and the corresponding carry out Co. Although by itself, a half adder is not extremely

useful, it can be used as a building block for larger adding circuits (FA). One possible

implementation is using two AND gates, two inverters, and an OR gate instead of a XOR gate as

shown in Fig. 1

Full Adder:

A full adder is a combinational circuit that performs the arithmetic sum of three bits: A, B

and a carry in, C, from a previous addition, Fig. 2a. Also, as in the case of the half adder, the full

adder produces the corresponding sum, S, and a carry out Co. As mentioned previously a full adder

maybe designed by two half adders in series as shown below in Figure 2b. The sum of A and B

are fed to a second half adder, which then adds it to the carry in C (from a previous addition

operation) to generate the final sum S. The carry out, Co, is the result of an OR operation taken

from the carry outs of both half adders. There are a variety of adders in the literature both at the

gate level and transistor level each giving different performances.

Parallel Adder:

Parallel adders are digital circuits that compute the addition of variable binary strings of

equivalent or different size in parallel. The schematic diagram of a parallel adder is shown below

in Fig. 3.

Ripple Carry Adder:

The ripple carry adder is constructed by cascading full adders (FA) blocks in series. One

full adder is responsible for the addition of two binary digits at any stage of the ripple carry. The

carryout of one stage is fed directly to the carry-in of the next stage.

A number of full adders may be added to the ripple carry adder or ripple carry adders of

different sizes may be cascaded in order to accommodate binary vector strings of larger sizes. For

an n-bit parallel adder, it requires n computational elements (FA). Figure 4 shows an example of

a parallel adder: a 4-bit ripple-carry adder. It is composed of four full adders. The augend’s bits of

x are added to the addend bits of y respectfully of their binary position. Each bit addition creates a

sum and a carry out. The carry out is then transmitted to the carry in of the next higher-order bit.

The final result creates a sum of four bits plus a carry out (c4).

Even though this is a simple adder and can be used to add unrestricted bit length numbers,

it is however not very efficient when large bit numbers are used.

One of the most serious drawbacks of this adder is that the delay increases linearly with

the bit length. As mentioned before, each full adder has to wait for the carry out of the previous

stage to output steady-state result. Therefore even if the adder has a value at its output terminal, it

has to wait for the propagation of the carry before the output reaches a correct value as shown in

Fig. 5. Taking again the example in figure 4, the addition of x4 and y4 cannot reach steady state

until c4 becomes available. In turn, c4 has to wait for c3, and so on down to c1. If one full adder

takes Tfa seconds to complete its operation, the final result will reach its steady-state value only

after 4.Tfa seconds. Its area is n Afa

A (very) small improvement in area consumption can be achieved if it is known in advance

that the first carry in (c0) will always be zero. (If so, the first full adder can be replace by a half

adder). In general, assuming all gates have the same delay and area of NAND-2 denoted by T gate

and Agate then this circuit has 3n T gate delay and 5nAgate. n is the number of full adders. (One

must be aware that in Static CMOs, this assumption is not true). Gate delays depend on intrins ic

delay + fan(in) delay + fan(out) delay.

Carry Propagation in Carry Ripple Adder

Generally speaking, the worst-case delay of the RCA is when a carry signal transition

ripples through all stages of adder chain from the least significant bit to the most significant bit,

which is approximated by:

where tc is the delay through the carry stage of a full adder, and ts is the delay to compute

the sum of the last stage. The delay of ripple carry adder is linearly proportional to n, the number

of bits, therefore the performance of the RCA is limited when n grows bigger. The advantages of

the RCA are lower power consumption as well as a compact layout giving smaller chip area.

To design a larger adder ripple carry adders are cascaded. An example of 37 bit carry

propagate adder is shown in Fig. 6

As of today standards, it is a common philosophy that area can be traded off in order to

achieve higher speed. This will be shown in the next sections by presenting alternative methods

that are based on pre-determining the carry signal of a number of stages based only on the input

vales.

Carry Skip Adder:

A carry-skip adder consists of a simple ripple carry-adder with a special speed up carry

chain called a skip chain. This chain defines the distribution of ripple carry blocks, which compose

the skip adder.

Carry Skip Mechanism:

on the carry in, Ci , which in reality is the carry out, Ci-1, of the previous stage. Therefore, in order

to calculate the sum and the carry out, Ci+1 , of stage i, it is imperative that the carry in, Ci, be

known in advance. It is interesting to note that in some cases Ci+1 can be calculated without

knowledge of Ci.

Boolean Equations of a Full Adder:

Therefore, if Equation 4 is true then the carry out, Ci+1, will be one if Ai = Bi = 1 or zero

if Ai = Bi = 0. Hence we can compute the carry out at any stage of the addition provided equation

4 holds. These findings would enable us to build an adder whose average time of computation

would be proportional to the longest chains of zeros and of different digits of A and B.

Alternatively, given two binary strings of numbers, such as the example below, it is very

likely that we may encounter large chains of consecutive bits (block 2) where Ai Bi. In order to

deal with this scenario we must reanalyse equation 3 carefully.

In order to take advantage of the last property, we can design an adder that is divided into

blocks, as shown in Fig. 7, where a special purpose circuit can compare the two binary strings

inside each block and determine if they are equal or not. In the latter case the carry entering the

block will simply be propagated to the next block and if this is the case all the carry inputs to the

bit positions in that block are all either 0’s or 1’s depending on the carry in into the block. Should

only one pair of bits (Ai and Bi) inside a block be equal then the carry skip mechanism would be

unable to skip the block. In the extreme case, although still likely, that there exist one such case,

where Ai = Bi, in each block, then no block is skipped but a carry would be generated in each

block instead.

Two strings of binary numbers to be added are divided into blocks of equal length. In each

cell within a block both bits are compared for un-equivalence. This is done by Exclusive ORing

each individual cell (parallel operation and already present in the full adder) producing a

comparison string. Next the comparison string is AND end within itself in a domino fashion. This

process ensures that the comparison of each and all cells was indeed unequal and we can therefore

proceed to propagate the carry to the next block. A MUX is responsible for selecting a generated

carry or a propagated (previous) carry with its selection line being the output of the comparison

circuit just described. If for each cell in the block Ai ≠ Bi then we say that a carry can skip over

the block otherwise if Ai = Bi we shall say that the carry must be generated in the block.

When studying carry skip adders the main purpose is to find a configuration of blocks that

minimizes the longest life of a carry, i.e. from the time of its generation to the time of the generation

of the next carry. Many models have been suggested: the first with blocks of equal size and the

second with blocks of different sizes according to some heuristic.

The delay of n-bit adder based on m-bit blocks of Carry Bypass Adder, CBA rippled

together. n is the adder length and m is the length of the blocks Comparing to the RCA, the CBA

has slightly improved speed for wider-bit adders (still linear to n), but with higher active

capacitance and the area overhead because of the extra bypass circuit.

VLSI PROJECT

TITLE: Design and simulate 4-Bit Parallel Adder using structural architecture style

using VHDL environment.

Addition of two binary numbers

1 1 0 1

+ 1 0 0 1

---------------------

BLOCK DIAGRAM:

PROGRAM CODE:

Sub-module:

entity soudip is

port(a,b,c:in bit; y,z:out bit);

end entity;

architecture dataflow of soudip is

begin

y<=(a xor (b xor c));

z<=((a and b) or (b and c) or (c and b));

end architecture;

Main-module:

entity soudip_1 is

port(d,e,f,i,j,k,l,m,n:in bit; a1,a2,a3,a4,b4:out bit);

end entity;

architecture dataflow of soudip_1 is

component soudip is

port(a,b,c:in bit; y,z:out bit);

end component;

signal b1,b2,b3:bit;

begin

palash port map (d,e,f,a1,b1);

palash port map (i,j,b1,a2,b2);

palash port map (k,l,b2,a3,b3);

palash port map (m,n,b3,a4,b4);

end architecture;

Test-madule:

entity soudip_2 is

end entity;

architecture mixed of soudip_2 is

signal z1,z2,z3,z4,z5,z6,z7,z8,z9,y1,y2,y3,y4,y5:bit;

component palash_1 is

port(d,e,f,i,j,k,l,m,n:in bit; a1,a2,a3,a4,b4:out bit);

end component;

begin

soudip_1 port map (z1,z2,z3,z4,z5,z6,z7,z8,z9,y1,y2,y3,y4,y5);

process

begin

z1<='1';

z2<='1';

z3<='0';

wait for 30ns;

z4<='0';

z5<='0';

wait for 30ns;

z6<='1';

z7<='0';

wait for 30ns;

z8<='1';

z9<='1';

wait for 30ns;

end process;

end architecture;

OUTPUT:

1 1 0 1

+ 1 0 0 1

------------------------

(1) 0 1 1 0

DISCUSSION:

Ripple carry adder delays In the ripple carry adder, the output is known after the carry

generated by the previous stage is produced. Thus, the sum of the most significant bit is only

available after the carry signal has rippled through the adder from the least significant stage to the

most significant stage. As a result, the final sum and carry bits will be valid after a considerable

delay.

Hence we can design and simulate this 4-bit parallel adder by structural architecture using

VHDL environment in help of PEAK-VHDL simulator software. By this simulation we can

produce sum of this given binary numbers.

APPENDIX

How to use Accolade Peak VHDL

1. Launch software from "Start\Programs\Accolade Peak VHDL\Peak VHDL Version4", or

launch it from the icon on the screen.

2. On VHDL package go to "File\New Project"

3. The "New Project" window appears, go to "File\Save Project As". (Save as "A:\Halfadd.acc").

Half add is the name of the project and A is the directory where the project will be stored. A

can be C:\temp or any other location; you have to remember where you store your work.

4. Click "File\New Module".

5. Click "Module Wizard". (Leaving the "Add New Module To Project" box, checked!)

6. Enter Entity Name: "HA".

7. Enter Architecture Name: "HA_ARC".

8. Enter Port Name: "A", Mode: "in", Type: "std-logic".

9. Click "Add Port".

10. Repeat steps 8 & 9, changing the 'Mode' accordingly, until all entity ports are accounted for.

11. Click "Create", and save as "A:\Ha.vhd". A screen appears showing the information you

already entered including the name and location of the module.

12. Edit "Ha.vhd". Enter YOUR Name & Project Name in the comment lines at top of file. Delete

Extra lines of code not needed by YOUR project. (Clock, Reset, etc.) Insert necessary lines of

code into YOUR project.

13. Click "File\Save module".

14. Minimize "Ha.vhd" file and highlight the "Ha.vhd" Module on the "Project" window.

15. Click the "Compile" Button.

16. If compilation errors occur, correct the errors and repeat step 15 until compilation is

successful.

17. Once Project compiles properly, a TEST file will be needed to simulate the VHDL program.

18. Click "File\Rebuild Heirarchy"

19. Highlight "Ha.vhd" in the "Project" window.

20. Click "File\New Module".

21. Click "Test Bench Wizard". (Leaving the "Add New Module To Project" box, checked!)

22. If you followed the above steps properly, the "Entity Name" should already be "HA".

23. Change "Architecture Name" to "HA_ARC".

24. All the "Port" information should be correct also. If this information did not appear you have

to enter it manually.

25. Click "Create".

26. Save file as "A:\Test-HA.vhd".

27. Delete Extra lines of code not needed by YOUR project. (Clock section, signal done: boolean

: = false, Resets, etc.)

28. Insert necessary Test lines of code into YOUR project.

29. (A <= '0' ; B <= 'O'; wait for Period;)

30. Click "File\Save".

31. Minimize "Test Ha.vhd" file and highlight the "Test Ha.vhd" Module in the "Project" window.

32. Click the "Compile" Button.

33. If compilation errors occur, correct the errors and repeat step 32 until compilation is

successful.

34. Once Project compiles properly, a SIMULATION of the logic needs to be done.

35. Click "File\Rebuild Heirarchy".

36. Highlight "Test-Ha.vhd" in the "Project" window.

37. Go to "Simulate\Load Selected".

38. Click "Add All"& "Close".

39. Click "Go", & the Wave-Forms appear. If signals match corresponding logic, then program is

finished!

· NOTES:

· To Print the Wave-Forms use the "Landscape" Setting.

· You may need to ZOOM out from the Wave-Forms to print entire segment.

· Make sure that the "Run to Time", under "Synthesize\Option\Simulate", is long enough to

complete the testing of your project.

BIBLIOGRAPHY

Information is taken from bellow link:

http://www.ece.uvic.ca/

http://virtual-labs.ac.in/

This simulation is run by PEAK-VHDL software.

THANK YOU