paging ppt
TRANSCRIPT
04/07/23 1Veer Singh(5073)
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Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Divide logical memory into blocks of same size called pages.
Veer Singh(5073)04/07/23
3 Divide physical memory into fixed-sized blocks called frames
The size of the page is power of 2, between 512 bytes and 16 MB per page. Selection of a power of 2 makes the translation from logical address to page no and page offset easy.
Keep track of all free frames.
Veer Singh(5073)04/07/23
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To run a program of size n pages, need to find n free frames and load program.
Set up a page table to translate logical to physical addresses.
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Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory.
Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.
Veer Singh(5073)04/07/23
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CPU P d f d
________ ________
f
________ ________
f000...000
f111…111
Logical address
Physical address
Physical memory
Page table
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Page 0
Page 1
Page 2
Page 3
2
4
5
7
Page 0
Page 1
Page 2
Page 3
0
1
2
3
4
5
6
7
0
1
2
3
Page table
Logical memory
Physical memory
Frame no.
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ab c d e f g h
i jk l
m nop
5
6
1
2
i j k l
m n o p
a b c d
e f g h
0
4
8
1216
20
24
0
1
2
3
Page table
Logical memory
Physical memory
0123
4567
8 91011
12131415
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Page 0Page 1Page 2Page 3
Page 0Page 1Page 2Page 3
Page 1
Page 0
Page 2
Page 3
Free frame list 14 13 18 20 15
Free frame list 15
1413
18
20
0123
New process page table
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20(a) (b)
Page table is kept in main memory.
Page-table base register (PTBR) points to the page table.
Page-table length register (PTLR) indicates size of the page table.
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In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called translation look-aside buffers (TLBs)04/07/23 Veer Singh(5073) 11
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CPU P d
____________
f
____________
Page table
Physical memory
Logical address
f d
Physical address
Page number
Frame number
TLB
TLB hit
TLB miss
Any Question……Plz Dnt Ask
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