pad manual

Procedural Analog Design (PAD) Tool Users Manual

Procedural Analog Design (PAD) Tool is a chart-based design

tool dedicated to the design of analog circuits aiming to optimise

design and quality by finding good tradeoffs of basic analog

structures.

This interactive tool allows step-by-step design of analog cells by

using guidelines for each analog structure. At each step, one subset of

design parameters can be changed interactively and the effect on

other circuit parameters can be observed. An optimised design is

ready for simulation (verification and fine-tuning).

PAD provides a layout generator for transistor cells and matched

structures, such as: current mirror, differential pair.

The analog basic structures calculator uses complete set of

equations of EKV MOS model, which links the equations for weak and

strong inversion in a continuous way.

1

What can be designed? The present version of PAD covers:

1) design and sizing of basic analog structures:

NMOS transistor cell

PMOS transistor cell

N current mirror

P current mirror

N differential pair

P differential pair

N cascode mirror

P cascode mirror

N cascode stage

P cascode stage

N cascode pair

P cascode pair

N folded cascode pair

P folded cascode pair

2) procedural analog design of complex analog structures:

OTA

Miller OpAmp

Folded Cascode OTA

2

Start PAD tool

Double click the program icon.

Choose basic or complex analog structure (that will be designed) from the list and click OK (or double click the item in the list).

Follow step-by-step design of analog structures by using guidelines for each analog topology.

In every step two windows are displayed on the screen:

the explication window – with the guidelines and explications

the design window – with the appropriate graphical

representations

3

For normal view → the explication window + the design window,

click Normal view:

on the Standard toolbar.

For design window on top → the explication window is hidden under

the design window, click Design Window on top:


For the navigation use:

The buttons Next / Previous in the explanation window or


Reset button will reset all parameters to default values.

To create a new design:

On the File menu, click New, choose basic or complex analog structure from the list and click OK (or double click the item in the list)

or Click New on the Standard toolbar, choose basic or

complex analog structure from the list and click OK (or double click the item in the list)

4

Save and Open design

To save a design:

click Save on the Standard toolbar, locate and open the

folder.

In the File name box, type a name for the design.

The design is saved as name.pad.

To open a design:

On the File menu, click Open, locate and open the folder in which the design was saved, double click the design you want to open

or Click Open on the Standard toolbar, locate and open the

folder in which the design was saved, double click the design you want to open

5

Basic analog structure design and sizing

Basic analog structure design and sizing consists of two steps:

initialisation

design and sizing

Initialisation – Enter EKV model parameters and the bias

information (supply voltages, bias voltages, bias current…) that

depends on basic analog structure.

the bias information and the basic analog structure scheme

EKV model params

6

Design and sizing –The user interface has the same appearance, for every basic analog structure.

• terminal voltages

• saturation voltages

• threshold voltages

• scheme

• general parameters

• specific parameters

• layout

geometrical dimensions:

• W • L • W/L

•

c

p

e

a

c

o

bias current(s)
generation
DC voltages and currents and geometrical dimensions can be

hanged interactively. When the parameter’s value is changed, it is

ossible to choose how this change will be performed. This will be

xplained in details in transistor cell sizing.

At the same time, general and specific parameters are calculated

nd displayed in form of appropriate graphical representations.

General parameters are parameters that are defined and

alculated for simple transistor cell.

Specific parameters are defined and related to the behaviour of

ther basic analog structures. All these parameters are displayed and

7

classified in form of cards: params, noise, mismatch, small signal

params, speed, etc. This will be explained for each basic analog

structure.

Card layout is for layout generation. (See transistor cell.)

It is possible to change displayed parameter’s range, if a slider

is used as a graphical representation.

Click the minimum/maximum range value and a dialog will be

displayed on the screen:

Enter a new value and click OK.

8

NMOS / PMOS transistor cell Initialisation → Enter EKV model parameters, terminal voltages

(gate, drain, source and bulk voltages) and transistor width and length.

Users interface →

DC params →

All terminal voltages Vg, Vs, Vd, Vb can be changed. Respect

Vd > Vs for NMOS, and Vs >Vd for PMOS transistor.

Threshold voltage and saturation voltage are calculated and indicated.

For PMOS transistor a negative sign is given for these voltages.

By default, when the geometrical dimensions: transistor width,

transistor length and W/L ratio are changed, the transistor current is

9

considered constant and the change influence voltage Vg. Following

options are possible:

if W (L) is changed

to Vg, Idsat constant → (default) Idsat is considered

constant and the change influence Vg

W/L constant → the ratio W/L is kept constant, a new

value for L (W) is calculated

W/L variable → Vg is considered constant, a new value

for Idsat is calculated (and a new value for the ratio W/L

is calculated)

if the ratio W/L is changed

to Vg, L const → (default) Idsat is considered constant

and the change influence Vg (L is kept constant, a new

value for W is calculated)

to Vg, W const → Idsat is considered constant and the

change influence Vg (W is kept constant, a new value for

L is calculated)

W constant → Vg is considered constant, a new value for

Idsat is calculated (W is kept constant, a new value for L

is calculated)

10

L constant → Vg is considered constant, a new value for

Idsat is calculated (L is kept constant, a new value for W

is calculated)

If W < Wmin or L < Lmin, the warning is displayed!

→ the indication of weak/moderate/strong inversion

→ the indication of linear/saturation region

Transistor drain current Id and transistor saturation drain current Idsat

are calculated and displayed. If Idsat < 1pF, too small current, the

warning is displayed!

If a new value for the current is calculated or the current is

changed that refers to Idsat. The value of the voltage Vd

determines if the transistor is in linear region or in saturation

region, and the corresponding value for Id is calculated. The

blue area inside Id slider corresponds to Idsat value.

If Idsat is changed following options are possible:

to Vg → the geometrical dimensions are kept constant

and a new value for the voltage Vg is calculated

11

to Vg, Vd the same → the transistor is considered like

diode-connected and the corresponding voltage is

calculated

to L → the voltage Vg is considered constant and a new

value for transistor length is calculated

to W → the voltage Vg is considered constant and a new

value for transistor width is calculated

to W/L, L const → the voltage Vg is considered constant

and a new value for the ratio W/L is calculated, where L

is kept constant

to W/L, W const → the voltage Vg is considered constant

and a new value for the ratio W/L is calculated, where W

is kept constant

General parameters →

params:

gm/Idsat

Early voltage ds

dsatA g

IE =

transcoductance efficiency factor dsat

tm

IVgn

tef⋅⋅

=

graph → transcoductance efficiency factor tef in function of

inversion factor if

12

red point traces parameters changes clear → deletes white trace, red point will stay in the current position

noise:

thermal noise 2

14_mg

qikTthermalv β=

flicker noise AFfCOXLeffWeffKFflic

⋅⋅⋅=ker_v

equivalent noise 22 ker___ flicvthermalveqv +=

corner frequency

small signal params :

transcoductances gm, gds, gmbs

gain - gm/gds(dB)

output resistance – 1/gds

inversion factor (the value and the indication)

speed:

intrinsic capacitances Cgs, Cgd, Cgb, Csb, Cdb

overlap capacitances Cgsov, Cgdov, Cgbov

transition frequency gs

m

Cg

ftπ2

=

13

Layout generation →

• transistor width • transistor length • number of devices in

case of long L (W) • layout type (for

transistor cell only) • area

redraw – to redraw the layout when geometrical dimensions are changed export – to export the current version in the buffer

The layout is automatically generated. When the transistor

dimensions are changed, click redraw button to redraw a new layout

version. To export the current layout version click export button and

it will be saved in the internal buffer. This can be repeated as many

times as it is needed. All exported versions of the layout (one by one,

in the order in which they were exported) are saved in the internal

buffer. But, the exported layout will be saved only if CIF file is

created and saved.

To save exported layout click Define CIF file name:

on the Standard toolbar → In the CIF File name box, type

a name and click OK.

then click Save CIF file:

on the Standard toolbar → to save CIF file.

After this action, generated layout is exported and saved and can be

imported in any layout editor.

To empty the internal buffer click Empty buffer:

14


→ In the present tool version it is not possible to change the setup for layout

generation.

N / P current mirror Initialisation → Enter EKV model parameters, the supply voltages,

the bias current, current mirror ratio (the ratio between mirrored

current and bias current) and transistor width and length. Users interface →

Following parameters can be changed: the bias current, current mirror ratio and the width and length of

transistor mb.

15


See general parameters for the transistor cell.

Specific parameters →

mismatch:

current mismatch

WL

A

WLA

Idg

IdId

vtT

Tm

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

in %

IdIdId

I100

)(δσ=∆ in uA

graph → current mismatch in function of inversion factor if

small signal params:

current mirror output resistance – rout

speed:

capacitance seen in the gate of tran m1 – Cg1

capacitance seen in the drain of tran m1 – Cd1

16


N / P differential pair Initialisation → Enter EKV model parameters, the supp

the drain current and the input voltage. Users interface →

17

see transistor

cell

ly voltages,

From the initial conditions the ratio W/L is proposed.

Terminal voltages are always set like:

VthVgVdVthVgVs+=−=

This condition enables to design with large dynamic.

Following parameters can be changed:

the drain current and transistor width and length.

Following options are possible:

if W (L) is changed


value for L (W) is calculated (the drain current is

constant, terminal voltages change)

W/L variable → a new value for the ratio W/L is

calculated (the drain current is constant, terminal voltages

change)

if W/L changed

L constant → L is kept constant, a new value for W is


change)

18

W constant → W is kept constant, a new value for L is


change)




mismatch:

voltage mismatch

WL

A

WLA

gIdVg

vtT

mT

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

in mV

graph → voltage mismatch in function of inversion factor if


see transistor cell

19

N / P cascode mirror Initialisation → Enter EKV model parameters, the supply voltages,

the drain current, transistor length and width and transistor length ratio

n. Users interface →

Transistor m1 and m2 are designed to be on the edge of saturation.

For given transistor width and length, the voltage Vg1 is calculated.

Transistor m3 and m4 are designed like:

1313LnL

WW⋅=

=

For given terminal voltages and drain current, the voltage Vbias is

calculated.

20


the drain current, transistor m1(m2) width and length and transistor

length ratio n.



N / P cascode stage

Initialisation → Enter EKV model parameters, the supply voltages,

the drain current and the input voltage. Users interface →

21

From the initial conditions the ratio (W/L)1 is proposed, where

terminal voltages are always set like:

13

111

111

VdVsVdsVsVd

VthVsVg

sat

=

+=

+=

For given drain current and ratio (W/L)3 the voltage Vbias is

calculated.


transistors’ widths and lengths, the input voltage and the drain current.

Following options are possible for both transistors:

if W (L) is changed


value for L (W) is calculated (the drain current is

constant, a new value for Vbias is calculated)


calculated (the drain current is constant, a new value for

Vbias is calculated)

if W/L changed

22











cascode stage output resistance 31

3

dsds

m

ggg

rout⋅

=

gain (approximation)

⋅

⋅=

3

3

1

1

21

ds

m

ds

m

gg

gg

A

speed:

input capacitance – Cin

23

N / P cascode pair

Initialisation → Enter EKV model parameters, the supply voltages,

the drain current, the input and the bias voltage. Users interface →



VbiasVgVdVs

VthVgVdVthVgVs

VinVg

==

+=−=

=

3

13

111

111

1

24

The ratio (W/L)3, as well as input and bias voltages can be changed

interactively. (Always check the mode of operation, the polarisation

and the transcoductances of all transistors). Following options are possible for both transistors:

if W (L) is changed


value for L (W) is calculated


calculated

if W/L changed


calculated


calculated



25


mismatch:

voltage mismatch (input pair)

WL

A

WLA

gIdVg

vtT

mT

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

in mV




3

dsds

m

ggg

rout⋅

=


⋅

⋅=

3

3

1

1

21

ds

m

ds

m

gg

gg

A

speed:


26

N / P folded cascode pair

Initialisation → Enter EKV model parameters, the supply voltages

and the input currents. Users interface →



13

111

111

1

2

VdVsVthVgVd

VthVgVsVinVg

VssVddVin

=+=

−==

−=

For given drain current and ratio (W/L)3, the voltage Vbias is

calculated.

27


transistors’ widths and lengths and the drain currents.

Following options are possible for both transistors:

if W (L) is changed


value for L (W) is calculated (the drain currents are

constant, a new value for Vbias is calculated)


calculated (the drain currents are constant, a new value

for Vbias is calculated)

if W/L changed









28


mismatch:

voltage mismatch (input pair)

WL

A

WLA

gIdVg

vtT

mT

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

in mV




3

dsds

m

ggg⋅

=rout


⋅

⋅=

3

3

1

1

21

ds

m

ds

m

gg

gg

A

speed:

pole (approximation) 3

3

22_

gs

m

Cg

polef⋅

=π


29

Procedural analog design of complex structures

Present PAD version covers analog design of following complex

analog structures:

OTA

Miller Amplifier

Folded Cascode

Procedural analog design for each analog structure consists of:

initialisation

circuit partitioning

basic analog structures sizing

circuit summary

Initialisation – The user is asked to enter NMOS and PMOS EKV

model parameters and the information for circuit initialisation (initial

design requirements, the supply voltages, the bias current, load and

compensation capacitances).

30

scheme of analog structure

• supply voltages

• bias current

initial design requirements: • SR • GBW • power

dissipation

• loaca

• co ca

Circuit partitioning – The circuit partitioning sequenc

analog structures) and the equation set (that describes circ

are proposed for every complex structure. Follow gu

explanations for every design step.

Basic analog structures sizing – From the in

requirements, the values for some circuit parameters will

For each block, using the same procedure as described in B

structure design and sizing, the user can modify par

observe impact of his decisions on circuit performances.

Circuit summary – Circuit performance can be che

and after sizing of each block.

31

d pacitance mpensationpacitance

e (into basic

uit behavior)

idelines and

itial design

be proposed.

asic analog

ameters and

cked, during

circuit performances can be checked and compared with initial design requirements

Following circuit parameters are calculated:

gain

CMRR

PSRR

equivalent input noise, corner frequency

offset voltage

positive / negative CMR

output swing

SR

GBW

power dissipation

phase margin

Frequency analysis is proposed, after basic analog structures design

steps.

32

the approximations for poles and zeros

phase margin in function of Cc (or Cl)

→ After having designed all building blocks, circuit level behavior is

summarized.

33

OTA design

Read the introduction, and follow proposed procedure and

guidelines in the program.

→ Circuit scheme and proposed partitioning for n input OTA:

VSS

VDD

1

2

3A

B

→ Design sequence is following:

1. n current mirror 2. n differential pair 3. p current mirror

34

→ Circuit scheme and proposed partitioning for p input OTA:

1

2

3A

B


1. p current mirror 2. p differential pair 3. n current mirror

→ Circuit-level design equations:

slew rate

LCI

SR 1=

gain bandwidth

frequency

1_2

m

L

gf GBW

Cπ=

gain 41

1

dsds

m

ggg

A+

=

positive/negative

CMR (n input)

25_

22_3_3

thsatdsss

thsatdssatdsthdd

VVVCMR

VVVVV

++=−

+−+−=+CMR

(p input) 22_3_3

25_

thsatdssatdsthss

thsatdsdd

VVVVVCMR

VVV

−+++=−

−−=+CMR

35

output swing (n input) 5_1_3_

_

satdssatdssatdsssdd

swingout

VVVVV −−−−

V =

(p input) 5_1_3_

_

satdssatdssatdsssdd

swingout

VVVVV −−−−

V =

CMRR 45

412dsds

mm

gggg

CMRR⋅⋅

=

current

mismatch

(curr mirr) WL

A

WLA

Idg

IdId

vtT

Tm

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

voltage

mismatch

(diff pair) WL

A

WLA

gIdVg

vtT

mT

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

equivalent noise

( )24

23

2

1

4

22

21

2

__

___

eqveqvgg

eqveqveqv

m

m +

+

+=

input offset ( )( ) ( )( )

( )( )

WLA

WLA

gIV

VggVV

VtT

m

DTg

gm

mgoff

ββ

β

σσ

σσδσ

δσδσ

==

⋅

+=

+=

,

22

22

24

2

1

421

2

pole estimations

and phase

margin

−

−°=

+==

)_

__

_180

_,_ 413

BA

B

dsdsB

A

mA

pfGBWfarctg

pfGBWfarctgPM

Cggpf

Cgpf

36

Miller OpAmp design



→ Circuit scheme and proposed partitioning n input Miller Op

Amp:

B

A

1

2

3

VSS

VDD

4

D


1. n current mirror 2. n differential pair 3. p current mirror 4. output stage

37

→ Circuit scheme and proposed partitioning p input Miller Op

Amp:

B

1

2

3

A

VSS

VDD

4

D


1. p current mirror 2. p differential pair 3. n current mirror 4. output stage


slew rate

cCI

SR 1=

gain bandwidth

frequency c

m

Cg

GBWfπ2

_ 1=

power dissip ))(( 21 IIIVVPowDissip ossdd ++−=

gain 76

6

41

1

dsds

m

dsds

m

ggg

ggg

A++

=

38

positive/negative

CMR (n input)

25_

22_3_3

thsatdsss

thsatdssatdsthdd

VVVCMR

VVVVV

++=−

+−+−=+CMR

(p input) 22_3_3

25_

thsatdssatdsthss

thsatdsdd

VVVVVCMR

VVV

−+++=−

−−=+CMR

output swing (n input) 7_6_

_

satdssatdsssdd

swingout

VVVV −−−

V =

(p input) 6_7_

_

satdssatdsssdd

swingout

VVVV −−−

V =

CMRR 45

412dsds

mm

gggg

CMRR⋅⋅

=

PSRR+/PSRR-

6

7

)(

)(

41

61

41

61

ds

ds

ggggg

PSRR

ggggg

PSRR

dsds

mm

dsds

mm

⋅+⋅

=

⋅+⋅

=

+

−

current

mismatch

(curr mirr) WL

A

WLA

Idg

IdId

vtT

Tm

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

voltage

mismatch

(diff pair) WL

A

WLA

gIdVg

vtT

mT

ββ

β

σσ

δσδσ

==

+=

,

,)( 22

equivalent noise ( )

( )2

41

1

27

2

6

726

24

23

2

1

422

21

2

__

_____

+

+

+

+

++=

dsds

m

m

m

m

m

ggg

eqvggeqv

eqveqvggeqveqveqv


( )( )

WLA

WLA

gIV

VggVV

VtT

m

DTg

gm

mgoff

ββ

β

σσ

σσδσ

δσδσ

==

⋅

+=

+=

,

22

22

24

2

1

421

2

pole estimations

and phase

margin

−

−°=

=+

=

+

+

+==

∑=

)_

__

_180

_,_,_,_

3

1

66

76

6

413

ii

C

m

CD

mD

dsds

mcB

dsdsB

A

mA

pfGBWfarctg

zfGBWfarctgPM

Cgzf

CCgpf

gggCC

ggpfCgpf

39

Folded Cascode OTA design



→ Circuit scheme and proposed partitioning for p input Folded

Cascode OTA:

VSS

VDD

1

4

2

5

3

6


1. p current mirror (bias 1) 2. n current mirror (bias 2) 3. folded cascode pair 4. cascode current mirror 5. bias 3 6. bias 4

40

→ Circuit scheme and proposed partitioning for n input Folded

Cascode OTA:

1

4

2

5

3

6

VSS

VDD


1. n current mirror (bias 1) 2. p current mirror (bias 2) 3. folded cascode pair 4. cascode current mirror 5. bias 3 6. bias 4


slew rate

LCIoSR =

gain bandwidth

frequency

1_2

m

L

gf GBW

Cπ=

41

power

dissipation

( ) ( )211 22 biasbiasbiasssdd IIIIVVPowDissip ++⋅+⋅⋅−=

gain 6

416

8

1081 )(,,m

dsdsdsoy

m

dsdsox

oyox

m

ggggg

gggg

gggA +⋅

=⋅

=+

=

positive/negative

CMR p input

11_4_

117_

thsatdssatdsss

thsatdsdd

VVVVCMR

VVV

−++=−

−−=+CMR

n input 117_

11_4_

thsatdsss

thsatdssatdsdd

VVVCMR

VVVV

++=−

+−−=+CMR

output swing p input ( )4_6_10_8_

_

satdssatdssatdssatdsssdd

swingout

VVVVVV +++−−

V =

n input ( )4_6_10_8_

_

satdssatdssatdssatdsssdd

swingout

VVVVVV +++−−

V =

equivalent noise

( ) ( )210

29

2

1

924

23

2

1

4

22

21

2

____

___

eqveqvggeqveqv

gg

eqveqveqv

m

m

m

m +

++

+

+=


( )( )

WL

A

WLA

gIdV

Vgg

VV

VtT

mTg

gm

mgoff

ββ

β

σσ

σσδσ

δσδσ

==

⋅

+=

+=

,

22

22

29

2

1

921

2

pole estimations

and phase

margin

−

−°=

++=

+=

)_

__

_180

_,_

21

146

621

pfGBWfarctg

pfGBWfarctgPM

CCCg

pfC

ggpf

ddgs

m

L

oyox

42

pad manual

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