ARM Architecture 1

ARM ARCHITECTURE

ARM Architecture 2

About ARM

• Acronym for Advanced RISC Machines• Founded in November 1990• Designs the ARM range of RISC processor

cores• Licenses ARM core design to semiconductor

partners– ARM does not fabricate silicon itself

• Develops technologies to assist with the design-ing of the ARM architecture– Software tools, boards, debug hardware, application software,

bus architectures, peripherals, etc

ARM Architecture 3

CISC Vs RISC

CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clockcomplex instructions

Single-clock,reduced instruction only

Memory-to-memory:"LOAD" and "STORE"incorporated in instructions

Register to register:"LOAD" and "STORE"are independent instructions

Small code sizes,high cycles per second

Low cycles per second,large code sizes

Transistors used for storingcomplex instructions

Spends more transistorson memory registers

ARM Architecture 4

About RISC• Reduced Instruction Set Computer• Common Characteristics

– One Instruction per cycle– Register to Register operations

• Large register file– Simple Addressing Modes– Simple Instruction Formats– Hardwired Programmed Unit– Less number of instructions

• More complex compiler design

ARM Architecture 5

Benefits of RISC approach

• Faster Execution – No microcode and simple instructions

• Effective pipelining – Lesser pipeline stalling

• Programs more responsive to interrupts

ARM Architecture 6

Features of ARM Architecture

• Typical RISC Features– Large uniform register file– Load/Store Architecture– Simple Addressing Modes– Uniform and fixed-length instruction fields

• Additional Features– Control over ALU and shifter– Auto-increment and auto-decrement addressing

modes– Load and Store multiple instructions– Conditional execution of all instructions

ARM Architecture 7

Evolution of ARM Architecture

1998 2000 2002 2004

vers

ion

ARMv5

ARMv6

1994 1996 2006

StrongARM®ARM926EJ-S™

XScaleTMARM102xE ARM1026EJ-S™

ARM9x6EARM92xT

ARM1136JF-S™

ARM7TDMI-S™

ARM720T™

Future

SC100™

SC200™

time

ARM Architecture 8

ARM Architecture Versions

Version 1– Basic data processing instructions– No Multiply instruction– Byte, word and multi word load/store instructions– Branch instructions– Software interrupt

Version 2–  Multiply and Accumulate Instructions– Coprocessor support– Two more banked regs in fast interrupt mode– SWP and SWPB load and store instructions– 26-bit address space

ARM Architecture 9

ARM Architecture Versions

Version 3–  32-bit address space– CPSR– SPSR– MRS and MSR instructions to access CPSR & SPSR– Two new processor modes

 Version 4

– Half word load/store instructions– Load and sign extend bytes and halfwords instructions– T – Thumb state transfer instruction– Privileged processor mode

ARM Architecture 10

ARM Architecture Versions

Version 5– ARM/Thumb interworking improved in T variants– Count leading zeros instr – efficient integer divide and

interrupt prioritization routines– Software breakpoint instr– More coprocessor instructions

ARM Architecture 11

ARM Architecture Variants

T Variants - Thumb Instruction set – Re-encoded subset of ARM instructions

– Advantages• Half the size of ARM instructions• Greater code density

– Disadvantages• More instructions for the same job• Some exception handling instructions are not included

– ARM code – best for maximizing performance of time critical code

ARM Architecture 12

ARM Architecture Variants

M Variants – Long Multiply Instructions– Four instructions – 32 x 32 -> 64 multiplications– 32 x 32 + 64 -> 64 multiply – accumulate

 

E Variants – Enhanced DSP Instructions– Includes DSP instructions– 16-bit MAC instruction – Add and sub with saturated signed arithmetic

ARM Architecture 13

Features

ArchitectureFeatures

Thumb DSP Jazelle Media

v4T v5TE v5TEJ v6

ARM Architecture 14

ARM Architecture Versions

Version ARM Instr version

Thumb Instr version

Long Mult instr

Enhanced DSP

V3 3 None No No

V3M 3 “ No “

V4 4 “ Yes “

V4TxM 4 1 No “

V4T 4 1 Yes “

V5 5 None Yes “

V5T 5 2 Yes “

V5TxM 5 2 No “

V5TE 5 2 Yes Yes

ARM Architecture 15

• ARM7TDMI

• T – Thumb Code

• D – JTAG Debug

• M – Fast Multiplier

• I – Embedded Cell Macrocell

• F – Vector Floating Point

ARM Architecture 16

Development of the ARM Architecture

16The ARM Architecture ED500

SA- 110

ARM7TDMI

4T

1

Halfword

and signed

halfword /

byte support

System

mode

Thumb

instruction

set

2

4

ARM9TDMI

SA- 1110

ARM720T ARM940T

Improved

ARM/Thumb

Interworking

CLZ

5TE

Saturated maths

DSP multiply -

accumulate

instructions

XScale

ARM1020E

ARM9E -S

ARM966E -S

3

Early ARM

architectures

ARM9EJ -S

5TEJ

ARM7EJ -S

ARM926EJ -S

Jazelle

Java bytecode

execution

6

ARM1136EJ -S

ARM1026EJ -S

SIMD Instructions

Multi - processing

V6 Memory

architecture (VMSA)

Unaligned data

support

ARM Architecture 17

ARM Powered Products

ARM Architecture 18

Intellectual Property

• ARM provides hard and soft views to licensees– RTL and synthesis flows– GDSII layout

• Licencees have the right to use hard or soft views of the IP– soft views include gate level netlists– hard views are DSMs

• OEMs must use hard views– to protect ARM IP

ARM Architecture

Data Sizes and Instruction Sets

• The ARM is a 32-bit architecture.

• When used in relation to the ARM:– Byte means 8 bits– Halfword means 16 bits (two bytes)– Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets– 32-bit ARM Instruction Set– 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java bytecode

ARM Architecture 20

Programmer’s Model

• Data Types

• Processor Modes

• Registers

• General Purpose Registers

• Program Status Registers

• Exceptions

• Memory

ARM Architecture 21

Data Types

• ARM processors support following data types– Byte 8 bits– Halfword 16 bits– Word 32 bits

• Halfwords must be aligned to two-byte boundaries

• Words must be aligned to four-byte boundaries

ARM Architecture 22

Processor Modes• ARM supports seven processor modes

– User: unprivileged mode under which most tasks run

– FIQ: entered when a high priority (fast) interrupt is raised

– IRQ: entered when a low priority (normal) interrupt is raised

– Supervisor: entered on reset and when a Software Interrupt instruction is executed

– Abort: used to handle memory access violations

– Undefined: used to handle undefined instructions

– System: privileged mode using the same registers as user mode

ARM Architecture 23

Registers

• ARM processor has total 37 registers– 31 general-purpose registers (32 bits wide)

• Unbanked registers, R0-R7• Banked register, R8-R14• Program Counter R15

– Only 16 are visible, others used for exception processing

– 6 status registers (32 bits wide)• Saved Program Status Register (SPCR)• Current Program Status Register (CPSR)

ARM Architecture 24

Register Organization

ARM Architecture 25

Special Registers

• Program Counter (R15)– Points to instruction which is two instructions after the instruction

being executed– ARM instr four bytes (32-bits) and are always word aligned– Two LS Bits are always zero

• Link Register (R14)– Performs two functions

• It holds the subroutine return address (address of the next instr after a Branch and Link instr)

• Each exception mode’s version of R14 is set to the exception return address

• Stack Pointer (R13)– It is by convention only

ARM Architecture 26

Program Status Register

Condition Code Flags

N Set to 1 when result is negative

Z Set to 1 when result is zero

C Set to 1 on carry or borrow generation and on shift operations

V Set to 1 if signed overflow occurs

2731

N Z C V Q

28 67

I F T mode

1623

815

5 4 024

U n d e f i n e d

ARM Architecture 27

Program Status Register

IDisables IRQ interrupts when set

FDisables FIQ interrupts when set

TT=0 indicates ARM execution

T=1 indicates Thumb execution

2731

N Z C V Q

28 67

I F T mode

1623

815

5 4 024

U n d e f i n e d

ARM Architecture 28

Program Status Register

2731

N Z C V Q

28 67

I F T mode

1623

815

5 4 024

U n d e f i n e d

M[4:0] Mode

0b10000 User

0b10001 FIQ

0b10010 IRQ

0b10011 Supervisor

0b10111 Abort

0b11011 Undefined

0b11111 System

Q Indicates occurrence of overflow and/or saturation

ARM Architecture 29

Exceptions• Generated to handle an event• ARM supports seven types of exceptions• When exception occurs execution is forced from fixed

memory address known as exception vector

Exception Type Mode Normal Address Priority

Reset Supervisor 0x00000000 1

Undefined Instruction Undefined 0x00000004 6

Software Interrupt Supervisor 0x00000008 6

Prefetch Abort Abort 0x0000000C 5

Data Abort Abort 0x00000010 2

IRQ (interrupt) IRQ 0x00000018 4

FIQ (fast interrupt) FIQ 0x0000001C 3

ARM Architecture 30

Memory

• Address Space– ARM uses a single, flat address space of 232 8-bit

bytes– Address calculations done using ordinary integer

instructions. Address wraps around if there is an overflow or underflow

• No support for unaligned memory (instruction and data) accesses

• Memory-mapped I/O

ARM Architecture 31

Endianness

• ARM has hardware input to configure the Endianness

Word Address at A

Halfword At Address A Halfword At Address A+2

Byte at address A

Byte at address A+1

Byte at address A+2

Byte at address A+3

01531

Word Address at A

Halfword At Address A+2 Halfword At Address A

Byte at address A+3

Byte at address A+2

Byte at address A+1

Byte at address A

1531 0

Big Endian Memory System

Little Endian Memory System

ARM Architecture 32

Conditional Execution

• Almost all ARM instructions can be conditionally executed

• If N, Z, C and V flags in CPSR satisfy a condition then the instruction is executed or it is treated as a NOP.

• Value of 0b1111 in condition field is used for instructions which can be unconditionally executed

• 4-bit condition code field

cond

0272831

ARM Architecture 33

Condition Codes

Not equal

Unsigned higher or same

Unsigned lower

Minus

Equal

Overflow

No overflow

Unsigned higher

Unsigned lower or same

Positive or Zero

Less than

Greater than

Less than or equal

Always

Greater or equal

EQ

NE

CS/HS

CC/LO

PL

VS

HI

LS

GE

LT

GT

LE

AL

MI

VC

Suffix Description

Z=0

C=1

C=0

Z=1

Flags tested

N=1

N=0

V=1

V=0

C=1 & Z=0

C=0 or Z=1

N=V

N!=V

Z=0 & N=V

Z=1 or N=!V

Example: ADDNE R0,R1,R2

ARM Architecture 34

ARM Instruction Set

• Branch Instructions

• Data-processing Instructions

• Status register transfer Instructions

• Load and Store Instructions

• Coprocessor Instructions

• Exception-generation Instructions

ARM Architecture 35

Exception-generating Instructions

• Two exception generation instructions present– The Software Interrupt (SWI) used to cause a

SWI exception. By this the User mode code can make calls to privileged OS code

– The Breakpoint (BKPT) used for software breakpoints. It causes a Pre-fetch Abort exception to occur

ARM Architecture 36

Enhanced DSP Extension

ARM Architecture 37

About Enhanced DSP Extension

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ARM Architecture 38

ARM Architecture 39

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