neural networks with cellular automata

Self-Adaptive Hardware Machine-Learning Systems Ludovic Krundel

Apr 8, 2023 1 /39

SEASONs:Spiking, Entropic, Asynchronous,Self-Organizing Neural Networks

On self-modifying ‘machine learning’ systems

Ph.D. project: Ludovic A. Krundel

Supervisors : Dr. David J. Mulvaney

Dr. Vassilios A. Chouliaras

Neural Networks with Neural Networks with Cellular AutomataCellular Automata


Apr 8, 2023 2 /39

Theme (talk emphasis)

● Innovative Emergence

● Connectionist approach

● Bottom-Up engineering (vs. conventional Top-Down engineering)

● Self-Modifying systems

● examples of physical implementation of NN on hardware device

● Aspects of the work:

– Scalability of NN

No learning algorithm-ready for more than 100s neurons

Interconnects issues

– Incremental Learning: trial-and-error processes ( no learning without errors)

– Asynchronous operation of the microelectronic system

introduction


Apr 8, 2023 3 /39

CPU: ubiquitous

●established industrialised solution as general purpose processor

●Typical example of full Top-Down design engineering

●sequencer

●low software level @ high hardware level

introduction


Apr 8, 2023 4 /39

CPU: insight

introduction

Sequencer(Automaton)Sequencer(Automaton)

Processing Unit Memory

Arithmetic and

Logic Unit

Instruction Register RI

Exchange Unit

Accus

Exchange Register RE

Address Register RAM

Ordinal Counter CO

Data

or

Instruction


Apr 8, 2023 5 /39

CPU: the good(?) old stuff?

● fatal processing error (e.g. wrong branching)

– not reliable for critical real-time system applications

embedded software for real-time applications: aircraft autopilot, space devices

microcontrollers for medical systems

● (exhibits) untrue time-parallelism: high surface/data-time-processing cost

– Instruction level parallelism

Pipelining

Superscalar design

– Thread level parallelism (MIMD)

Multiprocessing

Multithreading

– Data parallelism (SIMD) multimedia applications

Vector processor (vectors of data)

introduction

superscalar

pipeline

subscalar


Apr 8, 2023 6 /39

Manufacture of CPU

ASIC design flow

introduction


Apr 8, 2023 7 /39

Manufacture of CPU

Photolithography of ASIC circuit

CMOS Technology

introduction


Apr 8, 2023 8 /39

FPGA (Field-Programmable Gate Array)

●“Programmable Chip”

(Re-)Configurable Microelectronic Circuit

●True Time-Parallelism

●Massively parallel, highly distributed

processing units as in ASIC

●Examples of application: ASIC prototyping,

upgradeable hardware device, labs experiments

introduction


Apr 8, 2023 9 /39

FPGA: insight

introduction


Apr 8, 2023 10 /39

FPGA: manufacture

introduction


Apr 8, 2023 11 /39

SOC (System-On-a-Chip)

●True Time-Parallelism + CPU

●Lower surface/data-time-processing costs

introduction


Apr 8, 2023 12 /39

SOC: examples of application

introduction


Apr 8, 2023 13 /39

SOC: state-of-the-art

●Embedded FPGA (eFPGA): www.menta.fr

●Embedded CPU (eCPU): Mitrionics

– Massively parallel eCPU on FPGA

Supercomputing performance

introduction


Apr 8, 2023 14 /39

Conventional CAM (Cellular Automata Machine):“CA are a natural way of studying the evolution

of large physical systems and constitute a general paradigm for parallel computation” [Toffoli and Margolus, 1987]

● Clocked: whole 2D CA landscape updated at each clock tick (nth-order systems/rules)

● Two-state cells: e.g., alive or dead [Conway’s “Game of life”]

● Local (action-at-a-distance forbidden) and uniform (single rules’ recipe) system’s rules

part 1

Pure CA (Cellular Automata)


Apr 8, 2023 15 /39

Examples of self-organizing CAs

Innovative Emergence?

In big CA systems, complex global behaviours can emerge! [S. Wolfram, 2002]

Neuron-like CAs:

Dendritic CA

part 1


Apr 8, 2023 16 /39

NNs with CA

●CA can be configured to create functions

●Non-Linear Dynamics and Chaos

– Organized complexity innovative emergence

●Substrate for highly adaptive NNs

part 1


Apr 8, 2023 17 /39

EHW

●Intrinsic vs. Extrinsic EHW

●Evolving Neural Networks based on

Cellular Automata in hardware

●Genetic Algorithms

part 1

bit-streamJTAG

chromosome


Apr 8, 2023 18 /39

The CBM

●The CAM Brain Machine [H. de Garis, 1999]

●CAM = Cellular Automata Machine

●Growing CA-based NN modules for the

behaviour of a robot cat: Robokoneko

●Too many rules

Need ‘Rule Learning’

part 1


Apr 8, 2023 19 /39

CNN: Cellular Neural Networks

part 1

●CNN for Machine Vision [Pr. Leong Chua]

●POEtic embryonic tissue

– Phylogenesis: evolution

– Ontogenesis: development

– Epigenesis: learning


Apr 8, 2023 20 /39

CNN: POEtic embryonic tissue

part 1


Apr 8, 2023 21 /39

CA-based NN

●Evolved Neural Networks based on

Cellular Automata for sensory-motor

controller [Kim & Cho, 2005]

part 1

Khepera


Apr 8, 2023 22 /39

Cell Matrix

●The PIG Paradigm (Nicholas Macias, 1999)

●disappeared in 2005?

●FPGAs can actually also do it:

– ICAP: internal configuration access port

– Dynamic-reconfiguration efforts (IPFlex)

– Partial-reconfiguration efforts (JBits)

– Self-reconfiguration efforts (endo-reconfig)

part 1


Apr 8, 2023 23 /39

Some Interesting Features of NNs

●Rules Extraction (from non-linear

systems) – Inductive Inference

●Learning and automatic generation of

rules instead of evolutionary approaches

●Cognitive learning vs. blind learning

part 2


Apr 8, 2023 24 /39

Entropy Comparison Engine

●Improvability Evaluation: Self-Upgrades

●Similar concept to CPU sequencer:

systematic core engine

●Comparing NN system entropy with

environmental information

part 2


Apr 8, 2023 25 /39

Learning Algorithm

●Robot Controller: sensor-activator

– Sensor Signals Fusion

●Unsupervised Learning

●Spiking Neurons

●Self-Adaptive NN

– Entropy-based NN re-organization

– Automatic generation of CA rules

part 2


Apr 8, 2023 26 /39

Scalability

● Interconnects issues:

– NOC (Network-On-a-Chip)

– But FPGAs are now dominated by interconnects, just like NNs

●For more than 100s neurons:

– Modular architecture

multiplicity of learning algorithms?

– Hierarchical architecture

pseudo-fractal architecture?

part 2


Apr 8, 2023 27 /39

Ongoing Work: Design Approach

1. Top-down design and debug of one cell

– Using conventional EDA tools and design flows

– Implement at hand a minimal set of initial rules: basic rules

2. Bottom-up assembly as multiple instantiations of totipotent cells in a modular-hierarchical fashion

– Using HDL (Balsa, Verilog) parameterization facilities:

recursive instantiation

instantiation by name

3. Real-Time Simulations of the global hardware system

– Parametric simulations

– Comprehensive analyses

– Goto 1.: Eventual refinements of the cell design and initial rules

part 2


Apr 8, 2023 28 /39

Cell Architecture

part 2


Apr 8, 2023 29 /39

Possible Cell Structure

part 2


Apr 8, 2023 30 /39

Self-configured CA-based NN

Bottom-Up Engineering

part 2


Apr 8, 2023 31 /39

Selected FPGA design flow

part 3

Xilinx ISE


Apr 8, 2023 32 /39

Simulation with Balsa

●Spiking Entropic Asynchronous Self-

Organizing Neural networks: SEASONs

●Balsa development and simulation

environment

part 3


Apr 8, 2023 33 /39

Simulation with Balsa

●Balsa simulation environment

part 3


Apr 8, 2023 34 /39

FPGA Development Board

part 3


Apr 8, 2023 35 /39

Other Hardware Machine-Learning

Techniques for Self-Modifying Systems

1. Use SystemC or Handel-C and write synthesizable(?) self-modifying code

2. Perform software simulations

3. Target hardware FPGA

4. Perform hardware simulations and compare

discussion


Apr 8, 2023 36 /39

Neuropeptides

●nervous system + hormonal system

(immune system)

discussion


Apr 8, 2023 37 /39

Neuro-Modulation

●why hardware machine-learning

discussion


Apr 8, 2023 38 /39

Main Points

● SOC

● ASIC / FPGA

● CPU

● Digital Spiking NN based on asynchronous CA that dynamically reconfigure themselves to suit the changing task at hand

● Aware learning vs. blind adaptation

– Systematic learning mechanisms should not dominate a machine-learning technique

● Innovative Emergence of self-adaptation

conclusion

● CAM

● SEASON


Apr 8, 2023 39 /39

Acronyms

● FPGA: Field-Programmable Gate Array

● CPLD: Complex Programmable Logic Device

● ASIC: Application Specific Integrated Circuit

● SOC: System-On-a-Chip

● FSM: Finite State Machine

● CPU: Central Processing Unit

● DSP: Digital Signal Processor

● NN: Neural Network

● CA: Cellular Automata

● COTS: Commercially Off-The-Shelf

● EHW: Evolvable HardWare

● CAM: Cellular Automata Machine

● CBM: CAM Brain Machine

● JTAG: Joint Test Action Group

● ICAP: Internal Configuration Access Port

● RTL: Register Transfer Level

● EDIF: Electronic Design Interchange Format

● HDL: Hardware Description Language

● EDA: Electronic Design Automation

● VLSI: Very Large Scale Integration

● CMOS: Complementary Metal Oxide

Semiconductor

neural networks with cellular automata

Documents

manufacture introduction

blind learning

rule learning

cpu sequencer

big ca systems

processing costs introduction

cabased nn modules

dendritic ca