mos differential amplifier

Microelectronic circuits by Meiling CHEN

1

Lecture 13Lecture 13MOSFET Differential MOSFET Differential

Amplifiers Amplifiers


2

topicstopics• Ideal characteristics of differential

amplifier– Input differential resistance– Input common-mode resistance– Differential voltage gain– CMRR

• Non-ideal characteristics of differential amplifier– Input offset voltage – Input biasing and offset current

• Differential Amplifier with active load• Frequency response


3

Figure 7.1 The basic MOS differential-pair configuration.

MOS differential pair


4

CSV

Figure 7.2 The MOS differential pair with a common-mode input voltage vCM.

Common mode operation

DDDDDD

tGSnD

GSCMs

DD

RIVvv

VVLWkII

Vvv

III

QQ

21

2'

21

21

)(21

2

2

Q1 and Q2 in saturation mode

)(2

(min)

(max)

tGStCSssCM

DDDtCM

VVVVVv

RIVVv

BJT’s differential pair VCM no bound

Make sure current source is working

tsCMSDDDD

tGSDS

VvvvRIVVvv

)(

GSSSCSCM

tSSCSCM

tsCMtGS

vVVvVVVvVvvVv

)(


5

Exercise 7.1 kRmAIVVVmALWkVVV DtnSSDD 5.2,4.0,5.0,/4,5.1 2'

5.0816.015.22.05.1

816.0

)5.0(22.02

)(21

2

2'

tGSDS

DS

GS

GS

tGSnD

VVVVkmV

VV

VmI

VVLWkI

Saturation mode5.011

1

D

tCMDtGD

tSGSD

tGSDS

CM

VVVVVVV

VVVVVVVV

VV

Saturation mode VVCM 5.1(max)


6

Figure 7.3 (Continued)

48.0

VV

V

CM

CS

2.05.148.082.0

48.0

(min)

(min)


7

Figure 7.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid vG1 – vG2.

Large signal operation

22

'2

21

'1

)(21

)(21

tGSnD

tGSnD

VvLWki

VvLWki

2121 GGGSGSid vvvvv

2

'

'1

2

'

'1

2'2!

21

'21

21

2/122

12

21

2/122

12

212

21

LWk

vvILWkIi

LWk

vvILWkIi

vLWkIii

Iii

vLWkii

n

ididnD

n

ididnD

idnDD

DD

idnDD


8

Figure 7.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to I/2.


9

Figure 7.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV.

2

'

'1

21

2/122

12

LWk

vvILWkIi

n

ididnD

More k is bigger more linear range of vid


10

Figure 7.8 Small-signal analysis of the MOS differential amplifier: (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small-signal operation of the circuit.

7-2.1 Small signal operation (differential gain)

idCMG

idCMG

vvv

vvv

2121

2

1

21

21

2vvv

vvv

id

CM


11

)//(

)//(21),//(

21

)//(2

)//(2

12

22

11

22

11

oDmid

ood

oDmid

ooDm

id

o

oDid

mo

oDid

mo

rRgv

vvA

rRgvvrRg

vv

rRvgv

rRvgv

DR

gsv gsmvgor

1ov

2idv

Doo

id

RrRR

//21


12

ro effects

idoDmooo

idoDmo

idoDmo

vrRgvvvvrRgvvrRgv

)//()2/)(//()2/)(//(

12

2

1


13

2id

mVg

1oV

gsV

2idV

2idV

gsV

2

idm

Vg 1or DR DR 2or

2oV

Differential-mode equivalent circuit

)//(

)//()2/)(//()2/)(//(

12

12

2

1

oDmid

ood

idoDmooo

idoDmo

idoDmo

rRgv

vvA

vrRgvvvvrRgvvrRgv


14

Common-mode gain et CMRR

SS

D

icm

o

icm

omSS

SSm

D

icm

o

icm

o

RR

vv

vvgR

RgR

vv

vv

2/1

2/1

11

21

ssmcm

d

DmdssDcm

RgAACMRR

RgARRA

21,2/

21

21

(1) Half circuit of differential pair

(2) Full circuit

cm

d

Dmidoodicmoocm

AACMRR

RgvvvAvvvA /)(,0/)( 1212

mg1 DR

1ov

ssR2

di

icmR2

icmv

di


15

SSV

DDV DDV

fIRe

1DI

2DI

RVVVI

IIIvv

VvLWkI

GSSSDDD

refDDGSGS

tGSnD

1

2121

2' )(21

SSoo RrR

gsvgsmvg

or

1ov

R

gsvgsmvgor


16

Non zero common gain due to RD mismatch

D

Dssm

cm

d

Dmd

D

D

ss

D

ss

Dcm

icmss

Doo

icmss

DDo

icmss

Do

DD

RRRg

AACMRR

RgARR

RR

RRA

vRRvv

vR

RRv

vRRv

RRconsider

/2

22

2

2

2

12

2

1

21

mg1 DR

1ov

ssR2

di

icmR2

icmv

di

SS

D

icm

o

icm

omSS

SSm

D

icm

o

icm

o

RR

vv

vvgR

RgR

vv

vv

2/1

2/1

11

11


17

Figure 7.11 Analysis of the MOS differential amplifier to determine the common-mode gain resulting from a mismatch in the gm values of Q1 and Q2.

Non zero common gain due to gm mismatch

21

21

22

21

11

21

2121

2

1

2

121

21

)(

)(

)(

)()(

mmm

ssmm

icmmd

ssmm

icmmd

ss

icmddicms

ss

sddssdds

m

m

d

dgsgs

mm

gggletRgg

vgi

Rggvgi

Rviivv

RviiRiiv

gg

iivv

ggconsider

)(

)(2

2

tgsox

m

tgsox

d

VvLWCg

VvLWCi


18

m

mssm

cm

d

Dmd

m

m

ss

Dcm

ssm

icmDmDdDdoo

ssm

icmmd

ssm

icmmd

ggRg

AACMRR

RgAgg

RRA

RgvRgRiRivv

Rgvgi

Rgvgi

/2

2

2

2

2

1212

22

11


19

Figure 7.25 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the terminals with opposite polarity reduces VO to zero.

Input offset voltage

2121

21

21

.3

.2

.1

2

2

1

1

tt

LW

LW

DD

VVQQQQRR


20))(

2(

))(2

)(()()(

2

2

)2

(2

)2

(2

2

2

22

12

2

1

2

1

21

D

DOVos

D

DtGS

D

D

tGSLWC

tGSLWC

Dm

D

Dm

O

d

Oos

DDDO

DDDDD

DDDDD

DDD

DDD

DD

RRVV

RRVV

RR

VVVV

Rg

RI

RgV

AVV

RIVVV

RRIVV

RRIVV

RRR

RRR

RRconsider

ox

ox

))/()/()(

2(

)/(2)/(

2

)/()/(

22

)/()/(

22

)(21)(

)(21)(

2

1

2

1

21

LWLWVV

LWLWII

LWLWIII

LWLWIII

LW

LW

LW

LW

LW

LW

QQconsider

OVos

oVV


21tos

OV

t

tGS

t

tGSn

tGS

ttGSn

tGS

ttGSn

tGS

ttGSn

ttGSn

ttt

ttt

tt

VVV

VIVV

VII

IVVLWk

VVVVV

LWkI

VVVVV

LWkI

VVVVV

LWkVVV

LWkI

VVV

VVV

VVconsider

22

22

2)(

21

)1()(21

)1()(21

])(2

1[)(21)

2(

21

2

2

2'

2'12

2'1

22'2'1

2

1

21

222 )())/()/(

2()

2( t

OV

D

DOVos V

LWLWV

RRVV


22

Differential amplifier with active load

1. Differential gain 2. Common-mode gain et CMRR

Active load


23


24

Differential-mode equivalent circuit with active load

2idV

2id

mV

g 1orm

o gr 1//3

4gsmVg 4or 2or

oV

)2

( idm

Vg

2idV

2idV

2id

mV

g 1orm

o gr 1//3

4gsmVg 4or 2or

oV

)2

( idm

Vg

2idV

1Q 4Q 2Q

3Q

42 // ooo rrR

om

d

ooo

oomid

oovv

m

id

od

v

m

vm

moo

vmgs

oogsv

mo

rgA

rrrwhen

rrgv

rrgvvA

gg

grrgv

rrvgv

idid

ididid

id

2

)//()//)((

1)1////(

)//)((

42

424222

223124

4242

)//( oDmd rRgA Passive load

active load

SSoo RrR Passive load

active load


25

Common-mode equivalent circuit with active load

iCMV iCMV

di

di

mg1

1orm

o gr 1//3

4gsVoV

4gsmVg

ssR2 1i

2i

4or 2or

di

mg1

ssR22i

)( oss rR

iCMV iCMViCMV iCMV

di

di

mg1

1orm

o gr 1//3

4gsVoV

4gsmVg

ssR2 1i

2i

4or 2or

di

mg1

ssR22i

)( oss rR

1i

SSicm

SSicm

mogs

gsmoo

RivRiv

griv

ivgrv

22

)1//(

)(

2

1

414

244

moSS

o

icm

ocm

SS

icm

mo

SS

icmmoo

mo

SS

icmgs

SS

icmgsmoo

grRr

vvA

Rv

gr

Rvgrv

gr

Rvv

Rvvgrv

3

4

34

34

44

11

2

]2

)1//(2

[

)1//(2

)2

(


26

Figure 7.29 Determining the short-circuit transconductance Gm ; io/vid of the active-loaded MOS differential pair.

1. Find the transconductance Gm


27

mm

idmo

mmmmm

idm

id

m

mmo

idmgmo

id

m

mg

moo

oom

idmg

gGvgi

ggggg

vgvgggi

vgvgi

vggv

grr

rrg

vgv

2143

23

41

234

3

13

331

133

13

,

)2

()2

)((

)2

(

)2

(

)/1(,

)////1)(2

(


28

2. Find the output resistance Ro

3. Find the differential gain

42

4244

22

22

12222

2

//

22

21

)/1)(1(/

oox

xo

o

x

o

x

o

x

o

xx

oo

om

momoo

ox

rrivR

rv

Rv

rvi

rviii

rRrg

grgrRRvi

om

d

ooo

oomomid

od

rgA

rrrwhen

rrgRGvvA

2

)//(

42

42


29

Figure 7.31 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.

Common-mode gain et CMRR

30ssmom

mmooo

ssmoomcm

d

ssmcm

ooom

om

o

ssicm

ocm

oom

moo

om

mgm

om

g

ssomssooo

ss

icm

RgrgCMRRggrrrlet

RgrrgAACMRR

RgA

rrrgrg

rRv

vA

rirg

igriiv

rg

igvgi

rg

iv

RrgRrRRRvii

342

342

3

4333

33

4

4233

14424

33

14344

33

13

21

21

,

]2)][//([

21

,112

1

])//1([)(

)//1(

)//1(

222

mos differential amplifier

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