Modeling Registers With Uvm Tom Fitzpatrick

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Design and Verification in the SoC Era: Modeling Registers with UVM Tom Fitzpatrick Verification Evangelist DVT October 2011 The Idea Behind The Methodology  OVM & UVM underpin best practices — It's all about people... — Team Development  Peopleware is most important — — — — Develop Skill Set Common language Strategy and cohesion Clarity and transparency  A Guiding Methodology — Provides Freedom From Choice — Avoids Chaos and Repetition — Ease of Use APIs — Not just for Super-heroes! © 2011 Mentor Graphics Corp. Company Confidential 2 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Foundations Objective      Justification      Separation of stimulus generation from delivery Raise the abstraction level of stimulus and checking Test bench configuration Interoperability Reuse — Standard class library & API Several people can develop stimulus Increase productivity Avoid expensive recompilation Important for intra and inter company development Key to productivity — VIP — Testbench components — Stimulus © 2011 Mentor Graphics Corp. Company Confidential 3 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Testbench - Architectural Design For Each Interface: • How does the interface work? • What information is transferred? • Transaction variants? • Uni/bidirectional? Pipelined? APB DUT SPI I/F IRQ For the Design: • What does it do? • What are the use cases? • Which test cases are required? • What type of stimulus scenarios are required? • What represents correct behavior? • What kind of functional coverage do I need? 4 TF - UVM Recipe of the Month 10/11 www.mentor.com © 2011 Mentor Graphics Corp. Company Confidential UVC Structural Building Block Analysis port: Send transactions for checking - Contains virtual interface handle - Pass information on how agent should behave Detects transactions on the interface UVC(agent) Configuration Object Sequencer Monitor One per interface Sends stimulus to Driver seq_item Driver DUT Stimulus Converts seq_item to pin wiggles © 2011 Mentor Graphics Corp. Company Confidential 5 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Registers are Layered  UVM Register Layer provides protocol-independent register-based layering UVM Reg Layer Predict RegSeq UVC(agent) Configuration Object Sequencer Monitor Driver DUT Device specific cfg.write(0xDE); 7 TF - UVM Recipe of the Month 10/11 Bus specific wr(0xAF, 0xDE); © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com Registers, Blocks & Maps Registers contain bits & fields Register Map contains Registers Register Block contains Maps One Map per physical interface Blocks are hierarchical 31:14 Reserved 13 ASS 12 IE 11 10 9 8 7 R 6:0 Char_Len R R/W R/W R/W R/W R/W R/W LSB TxNeg RxNeg GoBsy Rsrv R/W © 2011 Mentor Graphics Corp. Company Confidential 8 TF - UVM Recipe of the Month 10/11 www.mentor.com The Register Map – uvm_reg_map  Contains offsets for: — Registers and Memories — (Hierachical blocks) — (Sub-maps) SQR  Also provides means to access registers — Handle for target sequencer — Handle for register layer adapter  A block can have > 1 map SQR — AXI Master1, AXI Master2 (Fabric) UVC(agent) Monitor Sequencer Driver DUT © 2011 Mentor Graphics Corp. Company Confidential 9 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Register Use Models  Stimulus Generation — Stimulus reuse — Abstraction of stimulus: – i.e. Set this bit in this register rather than write x to address y – If the bus agent changes, the stimulus still works – Front door is via an agent – Back door is directly to the hardware via the simulator database — Front and Back Door access:  Configuration — Register model reflects hardware programmable registers — Set up desired configuration in register model then dump to DUT – Randomization with configuration constraints  Analysis ‘Mirror’ — Current state of the register model matches the DUT hardware — Useful for scoreboards and functional coverage monitors © 2011 Mentor Graphics Corp. Company Confidential 10 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Model Code Example (Only 1 Reg) Register class with one field Block containing Register class spi_reg_block extends uvm_reg_block; `uvm_object_utils(spi_reg_block) rand divider divider_reg; uvm_reg_map APB_map; // Block map class divider extends uvm_reg; `uvm_object_utils(divider) uvm_reg_field reserved; rand uvm_reg_field ratio; function new(string name = "divider"); super.new(name, 32, UVM_NO_COVERAGE); endfunction virtual function void build(); ratio = uvm_reg_field::type_id::create("ratio"); ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, 1, 1); endfunction endclass #bits Coverage function new(string name = "spi_reg_block"); super.new(name, build_coverage(UVM_CVR_ADDR_MAP)); endfunction virtual function void build(); divider_reg = divider::type_id::create("divider"); divider_reg.build(); divider_reg.configure(this, null, ""); divider_reg.add_hdl_path_slice("divider", 0, 16); APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN); APB_map.add_reg(divider_reg, 32'h00000014, "RW"); add_hdl_path("DUT", "RTL"); lock_model(); endfunction: build endclass: spi_reg_block 11 TF - UVM Recipe of the Month 10/11 #bits lsb mode reset Build is not the component build A map is a component of a block © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com Register Model Code Example (Only 1 Reg) Register class with one field Block containing Register class spi_reg_block extends uvm_reg_block; `uvm_object_utils(spi_reg_block) class divider extends uvm_reg; `uvm_object_utils(divider) uvm_reg_field reserved; rand uvm_reg_field ratio; function new(string name = "divider"); super.new(name, 32, UVM_NO_COVERAGE); endfunction UVM_NO_COVERAGE UVM_CVR_REG_BITS virtual function void build(); ratio = uvm_reg_field::type_id::create("ratio"); rand divider divider_reg; UVM_CVR_ADDR_MAP ratio.configure(this, 16, 0, "RW", 0, 16'hffff, 1, endfunction uvm_reg_map APB_map; // Block map UVM_CVR_FIELD_VALS endclass function new(string name = "spi_reg_block"); UVM_CVR_ALL super.new(name, build_coverage(UVM_CVR_ADDR_MAP)); endfunction virtual function void build(); divider_reg = divider::type_id::create("divider"); divider_reg.build(); divider_reg.configure(this, null, ""); divider_reg.add_hdl_path_slice("divider", 0, 16); APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN); APB_map.add_reg(divider_reg, 32'h00000014, "RW"); 1, 1); Build is not the component build A map is a component of a block add_hdl_path("DUT", "RTL"); lock_model(); endfunction: build endclass: spi_reg_block 12 TF - UVM Recipe of the Month 10/11 © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com Register Assistant* Overview  Register/Memory Definition & Management for the Entire Design Process Central, Scalable & Extensible Register/Memory Datamodel — — — — Enables easy specification of registers Manages register changes Eliminates hand coding & resultant mistakes Completely customizable  Automatically Generates Register Outputs — — — — OVM/UVM Register Package Synthesizable RTL Documentation Extensive roadmap * Included with Certe Testbench Studio 13 Supports the entire design team © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com Common Register Path    Generate the UVM/OVM register model Generate the DUT registers Use Certe templates to generate UVM sequences, adaptor class & the bus agent Template Generated SQR Register Assistant -Generation UVC(agent) Template-Generated RegSeq Sequencer Monitor Driver DUT © 2011 Mentor Graphics Corp. Company Confidential 14 www.mentor.com UVM Register Package Generation Optional Blocks & Block Maps Customer Example Register Definitions Early in project: 335 Registers  11,500 lines Final project: 1,000 Registers  35,000+ lines of Register Package code © 2011 Mentor Graphics Corp. Company Confidential 15 www.mentor.com Register Documentation Generation  Communicate the register layer to all team members Final documents auto-generated Customizable content & style   © 2011 Mentor Graphics Corp. Company Confidential 16 www.mentor.com The Architecture – Open & Extensible Spreadsheet (CSV) IP-XACT API calls Control File Reg. Definitions Documentation Blocks A Readers P I Datamodel A P I Writers RTL Block Map OVM/UVM Pkg. Checks © 2011 Mentor Graphics Corp. Company Confidential 17 www.mentor.com UVM Coverage   You can specify the coverage model you wish to generate for instances in a block Simply add a column to your spreadsheet © 2011 Mentor Graphics Corp. Company Confidential 18 www.mentor.com UVM Register Class Access API Direct access methods  reg.read() and reg.write()  — Access the hardware register and update the register database — Can specify front or back door access – Front door access takes time and may create side effects – Uses bus agent and consumes clock cycles – Uses simulation database and access API (VPI) – Back door access is instant and does not cause side effects — Not used for individual fields  reg.peek() and reg.poke() — For back door accesses, register model updated with result — Can be used for individual fields — Desired value  The register model has two register variables: — Mirrored value – For when a field has been updated, but not the hardware – Containing the latest known value © 2011 Mentor Graphics Corp. Company Confidential 19 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Access Method Fields Type uvm_status_e uvm_reg_data_t uvm_path_e uvm_reg_map uvm_sequence_base int uvm_object string int Name status value path map parent prior extension fname lineno Purpose Indicates Access completed OK Data value transfered Front or back door access Map to use for access Parent sequence Sequence priority on sequencer Transfer extension object Filename (For reporting) Line number (For reporting)   Good news – most of these fields have defaults! A typical register access only needs a few of these: spi_rm.ctrl.write(status, wdata, .parent(this)); © 2011 Mentor Graphics Corp. Company Confidential 20 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Stimulus Examples – Base Class class spi_bus_base_seq extends uvm_sequence #(uvm_sequence_item); `uvm_object_utils(spi_bus_base_seq) // SPI Register model: spi_reg_block spi_rm; // SPI env config object (contains register model spi_env_config m_cfg; Sequence base class contains variables common to all register sequences: handle) • data, status • register model handle // Properties used by the various register access methods: rand uvm_reg_data_t data; // For passing data uvm_status_e status; // Returning access status // Common functionality: // Getting a handle to the register model task body; m_cfg = spi_env_config::get_config(m_sequencer); spi_rm = m_cfg.spi_rm; endtask: body endclass: spi_bus_base_seq © 2011 Mentor Graphics Corp. Company Confidential 21 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Stimulus Example: Set Divider Value class div_load_seq extends spi_bus_base_seq; `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2, 16'h4, 16'h8, 16'h10, 16'h20, 16'h40, 16'h80};} task body; super.body; // Randomize the local data value assert(this.randomize()); // Write to the divider register spi_rm.divider_reg.write(status, data, .parent(this)); endtask: body endclass: div_load_seq Extends base sequence Randomizes data value with specific constraint Writes data to divider register © 2011 Mentor Graphics Corp. Company Confidential 22 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Sequence Example – TX Data Load class data_load_seq extends spi_bus_base_seq; `uvm_object_utils(data_load_seq) Extends the base class uvm_reg data_regs[]; // Array of registers task body; Gets an array of register handles super.body; // Set up the data register handle array data_regs = '{spi_rm.rxtx0_reg, spi_rm.rxtx1_reg, spi_rm.rxtx2_reg, spi_rm.rxtx3_reg}; Randomizes the array index order // Randomize order data_regs.shuffle(); Foreach reg in the array: foreach(data_regs[i]) begin Randomize the content // Randomize register content and then update Updates the register assert(data_regs[i].randomize()); data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this)); end endtask: body endclass: data_load_seq © 2011 Mentor Graphics Corp. Company Confidential 23 TF - UVM Recipe of the Month 10/11 www.mentor.com How Do Front Door Register Accesses Work?  When an explicit register access method is called – Address, Data, Read or Write — The register access method forms a generic register command: — This is then sent through a layering to the target bus agent  The layering has to convert: — Generic register requests to target bus sequence items  This conversion takes place in the adapter B SQR — Extended from uvm_reg_adapter UVC(agent) Monitor RegSeq Reg Sequencer Driver DUT © 2011 Mentor Graphics Corp. Company Confidential 24 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Adapter Class Example class reg2ahb_adapter extends uvm_reg_adapter; `uvm_object_utils(reg2ahb_adapter) function new(string name = "reg2ahb_adapter"); super.new(name); endfunction reg2bus() converts register item to bus item – note single access only virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb"); ahb.HWRITE = (rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE; ahb.HADDR = rw.addr; ahb.DATA = rw.data; return ahb; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); ahb_seq_item ahb; if (!$cast(ahb, bus_item)) begin `uvm_fatal("NOT_AHB_TYPE","Provided bus_item is not of the correct type") return; end rw.kind = (ahb.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE; rw.addr = ahb.HADDR; rw.data = ahb.DATA; rw.status = UVM_IS_OK; endfunction endclass: reg2ahb_adapter bus2reg() converts bus item to reg item © 2011 Mentor Graphics Corp. Company Confidential 25 TF - UVM Recipe of the Month 10/11 www.mentor.com Keeping The Register Model Up To Date  Need to update register model with results of hardware access — This is referred to as prediction — Auto prediction  Two ways: – Register model updates based on value written or read back – OK in simple situations where only one way to access the DUT registers – Requires no additional components – A predictor component: — Explicit prediction (UVM Default) – Observes bus analysis transactions – Updates the register model on what it observes – Works for normal to complex scenarios – Supports hierarchical reuse 26 TF - UVM Recipe of the Month 10/11 © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com Auto Prediction  For ‘simple’ scenarios: — Only sequences accessing the bus agent are register sequences — Register can only be accessed via one bus — Based on value read or written to the register   The register model updates itself Has to be enabled – reg_model.set_auto_predict(1); Breq SQR UVC(agent) Monitor RegSeq Sequencer Reg www.mentor.com Driver reg © 2011 Mentor Graphics Corp. Company Confidential 27 TF - UVM Recipe of the Month 10/11 Explicit Prediction - Recommended   Supports arbitrary complexity Predictor component updates register model — Based on any detected bus transaction — Regardless of origin  Supports vertical reuse Reg Breq SQR UVC(agent) Predictor RegSeq Monitor Reg Sequencer Breq Driver Breq reg © 2011 Mentor Graphics Corp. Company Confidential 28 TF - UVM Recipe of the Month 10/11 www.mentor.com Explicit Prediction - Recommended Predictor RegSeq Sequencer Driver UVC(agent) Monitor SQR SQR reg UVC(agent) Predictor RegSeq Sequencer Driver Monitor reg © 2011 Mentor Graphics Corp. Company Confidential 30 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Model Testbench Integration class spi_env extends uvm_env; apb_agent m_apb_agent; spi_env_config m_cfg; // Register layering adapter: Predictor is a parameterised reg2apb_adapter reg2apb; uvm base class // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; Register adapter specific to bus agent function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; Predictor is integrated during // Set the predictor adapter: the connect phase apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect © 2011 Mentor Graphics Corp. Company Confidential 31 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Read And The Register Mirror Before mirrored value After mirrored value  Read cycle results in the register model being updated desired value desired value hardware value hardware value Mirrored and desired value updated at the end of the bus read cycle Mirrored and desired value out of step with hardware value © 2011 Mentor Graphics Corp. Company Confidential 32 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Write And The Register Mirror Before mirrored value During mirrored value After mirrored value desired value desired value desired value hardware value Initial state, hardware and reg model in sync hardware value Hardware value changed by bus write cycle hardware value Mirrored and desired value updated at the end of the write cycle © 2011 Mentor Graphics Corp. Company Confidential 33 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Model Internal Access And Update()    Indirect methods: — Only access the register database — Can be used on registers and fields — set/get the register or field reset value reg.get(), reg.set(), reg.reset(), reg.get_reset()  reg.update() — Cause the hardware to be updated if register model content has changed via reg.set(), reg.reset() or reg.randomize() — Can specify front or back door access  34 These methods set the desired value © 2011 Mentor Graphics Corp. Company Confidential TF - UVM Recipe of the Month 10/11 www.mentor.com Register Write And The Register Mirror Before mirrored value set() mirrored value update() mirrored value After mirrored value desired value desired value desired value desired value hardware value Initial state, hardware and reg model in sync hardware value Desired value changed by indirect access method (e.g. set()) hardware value Update() transfers desired value to HW via a write bus cycle hardware value Mirrored value updated at the end of the write cycle © 2011 Mentor Graphics Corp. Company Confidential 35 TF - UVM Recipe of the Month 10/11 www.mentor.com Built-In Sequences  Sequences are automatic — Low overhead to use — Useful for initial sanity checks on bus connectivity  Access modes are respected — e.g. Read only registers are not bit bashed — Read only memories are not tested  Memories, Registers or Fields can be opted out of a test — e.g. Clock enable bit — Mechanism is to use the uvm_resource_db to set an attribute for the register © 2011 Mentor Graphics Corp. Company Confidential 36 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Built-In Sequences Sequence Name uvm_reg_hw_reset_seq uvm_reg_single_bit_bash_seq uvm_reg_bit_bash_seq uvm_reg_single_access_seq uvm_reg_access_seq uvm_reg_shared_access_seq Description Checks register reset values Checks R/W path to each register bit in a register Runs single_bit_bash_seq on a register block Checks that both front and back door accesses work correctly for a register Runs single_access_seq on a register block If a register is in multiple maps, checks that accesses can be made from each map © 2011 Mentor Graphics Corp. Company Confidential 37 TF - UVM Recipe of the Month 10/11 www.mentor.com Stimulus Reuse (Bridge Example)    SPI master is integrated inside an AHB peripheral block Host bus sequences can reused as is Testbench structure changes AHB to APB Bridge SPI Master SPI Host Bus Sequence AHB APB Bus Agent APB SPI Another DUT APB ANI Another DUT APB ANI APB ANI © 2011 Mentor Graphics Corp. Company Confidential Another DUT 38 TF - UVM Recipe of the Month 10/11 www.mentor.com Stimulus Reuse Code Example class spi_env extends uvm_env; apb_agent m_apb_agent; spi_env_config m_cfg; // Register layering adapter: reg2apb_adapter reg2apb; // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; // Set the predictor adapter: apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect © 2011 Mentor Graphics Corp. Company Confidential 39 TF - UVM Recipe of the Month 10/11 www.mentor.com Stimulus Reuse Code Example class spi_env extends uvm_env; io_ss_env extends uvm_env; apb_agent m_apb_agent; ahb_agent m_ahb_agent; spi_env_config m_cfg; io_ss_env_config m_cfg; // Register layering adapter: reg2apb_adapter reg2apb; reg2ahb_adapter reg2ahb; // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor; #(ahb_seq_item) ahb2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin if(m_cfg.m_ahb_agent_cfg.active reg2apb = reg2apb_adapter::type_id::create("reg2apb"); reg2ahb reg2ahb_adapter::type_id::create("reg2ahb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); m_cfg.io_ss_rm.TOP_map.set_sequencer(m_ahb_agent.m_sequencer, reg2ahb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; ahb2reg_predictor.map m_cfg.io_ss_rm.TOP_map; // Set the predictor adapter: apb2reg_predictor.adapter = reg2apb; ahb2reg_predictor.adapter reg2ahb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); m_ahb_agent.ap.connect(ahb2reg_predictor.bus_in); end endfunction: connect © 2011 Mentor Graphics Corp. Company Confidential 40 TF - UVM Recipe of the Month 10/11 www.mentor.com Stimulus Reuse Layer II – Across Fabric SPI Host Bus Sequence AXI Bus Fabric AXI Bus Agent AXI 2 AHB Bridge AHB to APB Bridge SPI Master APB SPI © 2011 Mentor Graphics Corp. Company Confidential 41 TF - UVM Recipe of the Month 10/11 www.mentor.com Register Stimulus Reuse: Set Divider Value class div_load_seq extends spi_bus_base_seq; `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2, 16'h4, 16'h8, 16'h10, 16'h20, 16'h40, 16'h80};} task body; Extends base sequence which gets register super.body; model handle from config object. // Randomize the local data value Sequence works as before but via the AHB agent assert(this.randomize()); // Write to the divider register spi_rm.divider_reg.write(status, data, .parent(this)); endtask: body endclass: div_load_seq © 2011 Mentor Graphics Corp. Company Confidential 42 TF - UVM Recipe of the Month 10/11 www.mentor.com Relevant Parts Of Top Level Environment class sys_env extends uvm_env; axi_agent m_axi_agent; sys_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2axi; // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"); // Register sequencer layering part: m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi); // Set the predictor map: axi2reg_predictor.map = m_cfg.sys_rm.TOP_map; // Set the predictor adapter: axi2reg_predictor.adapter = reg2axi; // Connect the predictor to the bus agent monitor analysis port m_axi_agent.ap.connect(axi2reg_predictor.bus_in); end endfunction: connect © 2011 Mentor Graphics Corp. Company Confidential 43 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Register Package Works with OVM `include “ovm_macros.svh” `include “uvm_reg_macros.svh” import ovm_pkg::*; import uvm_reg_pkg::*; class sys_env extends ovm_env; axi_agent m_axi_agent; sys_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2axi; // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor; function void spi_env::connect(); if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"); // Register sequencer layering part: m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi); // Set the predictor map: axi2reg_predictor.map = m_cfg.sys_rm.TOP_map; // Set the predictor adapter: axi2reg_predictor.adapter = reg2axi; // Connect the predictor to the bus agent monitor analysis port m_axi_agent.ap.connect(axi2reg_predictor.bus_in); end endfunction: connect © 2011 Mentor Graphics Corp. Company Confidential 44 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Register Summary    Register model follows hardware structure — Fields, Registers, Blocks, Maps — Certe Register Assistant Register model generator available: Register access API: — Internal access – get(), set() etc — External access – Front and Backdoor – Sets up desired value  Access layered via model — Generic sequences adapted to target bus sequences — Sequence reuse straight-forward    45 Use explicit prediction Built in sequences available for initial testing Works with OVM © 2011 Mentor Graphics Corp. Company Confidential TF - UVM Recipe of the Month 10/11 www.mentor.com Mentor + UVM = Success  Mentor is uniquely able to meet your verification needs — Tools — Technology — Resources © 2011 Mentor Graphics Corp. Company Confidential 46 TF - UVM Recipe of the Month 10/11 www.mentor.com © 2011 Mentor Graphics Corp. Company Confidential www.mentor.com

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