mindtunes jonathan chen, po-han huang, michael kempf, yen-liang tung, christos vezyrtzis fpga...

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mindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

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Page 1: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

mindTunes

Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis

FPGA mp3/wav memo recording

Page 2: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Object – Environment of System

t

=

Music/voice signals are band-limited signals

Memo storing dictates capacity instead of quality as primary concern

We need:Low complexity systemWidely accepted storage format and medium

Therefore:Minimize sampling rate (8kHz) and bit analysis (16 bit)Choose wav/mp3 and USB Flash Drive

Page 3: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Hardware Setup (i-side only)

Programmable A/D converter

1-bit output stream : Use S/P8kHz sampling rate, dual channelNo pre-filteringSame setting for D/AWhy only input? Symmetry

Output of hardware: at request of the processor / encoderVery quick sample demand, very slow samplingSolution: HARDWARE MUST SLOW DOWN THE SOFTWAREHow long? As much as it takes !!

Page 4: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

S/P & Clock Setup (FYI)Clocks are always created as fractions of the Audio Clock: 18.432MHz18.432MHz / 2304 = 8kHz (Sampling)

A/D Output must be converted to 16-bit word before the next sample18.432MHz / 144 = 128kHz (S/P)Within 1-sample time interval we create one 16-bit word (sample)

Page 5: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

FIFO Processor much faster than A/DWithin 1 sample time : 6250 read commands but only 1 new sample !!

Pause processor until there is word to read from the FIFOIn the process of reading:

If there is a read command pause the processorPut the word on the busThen read it!!3 cycle delay (w.r.t. processor clock)

Page 6: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

FIFO(2) (FYI)

Questions: How big? mp3 frame Synchronous? NO

Moore state machine Input & Output FIFO

equally spaced ? NO Delay between

successful reading and output word: 3 cycles

Page 7: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

FIFO(3)

Operation: Altera MegaFunction One clock cycle after

rdreq, data is presented at output q; usedw decrements

One clock cycle after wrreq, data is latched in; usedw increments

Underflow circuitry prevents data being read from an empty FIFO; FIFO blocks

Overflow circuitry prevents data being wrteen to a full FIFO; FIFO blocks

Page 8: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Timing Diagram (Input) (FYI)

(2) New sample arrives at the FIFO FIFO is ready for output

(1) Read & Write are de-assetred WAITREQUEST

(3) FIFO is not empty prepares for output

(4) FIFO is not empty & Read command data is on the bus

(5) WAITREQUEST 0 and data is read

Page 9: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Operating System uClinux – microcontroller

implementation of Linux.

Enables the incorporation of device drivers – without having to write them!

Page 10: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Storage/File System

Utilized USB mass storage device

Running as a host device on DE2

Once mounted, provides convenient storage of recordings in a “directory”

Page 11: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

I/O programming in user space

Not kernel space - no interrupts

Can’t use Hardware Abstraction Layer (e.g. IORD16_Direct)

To access peripherals (switches, audio) use memory pointer access

Page 12: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

WAV Format Recording

The ‘RIFF’ chunk descriptor• WAVE format

The ‘fmt’ sub-chunk• format of the sound information

The ‘DATA’ sub-chunk• size of the sound information and raw sound dat

Page 13: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

MP3 Format (MPEG 1 Layer3)

MP3 is composed of succession of frames i.e. frame1 - frame2 - frame3 -……..

Each frame is totally independent, can cut any part of MPEG files and play correctly.

Page 14: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

MP3 Frame Header

Page 15: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Choosing MP3 version

Bits MPEG1 MPEG2 MPEG2.5 (ext 2)

00 44.1kHz 22kHz 11kHz

01 48kHz 24kHz 12kHz

10 32kHz 16kHz 8kHz

11 reserved reserved reserved

•Since we want to user low sampling Rate - 8kz, we choose MPEG 2.5Layer3 •Note: The only difference MPEG 1,2,2.5 is MPEF 2 and 2.5 support more bit rate, and sampling rate. Everything else are the same.

Page 16: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

MP3 Header in our caseLength (bits) Description In our case Bits

11 Frame Sync Always 1 11111111111

2 MPEG Version

2.5 00

2 Layer Layer3 01

1 CRC no 0

4 Bit rate 128k bits/sec 1200

2 Sampling Rate

8khz 10

1 Padding yes 1

1 Private bit Only informative 1

2 Channel Mono 11

2 Mode ext Only used in Stereo

11

1 Copyright no 0

1 Original no 0

2 Emphasis no 0

Page 17: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Encoding Implementation

The reason to have .wav file in the transition is that the mp3 encoding algorithm is to slow to make it realtime

ADC

.Wav file

At USB Encoding

.mp3 file at USB

Page 18: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Encoding Implementation

Take a code from shine fixed point version 1.09 which was originally used on ARM machine

Strip out the part about ARM and change the part of assembly code to C in order to run under nios-uclinux

Made it a function for main code to call

Page 19: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Decoding: Uclinux – MP3PLAY

Support MPEG-1, 2, 2.5 Layer 1 2 3 Support both fixed-point and floating-

point Can use Assembly to optimize the

computing Implementation: Set to use fixed-point function in mp3dec library and do not

use Assembly optimization Write out PCM data to FIFO input Add header on PCM data to write to WAV

Page 20: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Decoding Implementation

DAC.Wav file

At USB

Decoding

.mp3 file at USB

Page 21: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Problems – Comments Software(Decoding):

Now, we can hear artist’s vocal in the background with lots of white noise

Before waitrequest function enable, it sounded like machine gun

With waitrequest enabled, artist’s voice sounds retarded After we increased the FIFO size, the tempo is close to

original clip Write to wav file, but cannot hear sound Write raw PCM data, listening on Matlab does not work

Software(Encoding):

Too slow to be real-time

Inline assembly optimizationHardware mul() implementation

Page 22: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Problems – Comments Hardware:

FIFO timing Need to synchronize bus clock (100 MHz) and S. CLK (8 kHz) Encoder/Decoder might be consuming/feeding data faster than

ADC/DAC can process! Need to increase size of FIFO

Asynchronous “wait” waitrequest is combinational logic; state machine is sequential

Choice of Different configurations Size of FIFO’s (mp3 frame) Simulation :

Initial sample of FIFO undefined at output Caused by Legacy mode (chosen as a suggestion of the software)

Page 23: MindTunes Jonathan Chen, Po-Han Huang, Michael Kempf, Yen-Liang Tung, Christos Vezyrtzis FPGA mp3/wav memo recording

Thanks for help/listening