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  • Microcontroller multi-core Architecture: A real world device solving real world problems.

    NXP Microcontrollers ARM User Conference Birmingham, UK 16 May , 2012

  • NXP is a leader in ARM Flash MCUs

    Clear strategy: 100% focus on ARM

    Top performance through leading technology & architecture

    Design flexibility through pin- and software-compatible solutions

    – Scalable memory sizes – Widest range of peripherals

    Unlimited choice through complete families for multiple cores

    Cortex

    M4 Cortex

    M3 Cortex

    M0

    ARM7

    ARM9

    8051

  • 32-bit

    16-bit

    8-bit

    NXP Changing Microcontroller Landscape

    DSP

    cost performance

    Very low-end 8b e.g. 6-8 pin not planned

    High-end DSP/MPU not

    planned

    ARM Cortex-M Continuum

    Cortex-M4 Cortex-M3 Cortex-M0

    Breaking through traditional boundaries of 8b, 16b, 32b and DSP

    The ONLY vendor that offers the full range of ARM Cortex-M microcontroller families

    Binary and tool compatible

  • Cortex-M Processors: Binary Compatible

  • COMPANY CONFIDENTIAL

    Cortex-M0 Up to 50MHz

    Cortex-M3 Up to 180MHz

    Cortex-M4 Up to 204MHz

    Rapidly growing family of Cortex-M microcontrollers  For more information: www.nxp.com/microcontrollers

    5

    LPC1100

    LPC1200

    LPC1300

    LPC1700

    LPC1800

    LPC4300

    Best-in-class dynamic power consumption

    Memory options up to 128k flash

    USB solution, incl. on-chip USB drivers

    High-performance with USB, Ethernet, LCD, and more

    Memory options up to 1MB flash, 200k SRAM

    High performance M4/M0 DSC with advanced peripherals

    LPC40xx High-performance M4 with USB, Ethernet, LCD, and more

    5

    http://www.nxp.com/microcontrollers

  • LPC4300 Dual-Core MCU

    Introduction to NXP and Cortex-M4 based LPC4300

    More than one processor why? – Symmetric – Asymentric

    Asymmetric topologies – Bus infrastructure – Resources

    Communication – Hardware – Software

    Asymmetric Applications

    Debugging

    6

  • NXP Microcontrollers

    Cortex-M4, LPC4300 NXP Cortex-M4, introducing multi- core processing to microcontroller and DSP applications

    – Cortex-M4 based Digital Signal Controller featuring a highly flexible Cortex-M0 subsystem

    – Unique configurable peripherals especially suitable for motor control, solar inverter, digital power and audio applications

    + = LPC4300

    Processing Application

    Audio/Image Processing

    Control Algorithm + = Solution!

    Real Time Control

    Peripheral Control

    Protocol Emulation

    Cortex-M0Cortex-M4

    Digital Multicore award for NXP LPC4000 dual

    core microcontroller design

  • Pin/Peripheral Compatible

    Introducing the LPC4300 Family

    Cortex-M4 based Digital Signal Controller

    Cortex-M0 peripheral sub-system with dedicated configurable ‘smart’ I/O and event handling

    Up to 1 MB Flash – Dual-Bank Flash provides safe in-

    application programming (IAP)

    Large SRAM: up to 264 KB SRAM

    SPI Flash Interface with four lanes and up to 40MB/s data transfer rate.

    State Configurable Timer Subsystem

    Serial GPIO (SGPIO)

    Two High-speed USB 2.0 interfaces. An on-chip High-speed PHY

    – 10/100 Ethernet MAC – LCD panel controller (up to 1024H × 768V) – Two 10-bit ADCs and 10-bit DAC at 400ksps – Eight-channel General-Purpose DMA

    (GPDMA) controller – Motor Control PWM – Quadrature Encoder Interface – 4x UARTs, 2x I2C, 2x I2S, CAN 2.0B, 3x

    SSP/SPI – Smart card interface – Up to 146 general purpose I/O pins

    LPC4300

    Cortex-M4 LPC1800 Cortex-M3

    LPC4300

  • LPC4300 Part Numbers

    Part# Flash Total Flash A Flash B SRAM LCD Ethnt

    HS USB

    Max Freq Package

    LPC4350 0 KB 0 KB 0 KB 264 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4330 0 KB 0 KB 0 KB 264 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4320 0 KB 0 KB 0 KB 200 KB 1 204 BGA100, LQFP144 LPC4310 0 KB 0 KB 0 KB 168 KB 204 BGA100, LQFP144

    Part# Flash Total Flash A Flash B SRAM LCD Ethnt

    HS USB

    Max Freq Package

    LPC4357 1 MB 512 KB 512 KB 136 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4353 512 KB 256 KB 256 KB 136 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4337 1 MB 512 KB 512 KB 136 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4333 512 KB 256 KB 256 KB 136 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4327 1 MB 512 KB 512 KB 136 KB 1 204 BGA100, LQFP144 LPC4325 768 KB 384 KB 384 KB 136 KB 1 204 BGA100, LQFP144 LPC4323 512 KB 256 KB 256 KB 104 KB 1 204 BGA100, LQFP144 LPC4322 512 KB 512 KB 0 KB 104 KB 1 204 BGA100, LQFP144 LPC4317 1 MB 512 KB 512 KB 136 KB 204 BGA100, LQFP144 LPC4315 768 KB 384 KB 384 KB 136 KB 204 BGA100, LQFP144 LPC4313 512 KB 256 KB 256 KB 104 KB 204 BGA100, LQFP144 LPC4312 512 KB 512 KB 0 KB 104KB 204 BGA100, LQFP144

    9

  • Asymmetrical Dual Core

  • 11

  • Symmetric processing

    12

    Core 1

    Cache

    Core 2

    Cache

    Improved processing performance by distributing work load across N processors of the same type

    Complex – Cache Coherency – Requires OS support

    Amdahl's law ( can’t get 1/N speed up)

    Communication limitations as the number of cores increase

    – Hardware – Software

    Program Memory

  • Asymmetric processing

    13

    Core 1 Core 2

    Not intended to distribute 1 task over multiple cores

    Intended to process different applications

    Separate program resource per core

    Specialized OS not required

    Simple hardware for processor communication

    Program Memory Program Memory

  • M series microcontroller cores

    14

    Cortex M4

    Cortex M3

    Cortex M0

    Thumb Only No hardware divide 0.9 DMIPS/MHz

    Thumb 2 Hardware Divide 1.25 DMIPS/MHz

    Thumb 2 DSP support 1.25 DMIPS/MHz

  • Asymmetric Implementation

    15

    Cortex M4 Cortex M0

    Cortex M4 with DSP extensions Including FPU for computation

    Cortex M0 for control and communication

    Program Memory Program Memory

  • Simple IPC (inter-processor communication)

    16

    SRAM

    HOST_MSG_BUFFER

    Cortex M4 Cortex M0

    Read Pointer

    Write Pointer

    Write Pointer

    Read Pointer

    SRAM

    HOST_CMD_BUFFER

    Interrupt

    Interrupt

    AHB

    TXEV

    TXEV

    CREG

    CREG

    NVIC

    NVIC

  • 17

    AHB master regs

    AHB Matrix

    EM UL

    AT IO

    N TR

    AC E

    MO DU

    LE

    ARM Cortex-M4 or M3

    TEST/DEBUG INTERFACE USB2.0

    HS Host/ Device

    Ethernet 10/100 MAC

    S-bus

    AHB slaves

    SPIFI

    SRAM 72kB

    ROM 64kB

    I-bus

    LCD controller

    ETM

    c1 c4

    SDIO controller

    D-bus

    c2 c3

    USB2.0 HS OTG/

    Host/ Device

    DMA controller

    2x

    M0 sub- system

    ad ap

    ter

    adapter APB

    slaves4

    adapter APB

    slaves5

    adapter APB

    slaves3

    ad ap

    ter

    adapter

    SRAM 128kB

    SRAM 32kB

    SRAM 32kB

    State Cfg Timer

    External Memory controller

    adapter APB

    slaves2

    adapter APB

    slaves1

    Adapter

    Bus Master

    Bus Slave

    Memory

    VBAT VDD

    VSS

    Clock Generation, Power Control,

    and other System Functions

    Clocks and Controls

    R S

    T

    X ta

    lin

    X ta

    lo ut

    X 32

    ki n

    X 32

    ko ut

    VDDA

    JTAG interface Debug Port

    Ethernet PHY

    interface USB

    interface

    LCD interface SDIO interface

    ULPI USB FS

    HS GPIO

    12b ADC

    FP U ARM Cortex

    M0

    AES

    VSSA

    LPC4300 Bus Matrix

  • Contiguous Mode

    LPC4300 Flash Banks

    Two 512K byte banks of flash memory.

    Can be used as a single 1M byte memory area.

    Enhanced memory controller and 256-bit wide interface allows operation at up to 204MHz.

    18

    Flash B

    Flash A

    Dual Mode

    Flash B

    Flash A

  • LPC4300 Memory Model

    M4 and M0 can execute from FLASH without contention

    M0 can execute from its own RAM (4 options)

    ROM written in thumb mode means both M4 and M0 can use ROM code

    M4 MPU can be used to protect M0 code space.

    19

  • Cortex-M0 Subsystem: Bus Matrix Connections AH

    B Ma

    trix

    CORTEX-M4 204MHz

    CORTEX

    -M0 204MHz

    SRAM 128 KB

    ROM S I D

    72 KB

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