melay fsm 0110
DESCRIPTION
program code for sequence detector(0110) using mealy machinesit covers both vhdl and verilog code along with simulation waveformsTRANSCRIPT
MELAY FSM (0110)
OBJECTIVE:
To develop the source code for sequence detecter(mealy machine) by using vhdl/verilog and obtain the simulation, synthesis, place and route and implement into fpga.
METHODOLOGY:
A sequential machine is a quintule, M=(X,Z,S,f,g), where X,Z, and S are the finate and nonempty sets of inputs, outputs and states respectively, f is the next – state function, such that
St+1= f(St,Xt)
and g is the output function such that
Zt=g(St,Xt) for the mealy machine
BLOCK DIAGRAM:
1/0
0/0
1/0 0/1
0/0
0/0
1/0 1/0
SOURCE CODE:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seqvermealy is
S1 S3
S0
S2
Port ( a : in STD_LOGIC;
clk : in STD_LOGIC;
z : out STD_LOGIC);
end seqvermealy;
architecture Behavioral of seqvermealy is
type states is (s0,s1,s2,s3);
signal pst,nst: states;
begin
process(clk)
begin
if(clk='0') then
pst<=nst;
end if;
end process;
p1:process(pst,a)
begin
case pst is
when s0=>
if(a='0') then
z<='0';
nst<=s1;
else
z<='0';
nst<=s0;
end if;
when s1=>
if(a='0') then
z<='0';
nst<=s1;
else
z<='0';
nst<=s2;
end if;
when s2=>
if(a='0') then
z<='0';
nst<=s1;
else
z<='0';
nst<=s3;
end if;
when s3=>
if(a='0') then
z<='1';
nst<=s1;
else
z<='0';
nst<=s0;
end if;
end case;
end process p1;
end Behavioral;
VERILOG CODE:
module seqdec(a,clk,z);
input a;
input clk;
output z;
reg z;
parameter s0=0,s1=1,s2=2,s3=3;
reg[0:1] states;
initial
begin
states=s0;
end
always@(posedge clk)
case(states)
s0:
begin
if(a) begin
z=0;
states=s0;
end
else begin
z=0;
states=s1;
end
end
s1:
begin
if(a) begin
z=0;
states=s2;
end
else begin
z=0;
states=s1;
end
end
s2:
begin
if(a) begin
z=0;
states=s3;
end
else begin
z=0;
states=s1;
end
end
s3:
begin
if(a) begin
z=0;
states=s0;
end
else begin
z=1;
states=s1;
end
end
endcase
endmodule
RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:
FLOOR PLANNER:
XPOWER ANALYZER:
SUMMARY:
THERMAL INFORMATION:
VOLTAGE SOURCE INFORMATION:
SIMULATION WAVEFORMS:
SYNTHESIS REPORT:
Release 10.1 - xst K.31 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to C:/kalyan/sequencedetector/0110mealy/xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Parameter xsthdpdir set to C:/kalyan/sequencedetector/0110mealy/xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs
--> Reading design: seqdetector.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "seqdetector.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "seqdetector"
Output Format : NGC
Target Device : xc3s500e-5-fg320
---- Source Options
Top Module Name : seqdetector
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : seqdetector.lso
Keep Hierarchy : NO
Netlist Hierarchy : as_optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/kalyan/sequencedetector/0110mealy/seq.vhd" in Library work.
Architecture behavioral of Entity seqdetector is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <seqdetector> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <seqdetector> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/kalyan/sequencedetector/0110mealy/seq.vhd" line 41: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<nst>
Entity <seqdetector> analyzed. Unit <seqdetector> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <seqdetector>.
Related source file is "C:/kalyan/sequencedetector/0110mealy/seq.vhd".
WARNING:Xst:737 - Found 4-bit latch for signal <pst>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Using one-hot encoding for signal <pst>.
Unit <seqdetector> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Latches : 1
4-bit latch : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx\10.1\ISE.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Latches : 1
4-bit latch : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <seqdetector> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block seqdetector, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : seqdetector.ngr
Top Level Output File Name : seqdetector
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 3
Cell Usage :
# BELS : 6
# LUT2 : 3
# LUT2_L : 1
# LUT3 : 1
# LUT4 : 1
# FlipFlops/Latches : 4
# LD_1 : 4
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 2
# IBUF : 1
# OBUF : 1
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 3 out of 4656 0%
Number of Slice Flip Flops: 4 out of 9312 0%
Number of 4 input LUTs: 6 out of 9312 0%
Number of IOs: 3
Number of bonded IOBs: 3 out of 232 1%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 4 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 2.715ns (Maximum Frequency: 368.331MHz)
Minimum input arrival time before clock: 2.676ns
Maximum output required time after clock: 5.329ns
Maximum combinational path delay: 5.851ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.715ns (frequency: 368.331MHz)
Total number of paths / destination ports: 8 / 4
-------------------------------------------------------------------------
Delay: 2.715ns (Levels of Logic = 2)
Source: pst_1 (LATCH)
Destination: pst_1 (LATCH)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: pst_1 to pst_1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD_1:G->Q 2 0.588 0.532 pst_1 (pst_1)
LUT2_L:I0->LO 1 0.612 0.103 nst<1>_SW0 (N21)
LUT4:I3->O 1 0.612 0.000 nst<1> (nst<1>)
LD_1:D 0.268 pst_1
----------------------------------------
Total 2.715ns (2.080ns logic, 0.635ns route)
(76.6% logic, 23.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 2.676ns (Levels of Logic = 2)
Source: a (PAD)
Destination: pst_0 (LATCH)
Destination Clock: clk rising
Data Path: a to pst_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 1.106 0.690 a_IBUF (a_IBUF)
LUT3:I0->O 1 0.612 0.000 nst<0>1 (nst<0>)
LD_1:D 0.268 pst_0
----------------------------------------
Total 2.676ns (1.986ns logic, 0.690ns route)
(74.2% logic, 25.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 5.329ns (Levels of Logic = 2)
Source: pst_3 (LATCH)
Destination: z (PAD)
Source Clock: clk rising
Data Path: pst_3 to z
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LD_1:G->Q 3 0.588 0.603 pst_3 (pst_3)
LUT2:I0->O 1 0.612 0.357 z1 (z_OBUF)
OBUF:I->O 3.169 z_OBUF (z)
----------------------------------------
Total 5.329ns (4.369ns logic, 0.960ns route)
(82.0% logic, 18.0% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 5.851ns (Levels of Logic = 3)
Source: a (PAD)
Destination: z (PAD)
Data Path: a to z
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 1.106 0.607 a_IBUF (a_IBUF)
LUT2:I1->O 1 0.612 0.357 z1 (z_OBUF)
OBUF:I->O 3.169 z_OBUF (z)
----------------------------------------
Total 5.851ns (4.887ns logic, 0.964ns route)
(83.5% logic, 16.5% route)
=========================================================================
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.55 secs
-->
Total memory usage is 157256 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
DESIGN SUMMARY:
fsmmelay Project Status
Project File: fsmmelay.ise Current State: Placed and Routed
Module Name: melayfsm Errors: No Errors
Target Device: xc3s500e-5fg320 Warnings: 6 Warnings
Product Version: ISE 10.1 - Foundation Simulator Routing Results: All Signals Completely Routed
Design Goal: Balanced Timing Constraints: All Constraints Met
Design Strategy: Xilinx Default (unlocked) Final Timing Score: 0 (Timing Report)
fsmmelay Partition Summary [-]
No partition information was found.
Device Utilization Summary [-]
Logic Utilization Used Available Utilization Note(s)
Number of Slice Latches 6 9,312 1%
Number of 4 input LUTs 5 9,312 1%
Logic Distribution
Number of occupied Slices 5 4,656 1%
Number of Slices containing only related logic 5 5 100%
Number of Slices containing unrelated logic 0 5 0%
Total Number of 4 input LUTs 5 9,312 1%
Number of bonded IOBs 3 232 1%
Number of BUFGMUXs 1 24 4%
Performance Summary [-]
Final Timing Score: 0 Pinout Data:Pinout Report
Routing Results: All Signals Completely Routed Clock Data:Clock Report
Timing Constraints: All Constraints Met
Detailed Reports [-]
Report Name Status Generated Errors Warnings Infos
Synthesis Report Current Wed Jan 2 10:58:47 2013 0 5 Warnings 2 Infos
Translation Report Current Wed Jan 2 11:00:46 2013 0 0 0
Map Report Current Wed Jan 2 11:00:49 2013 0 1 Warning 2 Infos
Place and Route Report Current Wed Jan 2 11:00:57 2013 0 0 1 Info
Static Timing Report Current Wed Jan 2 11:00:59 2013 0 0 3 Infos
Bitgen Report
Date Generated: 01/02/2013 - 11:13:56
CONCLUSION:
Thus the design of sequence detector using VHDL and Verilog HDL using behavioural programming design is implemented successfully.