low-voltage high performance compact all cascode cmos current mirror
TRANSCRIPT
Low-voltage high performance compact allcascode CMOS current mirror
A. Garimella, L. Garimella, J. Ramirez-Angulo,A.J. Lopez-Martın and R.G. Carvajal
A high performance and compact current mirror with extremely low
input and high output resistances (Rin� 0.01O, Rout� 10 GO), high
copying accuracy, very low input and output voltage requirements
(Vin, Vout�VDSsat), high bandwidth (200 MHz using a 0.5 mm CMOS
technology) and low settling time (25 ns) is proposed. Simulations and
experimental results are shown that validate the circuit.
Introduction: To improve the accuracy and performance characteristics
of the basic current mirror, the active scheme shown in Fig. 1a can be
used [1]. It includes two auxiliary amplifiers A1 and A2. Amplifier A1
together with a flipped voltage follower (FVF) [1] formed by M1 and
M1C implements a double nested shunt feedback loop that lowers
input resistance by the gain of amplifier A1 to a value:
Rin¼ 1=(gm1gm1Cro1CA1). The cascode regulating amplifier A2 at
the output side has two purposes: (i) to boost the output impedance
by a factor A2 to a very high value Rout¼A2ro2gm2Cro2C; and (ii) to
satisfy the condition VDS1¼VDS2 to improve accuracy and linearity.
A1 and A2 were implemented in [1] using common source PMOS
amplifiers with gain A1, A2� gmro This implementation required
threshold voltages jVTPMOSj> VTNMOS to maintain the active transis-
tors in A1, A2 in saturated mode. This condition is difficult to satisfy
in some deep submicrometre CMOS technologies.
Fig. 1 Double nested regulated cascode mirror scheme; implementation ofauxiliary amplifiers A1 and A2; all cascode mirror
a Double nested regulated cascode mirror schemeb Implementation of auxiliary amplifiers A1 and A2c All cascode mirror
All cascode mirror: Fig. 1c shows a compact high gain implementa-
tion of the current mirror scheme of Fig. 1a using NMOS cascode
amplifiers for A1 and A2. These amplifiers use as reference voltage
Vref, the lowest rail voltage, which is in this case equivalent to the
level shifted voltage at the positive input terminals of A1 and A2 in
Fig. 1c. The auxiliary amplifiers have in this case gains A1,
A2�(gmro)2 that lead to extremely low input resistance Rin¼
1=[gm(rogm)3] (�0.01 O) and extremely high output resistances
Rout¼ ro(rogm)3 (�10 GO) at the mirror’s input and output node,
respectively. Because of these characteristics we denote the circuit
of Fig. 1c all cascode mirror (ACM). This circuit has only low
impedance nodes (with the exception of the dominant pole nodes
VY, V0Y and VZ in each feedback loop). For this reason it can have
simultaneously very high bandwidth and high phase margin. The
input resistance is so low that, if a typical single feedback loop is
used, it would only be achievable by using an extremely high gain
amplifier �(gmro)3 with the associated stability problems that can only
be circumvented at the expense of severely reducing the bandwidth. If
required, the circuit of Fig. 1c can be compensated using very small
valued capacitors CC, C0C and CC00 connected at the high impedance
(dominant pole) nodes VY, V0Y and VZ, although the need for compen-
sation can be obviated if gmMA1,2 is much lower than gmM1, gmM2. This
is easily achieved by using scaled down versions of M1 and Ibias for
MA1, MA1C and I0bias (e.g. by a factor 10). This has the advantage of
essentially reducing the silicon area and power dissipation require-
ments of A1, A2. A limitation of this implementation is that the
minimum input and output voltages are relatively large compared to
those of the conventional FVF mirror: VinMIN¼VGSA1, Vo
MIN¼
VGSA2þVDSsatM2C and for this reason the circuit is not appropriate
for utilisation in the low supply environment required by modern
CMOS technologies. It is also difficult to maintain M1C in saturation
unless a level shifter is used in the FVF feedback loop.
Fig. 2 Low voltage all cascode mirror implementation, and equivalentcircuit and symbol of floating gate transistor
a Low voltage all cascode mirror implementationb Equivalent circuit and symbol of floating gate transistor
Fig. 3 Simulations
a Output characteristics of ACMb Output characteristics of LVACMIin parametrised from 20 to 100 mA in 20 mA steps
Low voltage implementation of ACM: Fig. 2a shows a low-voltage
implementation of the all cascode mirror (denoted LVACM). It uses a
floating gate transistor MAi in each of the auxiliary amplifiers Ai. The
floating gate of MA1 (MA2) is coupled to node VX (V0X) and to VDD
through small valued capacitors Ca and Cb, respectively. Assuming
zero net charge on the floating gate of MA1 and MA2 (a condition
easily achieved using the layout technique described in [2]), it can be
shown [3] that VX¼VGSMA1�Vbat where Vbat¼ (Cb=Ca)[VDD�
VGSMA1]. A similar analysis leads to V0X¼VGSMA2�Vbat. Notice
that the floating gate transistor in conjunction with Ca and Cb acts
as a floating battery (as illustrated in Fig. 2b) that reduces the voltage
at node VX(V0X) with respect to VGSMA1 by the value Vbat. The ratio
Cb=Ca can be calculated so that VX (V0X)’VDSsat. This leads to an
essential reduction in the minimum input and output supply require-
ments. The capacitive divider formed by Ca and Cb reduces the
effective open loop gain of A1 and A2 by the factor k¼Ca=(CaþCb).
In practice k can take values of the order of k¼ 0.5 so that this
attenuation does not essentially affect the performance of the
proposed mirror. Once the voltage at VX and V0X reaches a value
VDSsat the voltage at the floating gates of MA1 and MA2 reaches the full
operating value VGS that turns A1 and A2 on. With this they apply
their regulating effect that leads to very low input impedance and very
high output impedance. This takes place even if the cascoding
transistors M1C, M2C operate in triode mode with VDSM1C and
VDSM2C close to zero. For this reason VinMIN, Vout
MIN in the circuit of
Fig. 2b take values close to VDSsat. This is essentially lower than for
the circuit of Fig. 1c, which requires a minimum output voltage
VoutMIN¼VGSþVDSsat. This can be confirmed in the SPICE simulations
of Fig. 3. Regulated cascode mirror implementations using cascode
ELECTRONICS LETTERS 8th December 2005 Vol. 41 No. 25
auxiliary amplifiers (mainly folded cascode opamps) have been
reported in the past that lead to similar high output impedances (but
higher input impedance) as the LVACM (see e.g. [4]). However most
reported approaches require relatively complex circuitry with essen-
tial additional power dissipation and silicon area requirements and
introduce pole zero doublets that can seriously affect stability or
introduce long-settling components in the transient behaviour.
Simulation results: The ACM and LVACM circuits of Figs. 1c and 2a
were simulated in CADENCE DFWII using 0.5 mm CMOS AMI-
MOSIS technology parameters with nominal threshold voltages of
0.73 and �0.95 V for NMOS and PMOS transistors, respectively. Bias
currents with values Ibias¼ 25 mA, I0bias¼ 5 mA, a single supply voltage
VDD¼ 3V, and a load resistance RL¼ 5 kO were used. Capacitors had
values Ca¼ 750 fF, Cb¼ 250 fF. Transistor dimensions (in mm) were:
W=L¼ 50=1.2 for M1, M1C, M2 and M2C and W=L¼ 5=1.2 for transis-
tors in A1, A2. Cascode current sources were used to implement Ibias
and I0bias with PMOS transistors with dimensions W=L¼ 100=1.2 and
W=L¼ 10=1.2, respectively, No compensation capacitors were
required. The floating gate model reported in [5] was used to simulate
floating gate transistors. Fig. 3 shows the simulated DC output
characteristics of the ACM of Fig. 1c and the LVACM of Fig. 2a with
Iin parametrised from 20 to 100 mA in 20 mA steps. From simulations,
the output resistance was determined to be 8 GO, at a current level of
50 mA. The LVACM minimum output voltage was approximately
0.15 V. The copy error was below 0.1%. The bandwidth from AC
simulations was approximately 200 MHz (with negligible peaking in
the frequency response) and the 0.1% settling time was 25 ns.
Measurement results: A test chip including the ACM and LVACM
circuits of Figs. 1c and 2a was fabricated in AMI 0.5 mm CMOS
technology. The chip used the same dimensions and was tested under
similar biasing conditions as for the simulations discussed above.
Fig. 4 shows the experimental DC output characteristics obtained
using a curve tracer. The measured input voltage at node VX had an
approximate constant value of 200 mV for the proposed LVACM and
750 mV for the ACM. It can be observed that the results of Fig. 4
show strong resemblance to the simulations shown in Fig. 3. This
verifies the proposed schemes.
a b
Fig. 4 Experimental output characteristics of ACM and of LVACM
a ACMb LVACMHorizontal axis 0.2 V=div., vertical axis 20 mA=div.
Conclusions: A new and very compact implementation of a high
performance current mirror has been introduced and validated with
simulations and with experimental results from a fabricated chip. This
circuit has extremely low input impedance (lower than any previously
reported approach), high bandwidth, extremely high output impe-
dance, low input and output voltage requirements and high accuracy.
Because of its characteristics it can be used for the implementation of
low voltage, low power, ultra-high-gain operational amplifiers with
very short settling time.
Acknowledgment: Financial support from the Spanish CICYT under
projects TIC2002-04323-C03-01 and TIC2003-07307-C02 is
acknowledged.
# IEE 2005 13 August 2005
Electronics Letters online no: 20052918
doi: 10.1049/el:20052918
A. Garimella, L. Garimella and J. Ramirez-Angulo (Klipsch School of
Electrical and Computer Engineering, New Mexico State University,
Box 30001=Dept. 3-0, Las Cruces, NM, USA)
E-mail: [email protected]
A.J. Lopez-Martın (Departamento de Ingenieria Electrica y
Electronica, Universidad Publica de Navarra, Spain)
R.G. Carvajal (Departamento de Ingenieria Electronica, Escuela
Superior de Ingenieros, Universidad de Sevilla, Spain)
References
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