Literature Review on Emerging Memory Technologies

Fengbo Ren

Apr. 1st 2011

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Background

Existing Memory Technology

Scaling become very difficult at and below 45-nm– SRAM suffers leakage– DRAM’s capacitor need to sustain enough charges– Flash needs novel array structure

SRAM DRAM

Flash

Background

Dream about “Universal Memory”– Fast read and write speed of SRAM– Density and cost benefits of DRAM– Non-volatility of flash– Unlimited endurance

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Phase Change RAM

Resistive RAM

Spin Torque Transfer

RAM

Basic Concept — PRAM

Represents “0/1” by Crystalline and Amorphous

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High R Low R

0 1

T > crystallization point

Ge2Sb2Te5

(GST)

High T > melting point

Basic Concept — STTRAM

Represents “0/1” by Magnetization Direction Alignment

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Parallel Anti-parallel

Low RP High RAP

Write

Read

Write

Read

Magnetic Tunnel Junction (MTJ)

Ferro-magnetic Materials

High current, fast switching, bigger cell

size

Low current, Slow switching, smaller cell

size

Basic Concept — RRAM

Represents “0/1” by resistance difference of dielectric

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- V

+ V

Over Drive

Wearing

Metal Oxides

Low R High R

State-of-Art Comparison

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PRAM– Flash density & endurance + Fast R/W speed

STTRAM– SRAM density & R/W speed + Highest endurance

RRAM– <SRAM density & R/W speed + High endurance

Mem. Type DesignerMemory Size

Power Supply

(V)

Cell Structur

e

CMOS Process

(nm)

Cell Size (F^2)

Rd.Time (ns)

Endurance (cyc.)

Memory Device Char.

Wrt. I / V Wrt./Ers. Time (ns)

RL (Ω) RH/RLVariation

Range (RL/RH)

SRAM [1] 　 　 　 6T 　 50-80 1-100 10^16 Low 1-100 　 　 　

DRAM [1] 　 　 　 1T1C 　 6-8 30 10^16Refresh Current

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FLASH [1] 　 　 　 NOR 　 5-10 3-15 10^5 High 10^3/10^6 　 　 　PRAM [2] Samsung 256 Mb 1.8/4.5 1T1GST 100 16.6 10 10^7 800-1000uA 100/500 1k 100 3-10xPRAM [3] Samsung 512 Mb 1.8 1D1GST 90 5.8 8 10^5 600-1000uA 430 1k 1000 3xPRAM [4] Numonyx 1 Gb 1.8 1BJT1GST 45 7.4 　 10^8 200uA 　 10k 100 1-5xPRAM [5] STMicro 4 Mb 1.2/3.6 1T1GST 90 36 12 10^6 400uA/4V 100/300 5k-7k 200 　

STTRAM [6] Sony 4 Kb 　 1T1MTJ 180 　 　 10^12 200-700 uA 2-1000 1.7k 2.6 3-4%STTRAM [7] Hitachi 2 Mb 1.8 1T1MTJ 200 64 40 10^9 200 uA 100 5k 2 　STTRAM [8] Qualcomm 32 Mb 1.1/1.8 1T1MTJ 45 50.7 <100 10^12 150-250 uA 10-1000 2.4k 2.1 　STTRAM [9] NEC 32 Mb 1/1.5 2T1MTJ 90 169 12 　 600-1000 uA 　 　 　 　

STTRAM [10] Fujitsu & UT 16 Kb 1.2/3.3 1T1MTJ 130 327 8 　 400-870 uA 9-10 　 　 　STTRAM [11] Toshiba 64 Mb 1.2 2T1MTJ 65 84.8 11 　 49 uA 30 　 　 　RRAM [12] Fujitsu 　 3 1T1R 180 　 　 >10^5 0.7-2.8V 5-50 1.2k >90 1-30RRAM [13] NTHU 　 1.5 1T1R MLC 180 30-300 　 >10^6 1.4 V >5 1.2k >1000 1.1x/100xRRAM [14] NTHU 　 1.4 1T1R 　 　 　 >10^10 1.5-1.6 V >0.3 1k-10k >10 1.2x/50xRRAM [15] NTHU 4 Mb 0.7-1.8 1T1R 　 　 3.6 　 <25uA 0.3 0.8k >100 　RRAM [16] Sony 4 Mb 1.8/3.3 1T1R 180 69 56 　 　 74 10k 　 2x/80x

Challenges—PRAM

Resistance and threshold voltage drift over time– Cause chip failure in long term– Limits the ability for multilevel operation

Speed vs. data retention time– If the switching thermal condition is close to standby

condition, e.g. room temperature● Faster switching speed — intended switching● Worse data retention time — higher probability of accidental

switching

Sensitive to temperature – Narrower operation window (0-70°C )

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Challenges—STTRAM

The switching current required is still too high.– 1-8x106 A/cm²

● Typical transistor:105-106 A/cm²● Bigger transistor size -> bigger cell size -> poor density● Boosting voltage -> higher power● Switching energy of MTJ is 2-3 orders of magnitude bigger than a

CMOS gate

– Lower switching current is desired

Low Rhigh/Rlow ratio

– 5x is the highest ratio reported, 2-3x in practical● Small sensing margin for reading

– Lower switching current -> even smaller sensing margin

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Challenges—RRAM

Need to understand the physics– Conduction filament formation & broken mechanism– Resistance & resistance variation dependency on bias

voltage– Wearing mechanism– Build precise compact model for CAD flow

Significant resistance variation– Worse sensing margin– Deteriorate the multi-level operation capability

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Conclusion

PRAM– Flash density & endurance + < Flash R/W speed– Nice replacement of Flash, commercial product is available

STTRAM– SRAM density & R/W speed + Highest endurance– Require better MTJ with smaller switching current to achieve

higher density

RRAM– Initial stage of exploration – <SRAM density & R/W speed + High endurance– Potential of multi-level operation– Lot of studies need to be done

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Thank You!

References[1] F. Tabrizi, ”The future of scalable STT-RAM as a universal embedded memory”, Available:http://www.eetimes.com/design/embedded/4026000/The-futureof-scalable-STT-RAM-as-a-universal-embedded-memory.[2] S. Kang, et al., ”A 0.1-m 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous

Burst-Read Operation”, JSSC, vol. 42, no. 1, pp. 210–218, 2007.[3] K.J. Lee, et al., ”A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput”, ISSCC, 2008, pp. 150–

162.[4] G. Servalli, ”A 45nm generation Phase Change Memory technology”, IEDM, 2009, pp. 1–4.[5] G. De Sandre, et al., ”A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS

Technology”, JSSC, vol. 46, no. 1, pp. 52–63, 2011.[6] M. Hosomi, et al., ”A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM”,

IEDM, 2005, pp. 459–462.[7] Takayuki Kawahara, et al., ”2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write

and Parallelizing-Direction Current Read”, ISSCC, 2008, pp. 109–120.[8] C.J. Lin, et al., ”45nm Low Power CMOS Logic Compatible Embedded STT MRAM Utilizing a Reverse-Connection

1T/1MTJ Cell”, IEDM, 2009, pp. 1–4.[9] R. Nebashi, et al., ”90nm 12ns 32Mb 2T1MTJ MRAM”, ISSCC, 2009, pp. 462–463.[10] David Halupka, et al., ”Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13m CMOS”, ISSCC,

2010, pp. 256–257.[11] Kenji Tsuchida, et al.,”A 64Mb MRAM with Clamped-Reference and Adequate-Reference Schemes”, ISSCC, 2010,

pp. 258–259.[12] K. Tsunoda, et al., ”Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage

Source of less than 3 V”, IEDM, 2007, pp. 767–770.[13] H.Y. Lee, et al., ”Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust

HfO2 Based RRAM”, IEDM, 2008, pp. 1–4.[14] H.Y. Lee, et al., ”Evidence and solution of Over-RESET Problem for HfOX Based Resistive Memory with Sub-ns

Switching Speed and High Endurance”, IEDM, 2010, pp. 19.7.1–19.7.4.

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