|letter a new charge pump pll with reduced...

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IEICE TRANS. COMMUN., VOL E84-B, N0 .6 JUNE 2001 l 6 8 0 |LET T ER A New Charge Pump PLL with Reduced Jitter ~ T he amount of FST , SLW node voltage drift increases a the diHer-- ®ce between the node and bias voltages increases. Consequently, PLL jitter characteristics get w or se a its operation frequency moves away from the center frequency. A new charge pump structure (Type H) that mini- mizes the above problem is shown in Fig.3. T his charge pump uses a self-biased method and functions a a diL f er en t i a,l ch ar ge p u m p . It has current mirrors which establish current path 9 from path @ when both UP and DN signals are logic ®1.¯ W hen UP and DN signals are both logic ®O,¯ PM OS and NM OS transistors are d l turned OH. T he FST and SLH7 node voltages should re- main 6xed, Ä there is no leakage path. As a result , the PLL output jitter is reduced. W hen UP and DN sig- nals are both logic ®1,¯ which happens during the PFD reset time, a FST , SLW node voltages in both charge pump structures can drift. However, this is not a major SUM M A RY A n ew c h a r g e p u m p i s p r o p o se d w h i c h p r o v i d e s i h m ×n m §1 m1 £ W ¦p w ¦r mo w ¦v w Þe d j i t t e r c h a r a c t e r i s t i c s f o r a p h a e - l o c k e d l o o p ( P L L ) . T h e P L L w i t h t h e p r o p o se d c h a r g e p u m p is i m p le m e n t e d w i t h 0 .6 P m CM O S t e c h n o l o g y . T h e m e as u r e d RM S o u t p u t j i t t e r is a m uch Ä 28% s m a l l e r t h a n that o f a P L L with a p re v i o u s l y reported charge pump structure. key wom -: c h a r g e p u m p , p h a s e - l o c k e d l o o p ¥ , × er char- o ctertstzcs 1 I n t r o d u c t i o n A charge pump is widely used in the phase-locked loop (PLL) for many applications Ì , Ò . Figure 1 shows the block diagram of the charge-pump PLL. Ideally, two outputs of PhÄ e/ D equem y Detector (PFD) should h aq the same logic values and the charge pump output should be Hxed when the PLL is locked. However, this does not happen in real circuits as the charge pump circuit usually hÄ asymmetric features that cause the Hud nation in the Voltage Controlled Oscillator (VCO) control voltage and PLL output phase noise. In order to minimize this problem, a new charge pump structure 1188 beeu proposed Ò . T he PL L circuit that ha the proposed charge pump is realized and its j itter char- ad eristics are compared with those of a previously re- poI-- d charge pump PLL ¹ . |N Design of Phase-Locked Loop 2 . Block diagram for phase-locked loop. F i g . 1 Fig ¤p 2 shows the conventional charge pump structure (Type I) Þ . W hen either- UP or DN signal is logic ®1¯ and £ p other is logic ¤0.®FST or SLH7 node is charged and 1lie other node is discharged, respectively- This In n-hips 1lu¤VC0 control voltage required for PLL op PIn t ion - R Then t he P L L is locked , b ot h U P and D N signals-s Hrp logic ¤0¯ as there is no plm e/ frequency diL fu¤cllrp bd ween PLL input and output- In this cme± CHITo n paths represented by dotted lines in Fig.2 are established and FST ® SLW node voltages should re- main ONto - However- if FST . SLM7 node voltages diHer from dw initial bias voltages, they drift because the OIl-- nt d1h ¤ ing capabilities of PM 0 S and NM OS tran- sid ol-s b¤ ing in tile same cu1Tent path are not the same- Manuscript received A ugust 2, 2000. èT he authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul, 12* 749, Korea. 11T he author is with Samsung Electronics, Korea.

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Page 1: |LETTER A New Charge Pump PLL with Reduced Jittertera.yonsei.ac.kr/publication/pdf/Jour_2001_ygkim_TC-01.pdf · A New Charge Pump PLL with Reduced Jitter ~ ... and D N signals are

IEI CE T RA NS. CO M M UN ., V OL E84- B , N0 .6 JUNE 2001

l 6 8 0

|LETT ERA N ew Char ge Pump PLL wit h Reduced J it t er

~

T he am ount of F ST , SLW node vol t age d r i f t i ncr easesa t he d i Her-- ®ce b et ween t he node and b ias vol t ages

incr eases. C onsequent ly , P L L j i t t er ch ar act er ist ics getw or se a i t s oper at ion fr equency m ov es aw ay fr om t he

cent er f requency .A n ew ch ar ge pu m p st r uct ur e (T y p e H ) t hat m in i-

m izes t he ab ove p r obl em is show n i n F ig . 3 . T h is char gepu m p uses a sel f-b iased m et hod and fun ct ion s a a d iL

fer ent i a,l ch ar ge pum p . I t has cur rent m ir r or s w h ich

est ab l ish cu r r ent pat h 9 f rom p at h @ w h en bot h U Pand D N signals are logic ®1.¯ W hen U P and D N signals

ar e b ot h logic ®O,¯ P M O S and N M O S t r ansist or s are d l

t u r ned OH. T he F ST an d SLH 7 node vol t ages shou ld re-

m ain 6x ed , Ä t her e i s no leakage pat h . A s a r esu l t , t heP L L ou t p ut j i t t er is red uced . W hen U P an d D N sig-n als are bot h logic ®1,¯ w h ich happ ens d u r ing t he P F D

r eset t i m e, a F ST , SLW node volt ages i n b ot h charge

pu m p st r uct u res can d r i f t . H owever , t h is is not a m aj or

S U M M A R Y A n e w c h a r g e p u m p i s p r o p o se d w h i c h p r o v i d e s

ihmm×nm§1m1£W¦ pw¦ rmmow¦ vwÞ ed j i t t e r c h a r a c t e r i s t i c s f o r a p h a e - l o c k e d l o o p ( P L L ) . T h e

P L L w i t h t h e p r o p o s e d c h a r g e p u m p i s i m p l e m e n t e d w i t h 0 .6 P m

C M O S t e c h n o l o g y . T h e m e as u r e d R M S o u t p u t j i t t e r i s a m u c h

Ä 2 8 % s m a l l e r t h a n t h a t o f a P L L w i t h a p re v i o u s l y r e p o r t e d

c h a r g e p u m p s t r u c t u r e .

k e y w o m - : c h a r g e p u m p , p h a s e - l o c k e d l o o p ¥ L í , × e r c h a r -

o c t e r t s t zc s

1 I n t r o d u c t i o n

A char ge pu m p is w idely used in t he ph ase- l ocked loop

(P L L ) for m any ap p l icat ions Ì , Ò . F igu re 1 show s t heb lock d iagr am of t he ch ar ge-p u m p P L L . I d eal ly , t w o

ou t put s of P h Ä e/ D equem y D et ect or (P F D ) shou ld

haq t he sam e logic val ues and t he char ge p um p ou t p u tshou ld b e Hx ed w hen t he P L L is locked . H owever , t h is

does not happ en in real ci rcu i t s as t he char ge pum pcir cu it usual ly hÄ asy m m et r ic feat u res t hat cause t h e

Hud nat ion i n t he Vol t age C on t r ol led O sci l l at or (V C O )cont rol vol t age and P L L ou t pu t p h ase noise. I n or der

t o m ini m ize t h is pr ob lem , a new ch arge p um p st r uct u re1188 beeu pr oposed Ò . T he P L L ci r cu i t t h at ha t hepr oposed ch arge pu m p is real ized and it s j it t er char -ad er ist ics are com par ed w i t h t hose of a p r ev iously r e-poI-- d char ge pum p P L L ¹ .

| N

Design of Phase-Locked Loop2 .

B lock d iag ram for phase- locked loop .F i g . 1

F ig ¤ p 2 show s t he convent ional ch ar ge p um p st r uct ur e(T y pe I ) Þ . W hen ei t her- U P or D N sign al is log ic ®1¯

and £ p ot her is logic ¤0 .® F ST or SLH 7 no de is char ged

and 1l ie ot her node is d ischarged , resp ect ively - T h isIn n-h ips 1lu¤V C 0 cont r o l vo l t age r equ i r ed for P L L opPIn t ion - R Then t he P L L is locked , b ot h U P and D Nsignals-s Hrp logic ¤0 ¯ as t here is no p lm e/ f requency d iL

fu ¤cl lr p bd w een P L L inp u t and ou t pu t - I n t h is cm e±

CHITo n pat hs r ep r esent ed by dot t ed l i nes i n F ig . 2 areest ab l ished and F ST ® SLW nod e vol t ages shou ld r e-m ain ONto - H owever - i f F ST . SLM 7 no de vol t ages d iHer

fr om d w in i t ia l b ias vol t ages, t hey d r i f t b ecause t heO Il-- nt d 1h ¤ing capab i l i t ies of P M 0 S and N M O S t ran-

sid ol-s b ¤i ng in t i le sam e cu 1Tent p at h ar e n ot t he sam e-

M anuscr ipt received A ugust 2, 2000.èT he aut hors are wit h t he D epar t ment of E lect r ical and

Elect ronic Engineer ing, Yonsei Universit y, Seoul , 12* 749,K orea.

11T he aut hor is wi t h Samsung E lect ronics, K orea.

Page 2: |LETTER A New Charge Pump PLL with Reduced Jittertera.yonsei.ac.kr/publication/pdf/Jour_2001_ygkim_TC-01.pdf · A New Charge Pump PLL with Reduced Jitter ~ ... and D N signals are

L E T T E R1 6 8 1

2 2( µÍ5¹ m

2 0

1 8 T y p eI nga----2 5

( µÍ5u m

Schemat ic diagram for newly proposed charge puttoF ig . 3(T y pe H ) .

- - - -Type l- - - - Type I I2 08 |

µ | 1£ 2 O4 L - J - - - - - |-¹ ¸ --- - -¦ ¯ lì | |

2 0O ̄ .6 9½ 6 93 6 95

T lM E(u s )

(c )

F ig . 5 T he t r ansient var iat ions of t he cont ro l volt age. (a) T y peI , (b ) T y pe I I , (c ) T he m agn ined wavefor ms.

pr obl em because t he d u r at ion of t he P F D reset t im e is

r elat ively sm al l .T o com p ar e t he p er for m an ce b et ween t he conven-

t ion al ch ar ge pum p (T y p e I ) and t he new ly pr op osed

char ge pum p (T y p e H ) , t w o P L L ci r cu i t s ar e desi gnedeach of w h ich includes T y p e I or T y p e I I ch ar ge p um p .E ach P L L h Ä a convent ional P F D Ò , a fo u r -st age

fr equency d iv i der ( 1/ 16 ) m ade up of fou r dy nam ic D -tH e m p - ps ¹ , and a secon de r-der on -ch ip loop Hl t ¤ -

T he lo op Gl t ¤ par am et er s (R 1 = 5000 O , G = 200 p Fa d Q = 20 p F ) are chosen so t hat t he d am p in g fa -

t or of t h e closed- loop t r an sfer fun ct ion is 0 .707. T h is

cor resp onds t o t he loop b and w id t h of 3 .3 M H z. Fqt he V C 0 , a six -st age d iHer a d i al r ing osci l l at or is used -

E ach r ing osci l lat or st age is com p osed o f a d iga - -Li al N M 0 S p air w it h var iab le r esist ance loads m ade of

P M O S dev i ces op er at ing in t he t r io de r egion . F igur e 4

show s t he SP I C E simu l at ion r esu l t s for V C O ou t p u t at

t he osci l lat ion f requency of 1.03 G H z. F igu r e 5 show st he si m u lat ed t r ansient r esp onses of V C 0 cont r ol vo l t -

ages for t w o P L L ci r cu i t s hav i ng d ig ¤ - m char ge pu m ps(T y p e I , T y pe H ) . For t he simu l at ion , t he in pu t fr e-

quency is 35 7 M H z m d t he locked V C O fr equency is

571 M H z. I t is show n t hat t he P L L w i t h T y p e I I char ge

F i g . 6

pump has smaller volt age var iat ion once it is locked.

Exper iment al Result s3 .

F i g u r e 6 s h o w s m e a s u r e d o u t p u t o f t w o P L L s l o c k e d

w i t h 5 0 M H z i n p u t s i g n a l s . F o r b o t h P L L s , t h e m e a -

s u r e d l o c k i n g r a n g e o f V C O * e q u e m y i s f r o m 5÷ 3â 2 t o

8· 0m 0 bM 1 IH 1 zZ . T h e t o t a l p o w e r c o n s u m p t i o n i n c l u d i n g IU / O

bh¢ tud1dì {H&fìh eaw Irm .s i s a b o u t 1B 3· 0 1nm¼n ½W f o r b o t h Pm ILH ¹J¾ILh ¹Ü¤s¥ . T a b l e 1 sm um nm* ½ç -

rnm1n1 aa rn i®z¼ eÄ S t h e P L L c h a r a c t e r i s t i c s . A s s h o w n i n T a b l e 1 .

T ype H PL L with t he new charge pump st ruct ure showsimproved j i t ter charact er ist ics in t he ent i re * equem y

Page 3: |LETTER A New Charge Pump PLL with Reduced Jittertera.yonsei.ac.kr/publication/pdf/Jour_2001_ygkim_TC-01.pdf · A New Charge Pump PLL with Reduced Jitter ~ ... and D N signals are

IEI CE T RA NS. COM M UN -- V O L E84- B , N0 .6 JUNE 20O1

1 6 8 2

Tab le 1 PLL charact erist ics.

ype | TyÚ | |

T e c h n o l o g y O 6-um CM0 S

Supply Vd ¢ e 3 3 V

| Power Consumption | 130 mW

532 - 800 (MHz)LOCKIng Range

| 532MHz

657MHz

800MHz

1 9 03ps

1 1 4 4ps

! 6 9 2ps

1 4 5 9 p s

1 O . 7 1 p s

| 2 1 0 p s

4U t t e r ( r m s )

SOOp¤ / div 4O 53n¤

range and t he improvement is much pronounced at fre-quencies away from t he PLL center frequency Ä ex-

pected . T he j it t er measurement is carr ied out usingTek 11801C digit al sampling osci l loscope by apply ing3.3 V p- p per iodic pulse signals supplied by HP 81101Apulse generator . F igure 7 shows t he measured j it tercharact er ist ics of T ype I (a) and T ype I I (b) PL L at800 M Hz. I t should be not ed t hat t he measured PL Lout put j it t er has a considerable cont r ibut ion from t hesignal source used . T he measured RM S j it t er for t hesignal source alone is 13.8 ps at 41M Hz.

!a) Type I PLL

C o n c l u s i o n4

A new low -j i t t er char ge pum p P L L is r ealized . I n t he

ex per i m ent al resu l t s, t he n ew char ge pu m p P L L has r ed uced j i t t er ch ar act er ist i cs t han t he convent ional st r uc-

t ur e. T his is b ecause t he leakage cu r rent pat hs for t hechar ge pu m p out p ut ar e blocked w hen t he P L L w Älocked . C onseq uent ly , t he char ge p um p ou t p u t vo l t -

ages rem ain st ab le. T he m easur ed P L L R M S j i t t er isÄ m uch a 28% leg t h an t hat of t he P L L w i t h a p rev i -

ously repor t ed ch arge pu m p st r uct ur e. T he new ch argepum p P L L can be usefu l fo r im p lem ent ing h igh-sp eed

and low£ t t er cl ock d at a recover y (C D R ) ci rcui t s-

Fig. 7 PLL output j it ter characterist ics (f w vf vc o = 800MHz).

= 50 MHz,

A c k n o w l e d u n e -m s

T h is wor k w as sup por t ed by t he K or ea R esear ch Fou n-

dat ion . P L L ci rcu i t s were fabr icat ed t hr ough t h e M P W

pr ogr am at I C D esign E ducat ion Cent er ( I D E C ) , K o

r ea .

R e f e r e n c e s

Ì B . Razavi , Monolit hic PhÄ e-Locked Loops and Clock Recovery Circui ts- T heory and Design, IEEE Prs s, 1996.

[2| K hw ani , F . Ssaleh, D. Lee, P R ang, P. Ta, and G. M iller ,°Clock and dat a recovery for 12 5Gb/ s et hernet t ransceiver

i n O3 5 P m C M 0 S ,± P r o c . I E E E 1999 C u st o m I n t eg r a t ed C i r -

c u i t s C o n fer en c e , p p .26 1- 2 6 4 , M ay 199 9 .

Ò M .- S . L ee , T .- S . C h ew . , W .-Y . C h o i , a n d E .e . C h o i , K o

r ea rt P a t en t A p p l i ed , 9S 6 2 13 6 , 19 9 9 .[4 ] S . SM i t-o p a t h s a n d M .A . H o r ow i t z , ° A sem i- d i g i t a l d u a l

d e lay - l o ck ed l o o p ,± I E E E J . So l id - S t a t e C i r c u i t s , v o l .32 ,

n o . 11 , p p . 16 8 3- 169 2 , 19 9 7 .

Ò S .d . K i m , K .- H . L ee , Y .S . M o o n , D .S . h o n g , Y .- H . C h o i -a n d H .- K . L i -n , °u ®W A m * M bw/¥s° /Î pMim n i n t e r fa c e fo r sk ew - t o le r an t

b u s u s i n g low j i t t er P LH ½LLDÂ,c,± I E E E J . So l id - S t a t e C i r cu i t s ,

v o l .3 2 , n o 5 , p p .6 9 16 % , 19 9 7 .¹ M . C o m b s , K . D i m ¤ y , a n d A . G M in er , ° A p o r t a b le c lo ck

m u l t i p l i e r ge n er a t o r usi n g d ig i t a l C M O S st a n d a r d ce l ls,±

I E E E J . So l id - S t a t e C i r c u i t s , v o l .3 1, n o .7 , p p .9 58 - 9 6 5 , 199 6 .