LES BUS NUMERIQUES Bus parallèles

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LES BUS NUMERIQUES Bus parallles. Les bus on-chip. N03_Bus_onchip. LES BUS ON-CHIP Sommaire. Premire partie: Prsentation Deuxime partie: Le bus IBM CoreConnect Troisime partie: Le bus ARM AMBA. LES BUS ON-CHIP 1 ire partie: Prsentation Sommaire - Repre. - PowerPoint PPT Presentation

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  • LES BUS NUMERIQUES

    Bus paralllesLes bus on-chipN03_Bus_onchip

  • LES BUS ON-CHIP

    SommairePremire partie:PrsentationDeuxime partie:Le bus IBM CoreConnect Troisime partie:Le bus ARM AMBA

  • LES BUS ON-CHIP1ire partie: Prsentation Sommaire - ReprePremire partie:PrsentationLes System On Chip (SoC)Spcificits des bus on-chip

  • LES BUS ON-CHIP1ire partie: PrsentationLes System On Chip (SoC)Les technologies des semi-conducteurs voluent trs vites:

  • LES BUS ON-CHIP1ire partie: PrsentationLes System On Chip (SoC)Elles autorisent des densits dintgration normeExemple: En 0.18m, il existe des matrices de 8 millions de portesDfinition dun SoC:Circuit (ASIC/FPGA) intgrant tout ou partie de llectronique requise pour une applicationIntgre gnralement un ou plusieurs processeurs et des priphriquesUn SoC peut tre purement numrique ou mixte

  • LES BUS ON-CHIP1ire partie: PrsentationLes System On Chip (SoC)Architecture dun SoC:Il est possible davoir:Plusieurs bus hautes performancesPlusieurs bus priphriquesLes bus sont coupls par des Bridges

  • LES BUS ON-CHIP1ire partie: PrsentationSpcificits des bus on-chipPourquoi faut-il des bus particuliers pour les SoC?Structures synchronesviter davoir des tats indfinis: Pas de buffers 3 tatsPas de collecteurs ouvertsConsquences:Les bus on-chip comportent beaucoup de lignes et des bus de donnes en criture et en lecture spars2 familles:Matrices de commutation ou crossbarMultiplexeursCe qui existe:VSIA: Organisme multi-industrielsA dfini les principes respecter pour un bus on-chipPlusieurs standards existent:IBM:CoreConnectARM:AMBASonics...

  • LES BUS ON-CHIP2ime partie: Le bus IBM CoreConnect Sommaire - RepreDeuxime partie:Le bus IBM CoreConnect Prsentation gnraleBus PLBBus OPB

  • LES BUS ON-CHIP2ime partie: Le bus IBM CoreConnect Prsentation gnraleBus hautesperformancesPLBBuspriphriquesOPBDevice Control Register bus

  • LES BUS ON-CHIP2ime partie: Le bus IBM CoreConnect Bus PLBLe busEntirement synchroneArchitectures 32 et 64 bits, extensibles 128 et 256 bitsData bus critures et lectures spars, pour:autoriser des transferts simultans hauts dbitsviter les conflits lors des transitions lecture / critureTransferts de bursts de longueur fixe de mots sur 8, 16, 32, 64 bitsBus adresses pipelinGre les interruptions des changesTransferts DMAPas de signaux 3 tatsGestion des mmoires caches (transferts de lignes)Gestion des atomic instructionsSupporte les transferts non alignsLarbitreSupporte jusqu' 16 matres4 niveaux de prioritPhase darbitrage masqu par les transferts de donnes en coursIntgre un mcanisme de re-arbitrage avec watchdog

  • LES BUS ON-CHIP2ime partie: Le bus IBM CoreConnect Bus OPBLe busEntirement synchroneBus adresses 32 bitsBus donnes 32 bitsSupporte les transferts sur 8, 16, 32 bitsDuplication des mots de 8 et 16 bits pour les transferts 8 et 16 bitsSupporte les transfert burstAccepte des transferts de donnes mono-cycles entre un matre et des esclavesLa fonction " Bridge " peut tre matre sur le PLB ou l'OPBPas de signaux 3 tatsLarbitreArbitrage pour jusqu' 4 priphriques matres du bus OPB

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBA Sommaire - RepreTroisime partie:Le bus ARM AMBABus AMBA High performance Bus (AHB)Bus AMBA Peripheral Bus (APB)Comparaison IBM / ARM

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAIntroductionSpcification ARM version 2.0AMBA Advanced Microcontroller Bus ArchitectureBus standard de communications on-chip pour la cration de designs avec microcontrleur(s) enfouis (SOCs).3 bus distincts:AHB: Advanced High-performance BusASB: Advanced System BusAPB: Advanced Peripheral BusExistence dune version AMBA Light

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBADfinitionsMatre AHBInitie une opration de lecture ou dcriture (transfert) en envoyant (vers lesclave) les signaux de contrle, dadresse (signal de slection) et de donnes.Esclave AHBRpond lopration de lecture ou dcriture initie dans son espace dadresses en renvoyant (au matre) un message rponse: Succs (la donne a t bien crite ou bien lue), chec ou attente.Arbitre AHBSassure quun seul matre la fois est autoris effectuer des transferts sur le bus AHB.Dcodeur AHBDcode ladresse lie chaque transfert et active le signal de slection de lesclave ainsi dsign

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBABus AMBA High performance Bus (AHB)MAITRE 3MAITRE 2MAITRE 1ESCLAVE 1ESCLAVE 2ESCLAVE 3ARBITREDECODEURRequteRequteRequteAHB accordAHB accordAHB accordSignal de slectionSlection 3Slection 2Slection 1HADDRHWDATAHRDATA

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Liste des principaux signaux utiliss (1/3)NameSourceDescriptionHCLKClock source Times all bus transfers. All signal timings are related to the Bus clock rising edge of HCLK.HRESETnReset controllerActive LOW and is used to reset the system and the bus. ResetThis is the only active LOW signal.HADDR[31:0]MasterThe 32-bit system address bus. Address busHTRANS[1:0]MasterType of the current transfer, can be NONSEQUENTIAL, Transfer typeIDLE or BUSY.HWRITEMasterHIGH: write transferTransfer direction LOW: read transferHSIZE[2:0]MasterSize of the transfer: byte (8b), halfword (16b) or word (32b) Transfer sizePossibility for larger transfer sizes up to 1024 bitsHBURST[2:0]MasterIndicates if the transfer forms part of a burst. Four, Burst typeeight and sixteen beat bursts are supported and the burst may be either incrementing or wrapping.HPROT[3:0]MasterThe protection control signals provide additional Protection controlinformation about a bus access and are primarily intended for use by any module that wishes to implement some level of protection.

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Liste des principaux signaux utiliss (2/3)NameSourceDescriptionHWDATA[31:0]MasterUsed to transfer data from the master to the bus slaves Write data busHSELxDecoderEach slave has its own slave select signal. Combinatorial Slave selectdecode of the address bus.HRDATA[31:0]SlaveData bus used to transfer data from bus slaves to bus Read data busmasterHREADYSlaveWhen HIGH, indicates that a transfer has finished on the Transfer donebus. This signal may be driven LOW to extend a transfer. Note: Slaves on the bus require HREADY as both an input and an output signal.HRESP[1:0]SlaveAdditional information on the status of a transfer: Transfer responseOKAY, ERROR, RETRY and SPLIT.

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Liste des principaux signaux utiliss (3/3)NameSourceDescriptionHBUSREQxMasterSignal from master x to the bus arbiter. Indicates that the Bus requestthe master requires the bus. There is an HBUSREQx signal for each bus master, up to 16 bus masters.HLOCKxMasterWhen HIGH, indicates that the master requires locked Locked transfersaccess to the bus and no other master should be granted the bus until this signal is LOW.HGRANTxArbiterMaster x has the highest priority master. Ownership of the Bus grantaddress/control signals changes at the end of a transfer when HREADY is HIGH, so a master gets access to the bus when both HREADY and HGRANTx are HIGH.HMASTER[3:0]ArbiterIndicate which bus master is currently performing a Master numbertransfer and is used by the slaves which support SPLIT transfers to determine which master is attempting an access. The timing of HMASTER is aligned with the timing of the address and control signals.HMASTLOCKArbiterCurrent master is performing a locked sequence of Locked sequence transfers. Same timing as the HMASTER signal.HSPLITx[15:0]SlaveUsed by a slave to indicate to the arbiter which masters Split completion(SPLIT-should be allowed to re-attempt a split transaction. Each bit requestcapable)of this split bus corresponds to a single bus master.

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Entres/Sorties dun Matre

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Entres/Sorties dun Esclave

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Entres/Sorties de lArbitre

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Entres/Sorties du Dcodeur

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Transfert simple, sans wait states [W/R]

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Transfert avec wait states

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Les types de transfertHTRANS[1:0]TypeDescription00 IDLENo data transfer required. Used when a bus master is granted the bus, but does not wish to perform a data transfer. Slaves always provide a zero wait state OKAY response. Transfer ignored by the slave.01BUSYAllows bus masters to insert IDLE cycles in the middle of bursts. Indicates that the bus master is continuing with a burst of transfers, but the next transfer cannot take place immediately. When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst. Transfer ignored by the slave. Slaves provide a zero wait state OKAY response.10NONSEQIndicates the first transfer of a burst or a single transfer. Address and control signals unrelated to the previous transfer. Single transfers treated as bursts of 1 -> the transfer type is NONSEQUENTIAL.11SEQRemaining transfers in a burst are SEQUENTIAL. Control information identical to the previous transfer. Address equal to the address of the previous transfer plus the size (in bytes). Wrapping burst: Address of the transfer wraps at the address boundary equal to the size (in bytes) multiplied by the number of beats in the transfer (either 4, 8 or 16).

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Exemples de diffrents type de transfert

  • LES BUS ON-CHIP3ime partie: Le bus ARM AMBAAHB: Les accs burstIncrementing bursts:Accs squentielLadresse de chaque donne du burst est ladresse prcdente