lecture7 - intercomponent busses

7/28/2019 Lecture7 - Intercomponent Busses

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1. SEPTEMBER 2011

NAVN NAVNESEN

INTERCOMPONENT BUSSES

9.OCTOBER 2012

MDL ETIADE 2012

VERSITyUNIMDL ETIADE 2012


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SUBJECTS

SPI

I2C I2C example: LM75 temperature sensor.1-wire

-

9.OCTOBER 2012

MDL ETIADE 2012MDL ETIADE 2012

. I2SCodeVision setup


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SPI (SERIAL PERIPHERAL INTERFACE)

Introduced by Motorola.

Well suited for fast data rates (data streaming).Primitive (no error checks).Addressing multiple slaves extents HW.

9.OCTOBER 2012


.Normally only one master.Multi-master possible, but troublesome.

No speed limit is stated in the standard


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SPI: SHIFT REGISTER BASED

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SPI: MASTER AND SLAVE

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CPOL=clockpolarity

CPHA=clockphase


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SPI SLAVE

SS

SCLK

MOSI MISO

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SLAVES IN PARALLEL

CONFIGURATION

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SLAVES IN SERIAL CONFIGURATION

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SPI PRODUCTS

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MEGA16: SPI INTERFACE

Mega16 has HARDWARE for SPI interface.

Registers:SPI Control Register SPCRSPI Status Re ister SPSR

9.OCTOBER 2012


SPI Data Register SPDR


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I2C (IIC)

Inter IC bus (Introduced by Philips).

Suited for medium data rates.Limited range (often locally at PCB). Inbuild addressing (minor HW demands).

9.OCTOBER 2012


.Real time qualified (respons times can be calculated).Speed 100kbit/s (many devices support up to 400kbit/s)


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I2C TOPOLOGY

Each node has its own uni ue address (or ID).

9.OCTOBER 2012


By sending a START command,

each node isable to become the bus master.


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I2C MASTER: START + ADDRESS

All other nodes now enters a state of listening.

Then the master sends the address of the slave, it

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The address is 7 bits.

The last bit (R/W) informs the slave, whether the master

wants to read or to write.


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I2C SLAVE: ACK

After having received the STARTcammand and the

address, all slaves compares the addresswith their own

address:

* If no address match, the STOP command is awaited.

* If the addressmatches, the slave sends an ACK:

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SDA

SCL

The slave holds SDA low and

generates an SCL -pulse.

- Subsequently the master regains bus control -


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I2C MASTER: SENDS / RECEIVES DATA

1. Master sends data:

9.OCTOBER 2012


During reception (2) the slave controls SDA,but the master controls SCL.

The slave is only allowed to change SDAwhile SCL is high.


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I2C MASTER: ACKAFTER EACH

BYTE RECEIVED

Following each byte received from a slave, the master

MUST send an ACK (except

after

the last byte).

Master sets SDA low and

9.OCTOBER 2012


SCL

generates a clockpulse.Then the slave regains

control over SDA.

Following the last received byte, the master sends the

STOP command (freeing the bus again).


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MASTER: STOP

Sent by the master, when it has finished sending /receiving

data.

9.OCTOBER 2012


Received by all slaves, now knowing the bus is again free.

STOP can be sent at any time (even in the middle of a data

transmission).

In all cases STOP means END of transmission.


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I2C BUS HARDWARE

SCL and SDAare bi-directional.

Open drain => External pull-up necessary!

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RESERVED ADDRESSES

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10-bit addressering is possible (new standard).

In this case 2 bytes are sent as address:

11110AAx + AAAAAAAA.

(8-bit nodes ignores 10-bit addressing).


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I2C BUS ARBITRATION

If a master is unable to set an output high (it always test for this), it looses

the bus control.

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,

Until the yellowmarking, bothmasters think, they own the bus.

ThenCPU2 surrenders (until STOP).


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I2C EXAMPLE: LM75

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LM75: BLOCK DIAGRAM

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LM75 ADDRESS

LM75 is always a slave (not capable of being a master).

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The address(7 bit) is composed

of 4 constant bits and

the external pin settings (A2-A0).


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LM75: TEMPERATURE DATA FORMAT

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2complement format.

LSB = 0,5deg

. Celsius.


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LM75: REGISTER STRUCTURE

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LM75: POINTER REGISTER

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LM75: TEMPERATURE REGISTERS

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MDL ETIADE 2012


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LM75: CONFIGURATION REGISTER

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MDL ETIADE 2012


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LM75: I2C TIMING, 2 BYTE READING

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MDL ETIADE 2012


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LM75: I2C TIMING, 1 BYTE READING

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LM75: I2C TIMING

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MEGA16: I2C INTERFACE

Mega16 has HARDWARE for I2C interface.This is called the Two Wire Serial Interface.

Dedicated pins for SDA and SCL.

Registers:

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TWI Control Register TWCRTWI Status Register TWSRTWI Data Register TWDR

TWI (Slave) Address Register TWAR


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CODEVISION: I2C LIBRARY

CodeVision comes with a library for interfacing I2Cdevices (uses BIT BANGING).

Any port pins can be used.

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CODEVISION: I2C LIBRARY

FUNCTIONS

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CODEVISION: LM75 LIBRARY

CodeVision comes with a library for interfacing the I2Cdevice LM75 (uses BIT BANGING).

Any port pins can be used.

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CODEVISION: LM75 LIBRARY

FUNCTIONS

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1-WIRE

Introduced by Dallas Semiconductor corp.Only 1 wire (+ground + optionally power).

Cheaper than I2C.Only suited for low data rates.Limited range (often locally at the PCB).

9.OCTOBER 2012


.

See good presentation at:

http://www.maximintegrated.com/products/1-wire/flash/overview/index.cfm


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1 WIRE TOPOLOGY

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Notice the inbuild capacitor (800pF).

Possibility ofmany slaves.


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1-WIRE: SEQUENCE OF INITIALIZING

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Master sends the RESET pulse.

All slaves responds by sending a Presence Pulse.

This tells the master, that at least one slave is present and ready to

communicate. But the master will not know if several slaves are

connected


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1-WIRE:WRITE

To write a 1, themaster pulls the line

low and releases itagain. After 15s theslave will read the bus

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.To Write a 0, themaster keeps the linelow for 60s

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1-WIRE: READ

To read a bit, the master pulls the line lowand releases it. If the slave keeps it low

after 15s it means 0, if the slave releasesit, it means 1

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1-WIRE: IN GENERAL

Normal sequence:

1. Master sends RESET and awaits Presence Pulse.

2. Master sends an 8-bit read command.

3. Master reads one or more bytes from the slave.4. Often, the last byte will be CRC, only to be used if desirable.

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Each slave has its own unique 64 bit address.

This can be searched by the master (complex algorithm).


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DS1820: 1-WIRE TEMPERATURE

SENSOR

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DS1820 TEMPERATURE REGISTER

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DS1820: ALARM REGISTERS

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DS1820: POWER

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S 820 OM CO


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DS1820: ROM CODE

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DS1820 MEMORY MAP


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DS1820: MEMORY MAP

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DS1820 SEQUENCE OF


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DS1820: SEQUENCE OF

TRANSACTIONS

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DS1820 COMMANDS


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DS1820: COMMANDS

ROM Commands:

FunctionCommands:

The bus master uses a ROM command to address the DS18S20 with which it

wishes to communicate,

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MEGA16 1 WIRE INTERFACE


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MEGA16: 1-WIRE INTERFACE

Mega16 has NO HARDWARE for 1-wire interface.But CodeVision comes with has a 1-wire library.

This library uses bit banging (any port pin can be used).

9.OCTOBER 2012


, -

(many timing requirement to be met).

CODEVISION 1 WIRE LIBRARY


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CODEVISION: 1-WIRE LIBRARY

9.OCTOBER 2012


CODEVISION: DS1820 LIBRARY


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CodeVision comes with a library for interfacing the 1-wire device DS1820 (uses BIT BANGING).Any port pin can be used.

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FUNCTIONS

9.OCTOBER 2012


I2S


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I2S

Inter-IC SoundOnly used for digital audio streaming (as far as I know)Streaming from master to slaveNo feedback from slave to master at all

9.OCTOBER 2012


Multiple slaves can be connected in parallel and listento the streamSupported by almost all audio ADC/DACs and mostdigital signal processors

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I2S


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I2S

I2S consists of three wires:- Word clock-Bit clock-Data

9.OCTOBER 2012


44.1kHz

The bit clock is 64 times word clock

Normally there are 24 or 32 bits per. channel and twochannels per word.

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I2S TIMING


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I2S TIMING

From the ADMP441 datasheet

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CODEVISION SETUP


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CODEVISION SETUP

Create a new project.

Select No to the

question about using

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z r v

project

CODEVISION SETUP


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CODEVISION SETUP

Add your *.c files. If you

have not written them

yet, they can be

created using

file>new>source

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this dialog

CODEVISION SETUP


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CODEVISION SETUP

Go to C compiler.

Select yourmicrocontroller

(Mega16) and your clock(3,6864MHz for STK500)

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CODEVISION SETUP


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CODEVISION SETUP

Go to After Build

Select Program the Chip

PressOK

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CODEVISION SETUP


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CODEVISION SETUP

Press programmer settings

and select your COM-port

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lecture7 - intercomponent busses

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