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19.9.2011 1 Lecture 7 VHDL (Part-2) Concurrent and Sequential Statements, Loops Concurrent vs Sequential Statements Concurrent statements – Simple signal assignment statement – Conditional signal assignment statement – Selected signal assignment statement Sequential Statements – VHDL process – Sequential signal assignment statement – Variable assignment statement – If statement – Case statement – Simple for loop statement 2

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Page 1: Lecture 7 VHDL (Part-2) - Computer Engineering at ... 7 VHDL (Part-2) Concurrent and Sequential Statements, Loops ... Concurrent vs Sequential VHDL Modeling Style Location inside architecture

19.9.2011

1

Lecture 7

VHDL (Part-2)Concurrent and Sequential Statements, Loops

Concurrent vs Sequential Statements

Concurrent statements– Simple signal assignment statement– Conditional signal assignment statement– Selected signal assignment statement

Sequential Statements– VHDL process– Sequential signal assignment statement– Variable assignment statement– If statement– Case statement– Simple for loop statement

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Concurrent vs Sequential VHDL

Modeling Style

Location inside architecture inside process

Example statements process, component instance, concurrent signal assingment

if, for, switch-case, signalassignment

3

CONCURRENT SIGNAL ASSIGNMENT STATEMENT

Section 1

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Architecture body

Simplified syntax

5

Simple Signal Assignment

Syntax:signal_name <= projected_waveform;

– E.g., y <= a + b + 1 after 10 ns;

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Examples

E.g.,– status <= '1';– even <= (p1 and p2) or (p3 and p4);– arith_out <= a + b + c - 1;

Implementation of last statement

7

Conditional signal assignment statement

Syntax

signal_name <= value_expr_1 when boolean_expr_1 elsevalue_expr_2 when boolean_expr_2 elsevalue_expr_3 when boolean_expr_3 else. . .

value_expr_n

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E.g., 4-to-1 mux

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E.g., 4-to-2 priority encoder

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Conceptual representation

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Examples

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ALU

E.g.,

13

SEQUENTIAL SIGNAL ASSIGNMENT STATEMENTS

Section 2

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Sequential vs. Concurrent

architecture x of entity isdeclarationbeginconcurrent statement;concurrent statement;process()

beginsequential statement;sequential statement;end

concurrent statement;process()

beginsequential statement;sequential statement;end

end x;

sequential!

concurrent

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Conceptual implementation

Concurrentstatement

ProcessSequential statement;Sequantial statement;

…

Concurrentstatement

Concurrentstatement

ProcessSequential statement;Sequantial statement;

…

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VHDL Process

Contains a set of sequential statements to be executed sequentiallyThe whole process is a concurrent statementCan be interpreted as a circuit part enclosed inside of a black box

Two types of process– A process with a sensitivity list– A process with wait statement entity

P1P2

P3a_v

tmp_vP4tmp_v

archprocess

signalvariable

port

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A process with a sensitivity list

Syntaxprocess(sensitivity_list)

declarations;

begin

sequential statement;

sequential statement;

. . .

end process;

A process is like a circuit part, which can be

– active (known as activated) – inactive (known as

suspended).A process is activated when a signal in the sensitivity list changes its valueIts statements will be executed sequentially until the end of the process

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Example

E.g, 3-input and circuitsignal a,b,c,y: std_logic; process(a,b,c)begin

y <= a and b and c;end process;

How to interpret this: process(a)begin

y <= a and b and c;end process;

For a combinational circuit, all input should be included in the sensitivity list

19

Sequential Signal Assignment Statement

Syntax signal_name <= value_expression;

Syntax is identical to the simple concurrent signal assignment

Caution:– Inside a process, a signal can be assigned multiple times, but only

the last assignment takes effect

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Examples

E.g., process(a,b,c,d)

Begin y <= a or c;

y <= a and b;

y <= c and d;

end process;

It is same as process(a,b,c,d)

begin

y <= c and d;

end process;

21

IF statement

Syntax

if boolean_expr_1 thensequential_statements;

elsif boolean_expr_2 thensequential_statements;

elsif boolean_expr_3 thensequential_statements;

. . .else

sequential_statements;end if;

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E.g., 4-to-1 mux

23

Comparison to conditional signal assignment

Two statements are the same if there is only one output signal in if statementIf statement is more flexibleSequential statements can be used in then, elsif and else branches:

– Multiple statements– Nested if statements

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Incomplete branch and incomplete signal assignment

According to VHDL definition:

– Only the “then” branch is required; “elsif” and “else” branches are optional

– When a signal is unassigned due to omission, it keeps the “previous value” (implying “memory”)

25

Incomplete branch

E.g., It implies

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Incomplete branch (cont’d)

Fix

27

Incomplete signal assignment

E.g.,

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Fixes

29

Conceptual implementation

Same as conditional signal assignment statement if the if statement consists of

– One output signal – One sequential signal assignment in each branch

Multiple sequential statements can be constructed recursively

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Case statement

Syntax

case case_expression iswhen choice_1 =>

sequential statements;when choice_2 =>

sequential statements;. . .when choice_n =>

sequential statements;end case;

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E.g., 4-to-1 mux

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Comparison to selected signal assignment

Two statements are the same if there is only one output signal in case statement

Case statement is more flexible

Sequential statements can be used in choice branches

33

Incomplete signal assignment

According to VHDL definition:– When a signal is unassigned, it keeps the “previous value” (implying

“memory”)

34

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Fixes

35

Conceptual implementation

Same as selected signal assignment statement if the case statement consists of

– One output signal – One sequential signal assignment in each branch

Multiple sequential statements can be constructed recursively

36

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Simple for loop statement

VHDL provides a variety of loop constructs

Only a restricted form of loop can be synthesized

Syntax of simple for loop: for index in loop_range loop

sequential statements;end loop;

loop_range must be static

Index assumes value of loop_range from left to right

37

Loops: example

Hardware:add_i: for i in 0 to max_c-1 generate

b(i) <= a(i) + i;end generate add_i;

Generates <max_c> parallel computation units

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E.g., bit-wide xor

39

Conceptual implementation

“Unroll” the loop For loop should be treated as “shorthand” for repetitive statementsE.g., bit-wise xor

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E.g., reduced-xor

41

Summary

Concurrent vs. sequential statement

Concurrent– simple assignment– selected assignment– conditional assignment

Sequential– Processes– If statement– Case statement– Loop statement

42


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