lecture 5 computer hardware. von neumann architecture
TRANSCRIPT
Lecture 5
Computer Hardware
von Neumann Architecture
Secondary Storage - The Disc Drive
The Very Simple Computer
Half Adder
a b
s
c
HalfAdder
a b
c s
a b
s
c
HalfAdder
a b
c s
a b
s
c
a b
s
c
HalfAdder
a b
c s
HalfAdder
a b
c s
Full Adder
N-Bit Adder
Ripple-Carry Adder
S-R Latch and D-Type Flip Flop
Register Transfer
The Fetch - Execute Cycle
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Running the VSC
Running the VSC
enEXE
MARMEM1LAT
ACC2LAT
1PCPC
04IRMAR
MARMEMIR
PCMAR
][
:
][
Fetch-Execute Cycle Timing Diagram
Control UnitExecuting OpCodes
LDAen - load ACC enable - moves value in LAT1 into ACC
STAen - store ACC enable - moves value in ACC into MEM[MAR]
ADDen - ADD enable
CMPen - CMP (1's complement) enable - takes the bitwise inverse of LAT1
BNNen - if(ACC7 = 0) then PC = IR<4:0>
SHLen - shift-left enable
SHRen - shift-right enable
HLTen - halts the fetch-execute cycle by setting
ControlUnit
IR
Arithmetic Logic Unit
Programming the VSC
addr label instruction addr machine code .
0 LDA A 00000 00000100
1 ADD B 00001 01000101
2 STO C 00010 00100110
3 HLT 00011 11111111
4 A 24 00100 00011000
5 B 30 00101 00011110
6 C 0 00110 00000000
Types of Multiprocessors
SISD - Single Instruction - Single DataSIMD - Single Instruction - Multiple DataMISD - Multiple Instruction - Single DataMIMD - Multiple Instruction- Multiple Data
