lecture #19: combinational logic design review lecture.pdf · based on lecture notes by dr. eric m....
TRANSCRIPT
University of Florida Joel D. Schipper ECE Department Summer 2007
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LECTURE #19: Combinational Logic Design Review EEL 3701: Digital Logic and Computer Systems
Based on lecture notes by Dr. Eric M. Schwartz Important Design Techniques and Methods for Combinational Logic 1: SOP & POS 2: K-Maps (MSOP & MPOS) 3: MUX’s 4: PLA & PAL (PLDs) 5: ROM
6: VHDL POS & SOP Example: Given a Truth Table, determine the equation in POS format.
Truth Table A B C D F 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1
))()()(( DCBADCBADCBADCBAFPOS ++++++++++++= Boolean Algebra: Combining the 1st and 2nd term => )( CBA ++ Combining the 2nd and 3rd term => )( DCA ++ Combining the 2nd and 4th term => )( DCB ++
))()(( DCBDCACBAFMPOS ++++++= Draw the resulting circuit:
University of Florida Joel D. Schipper ECE Department Summer 2007
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K-Maps Using the Truth Table on the previous page, solve the MSOP.
AB\CD 00 01 11 10 00 0 0 1 1 01 1 0 1 1 11 1 1 1 1 10 1 0 1 1
CDBDAABFMSOP +++= Draw the resulting circuit: MUX’s From the Truth Table, K-Map, or Equation, implement the design using a 4-to-1 MUX.
CDBDAABFMSOP +++= Assigning C and D to select lines. - When C=0 and D=0 => A+B - When C=0 and D=1 => AB - When C=1 and D=0 => 1 - When C=1 and D=1 => 1
University of Florida Joel D. Schipper ECE Department Summer 2007
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PAL & PLA Given the equation, show the connections within a PAL and PLA.
CDBDAABFMSOP +++=
PAL (Programmable Array Logic)
PLA (Programmable Logic Array)
XX
X X
X X
X
AD'AB
BD' C
C
F
BA
D
X
A
X X X
X
XX
X
X
X
XBC
D
AB BD' CAD'0
0
1
2
3
2 3 41
F
University of Florida Joel D. Schipper ECE Department Summer 2007
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ROM Use a ROM to implement the Truth Table from the first page. => You must use a 2K x 8 EPROM consisting of eight 256-byte address blocks. => Important data is already stored in lower 75% of the memory. 2K addresses = 211 => 11 address lines
75% of 2K = 1.5k => Addresses 010 to 153510 010 => 000 0000 0000 153510 => 101 1111 1111
We have 4 inputs, so we want 16 contiguous addresses in a single block:
Start: 000 0000 0000 256 Bytes End: 000 1111 1111 UsedStart: 001 0000 0000 256 Bytes End: 001 1111 1111 UsedStart: 010 0000 0000 256 Bytes End: 010 1111 1111 UsedStart: 011 0000 0000 256 Bytes End: 011 1111 1111 UsedStart: 100 0000 0000 256 Bytes End: 100 1111 1111 UsedStart: 101 0000 0000 256 Bytes End: 101 1111 1111 UsedStart: 110 0000 0000 256 Bytes End: 110 1111 1111 Start: 111 0000 0000 256 Bytes End: 111 1111 1111
We will be using the last 4 address bits for our inputs, therefore, we have 2
available blocks with 4 remaining address bits: 2 x 24 = 32 possible starting address.
Let’s pick 110 0000 0000 as our starting address.
VHDL: To be discussed next lecture. VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Aside: Other important acronyms VLSI = Very Large Scale Integration
ASICs = Application Specific Integrated Circuits