Layout Tutorial for Lab 3: Automated Design, Synthesis, and Layout

We wont be doing the layout of each cell ourselves. Instead we will be using “black box cells“. The black boxes are provided by CMC and TSMC (CMC provides access to the materials and TSMCs fabrication facility). The black box cells are place holders (look them up in the library manager when you get the chance) and will be filled in by CMC when the design is submitted for fabrication (something we wont be doing). Instead we are going to use First Encounter (a cadence tool) to do the following:

• Floor planning, • Place and route,• Power distribution • Clock distribution.

Once we are done we will have a prototype layout for our verilog module that can be sent to CMC for fabrication (once they replace the black boxes with the real cells).

Note: Unfortunately, First Encounter is not quite ready for full use (I.e. not everything works yet). There are some licensing problems and the design flow hasn’t been completely worked out yet (There are a few work arounds but they aren’t that easy to implement). However, in the near future First Encounter will become the tool of choice (if it isn’t already) for industry and graduate students so it’s probably a good idea to be familiar with it.

The layout lab is a continuation of the synthesis work you did last week. Therefore, we will need the synthesised version of your signed serial multiplier. This example will use the synthesized decoder from the previous tutorial.

Make sure you have a saved copy of your synthesized module (if necessary run design analyzer again). It is best to save a version of your synthesized module in a separate directory

1. In your lab3 directory create a new directory called FE. This directory will hold all your encounter files

Open a terminal console>cd ELEC4708> cd lab3>mkdir FE

2. Now we want to save a copy of your synthesized module in a new directory but first we need to make a directory to save it to.

>cd FE>mkdir synthesized

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Now we need to run design analyzer as before (see tutorial for part 2 of lab 3. Make sure your in the right directory) and add a new step at the end as follows:

3. Go back to the top level of the hierarchy. Save the design using File-->Save As. Save the file in the "Synthesized" directory with file name "decoder.v". Make sure you save it as file type "Verilog", and save the full hierarchy.

4. Now we can start encounter. In a terminal console make sure that you are in the FE directory and type

>encounterYou should see the following window

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5. Before we go any further you need to make a new directory. Open a new terminal window

>cd ELEC4708>cd lab3>cd Femkdir FE_libs

6. Now we need to get a few files. They should all be on the course web page. So, lets open a web page. Go back to the terminal window and type

>netscape

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go to the following URL: www.doe.carleton.ca/~bmorshed/ELEC4708/

Find the FE_libs files on the web page (under lab 3) and copy all the files to your FE_libs directory (the one you just made).

There are 12 files 6 .lef files (they provide encounter with technology information) and 6 .tlf files (they provide all the timing information).

7. In encounter we now need to import the design that we saved in the synthesized directory. Go to “Design” pull down menu then select “Design Import”, and fill in the pop-up window as shown below (modify the file locations to suit where your files are saved). Note that under the advanced tab you must fill in the “POWER” and “IPO/CTS” windows as shown below.

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Don’t forget to click on Generate Footprint Based on Functional Equivalence.

Click ok, this may take some time to load all the information. You should eventually get the following screen or something similar.

8. We can now see the initial floor plan (dominates most of the window) and the module in the bottom left of the window (the decoder is very small and doesn’t take up much room in the module view).

9. The next step is to specify the floor plan. We need to leave enough space so that the router will be able to place all the metal interconnects but not so much that we waste space. We also want to have a large enough space for any buffers that might be needed during optimization. A decent number for core utilization is somewhere between 0.5 and 0.7 (we will use 0.7 in this case since the decoder does not have a lot of cells).

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We also need to decide how much space we want to leave around the core. Keep in mind that we want to add our power rings so we might need something like 25 or 100 microns of space. (for the decoder we will use 25 microns)

From the encounter window select the “Floorplan” drop down menu and then “Specify Floor-plan”. Fill in the resultant pop up window as shown.

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click “OK”. The encounter window should now look like this

We can see that the chip has been divided into three sections. You can play around with some of the Floorplan numbers to get different sizes, size ratios, core boundary sizes, etc.

10. Now is probably a good time to save your work. It’s also probably a good idea to save often. Select the “Design” pull down menu and then “Save Design”. You can restore a saved design by going to the “Design” pull down menu and selecting “Restore Design”.

11. We can now add the power rings around the core. Open the power rings window as shown below.

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12. Make the power lines 5 microns wide and use Metal 6 for top and bottom and metal 5 for left and right. Click on “Update”. Set an offset of 1 micron. Click “OK”. The width of the power lines is determined (somewhat) by the size of the chip. A much bigger design would need wider lines.

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The encounter window should now look like this.

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13. Now we need to add power stripes. Open the power stripes window as shown below

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In the add stripes form select Metal 6 and make it 5 microns wide. click on “Update”. Select number of sets and set it to 1 (this design is small, so we only need one power strip. You might need more). Set “X from left” to 9 (it’s near the bottom of the form. It places the power stripe in the centre of the design.). Make sure the form looks like this:

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14. At this stage we can add the rest of the routing for power but unfortunately we either don’t have the appropriate license and/or the function doesn’t seem to work. Most people recom-

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mend we use Special Route to do the final power routing but wrout can also do the job (nano-route as well).

15. We can now place our cells. Go to the “Place” pull down menu then “Standard Cells and Blocks”. You should get the following form:

The default settings should be fine. Click on “OK”.

16. To see the cells we just placed click on the “Physical View” button in the upper right hand cor-ner of the encounter window.

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17. Now we need to make sure that the power nets are specified. select the “Floorplan” drop down menu and then “Connect Global Nets”. Fill in for both VSS and VDD as shown. Click on “Add to List” to add them to the list on the left hand side. Make sure “Apply All” is checked (for both VDD and VSS). The window should look as follows.

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18. Click on “Apply”, then “Check”. Make sure there are no errors (check the host terminal for errors).

19. At this stage we need to insert a clock tree but the decoder doesn’t have a clock. Therefore I will switch to a more complex circuit that has a clock (This will also give you an opportunity to see what a larger circuit looks like). I will be using a Biquad IIR filter.

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Notice that the filter is much larger than the decoder, its approximately 500 x 500 microns (the decoder is approximately 20 x 20 microns). There are hundreds of cells as opposed to the decoder which has 11. Also the power rails are much wider 20 microns for the rings and the stripes are 10 microns (the stripes are also in metal 2).

20. Lets make a clock tree. First we need to make a specification file. Go to the “Clock” pull down menu and select “Create Clock Tree Spec”. Fill in the form as follows:

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21. We will use the default file (The file can be edited to meet your needs). Click on “OK“.

22. Go to the “Clock” pull down menu and select “Specify Clock Tree”.

Make sure that the file is the one you just created and click “OK”.

23. We can now create the clock tree. Go to the “Clock” pull down menu and select “Synthesize Clock Tree”. Accept the default values and click “OK”.

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24. We can now do a timing optimization based on the clock tree we just made. Go to the “Tim-ing” pull down menu and select “Optimization”.

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Make sure “Post-CTS” is selected and click “OK”.

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25. We are finally ready to route our design. To do this we will use Nanoroute (there are several options but this is probably the best). Go to the “Route” pull down menu and select “Nano-route” then select “Route”.

We will use the default values. Click on “OK”.

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Since we don’t have pads in our design the tool routes the inputs and outputs to the periphery of the floor plan (the idea is that they can then be connected to other blocks hierarchically)

26. We can now do an optimization of our layout with wires included. Go to the “Timing” pull down menu and select “Optimization”.

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Make sure “Post-Route” is selected and click “OK”.

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It will be difficult to see any changes in the layout so check the terminal window which should show a summery of changes.

Note: I got a lot of N/A and 0 s time intervals in the terminal window summery so I’m not sure if the function is working properly. On the other hand this is a correct method of doing things.

27. This is a good time to add empty filler cells to the design. Go to the “Place” pull down menu select “Filler” then “Add”. Make sure the form is filled in as below and click “OK”.

The encounter window should now look something like this

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28. Under the “Verify” pull down menu there are several verification functions. Use the default values and try the “Verify Geometry” and Verify Connectivity”. Once you have run both select the “Violation Browser” from the “Verify” pull down menu.

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29. Correct any errors that you find.

Hints: • Some routing errors are due to insufficient space. A solution is to make the chip

area larger • You can ignore any VSS or VDD errors as they are probably due to that routing

issue I mentioned earlier.

30. There are several report tools that you can use. Go to the “Tools“ drop down menu then select “Summary Report”.

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From the summary report GUI you can select a text and/or HTML report similar to this:

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31. You can also use the design browser (located under the tools pull down menu) to locate the individual cells, module, nets, etc.Select the design browser according to the following picture under the “tools” pull down menu.

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32. The following picture shows the results browser and the selected module in red in the encoun-ter window.

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33. We have gone through a simplified design flow. There are many options that we haven’t had a chance to explore. It might be a good idea to take a look at some of the available options. like RC extraction or the various routing options.

Generally the last step in a design flow is to send a completed design to the fabrication facility. To do this the design is exported to a GDS2 file. To generate a GDS2 file we need a map file that relates layer names to numbers. Go to the “Design” pull down menu select “Save” and then “GDS”.

Name the output stream file anything you want (should be related to what the design is) with the gds2 extension. Make sure the map file is “streamOut.map” and the “GDS Structure Name” is the name of your layout. click “OK”.

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34. Congratulations, you have now completed the tutorial for a simplified First Encounter design flow.

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