large-scale sfq switches using miniaturized 2$\,\times\,$2 switch cell

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1790 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 18, NO. 4, DECEMBER 2008 Large-Scale SFQ Switches Using Miniaturized 2 2 Switch Cell Takahiro Nakagawa, Yoshihito Hashimoto, Yoshio Kameda, Shinichi Yorozu, Mutsuo Hidaka, and Kazunori Miyahara Abstract—We have developed a miniaturized 2 2 switch cell, a key component of single-flux-quantum switches. The cell was opti- mized using a full-custom design approach instead of our conven- tional cell-based design approach. The cell contains 74 Josephson junctions, and its power consumption is 16.8 W. Its area is signif- icantly reduced to 160 m 200 m, which is 69% smaller than our conventional cell-based switch. We fabricated test chips using our 2.5-kA/cm Nb standard process and confirmed a 40-GHz op- eration with a bias margin of 8.5% by an on-chip test. We also designed 4 4 and 8 8 cross-bar switches using the 2 2 switch cells. The 40-GHz operation of the 4 4 switch was confirmed with a bias margin of 4% by an on-chip test. The full function of the 8 8 switch was also confirmed with a bias margin of 5% at a low-frequency (10 kHz). The area of these switches was re- duced to about half of that of our conventional switches. We dis- cussed large-scale switches using our advanced high- multilayer process. We estimated that area of a 32 32 switch designed for the advanced process are reduced by 83% compared to a switch designed for the standard process. Index Terms—Cell-based design, miniaturization, passive trans- mission line (PTL), single-flux-quantum (SFQ), switch. I. INTRODUCTION S INGLE-FLUX-QUANTUM (SFQ) circuits operate at clock frequencies higher than 10 GHz with very low power consumption [1]. One promising application of SFQ circuits is the high-speed network switch, which we have been developing [2]–[4]. So far, we developed a 4 4 switch and demonstrated it up to 40 GHz [4]. Recently, we have begun an investigation of the design approach for miniaturizing switch circuits in order to realize compact large-scale switches [5]. Since any switch can be realized by connecting a 2 2 switch cell array, miniaturization of 2 2 switches is very effective Manuscript received March 26, 2008; revised May 11, 2008. Current ver- sion published December 04, 2008. This work was supported by the New En- ergy and Industrial Technology Development Organization (NEDO) Supercon- ductors Network Device Project, and by the Next-Generation High-Efficiency Network Device Project. This paper was recommended by Associate Editor O. Mukhanov. T. Nakagawa is with Toshiba Corporation, Kanagawa 212-8583, Japan, and also with Creare B-302, Tokyo 183-0043, Japan (e-mail: [email protected]; [email protected]). Y. Hashimoto is with NEC Corporation, Kanagawa, Japan, and also with the International Superconductivity Technology Center, Ibaraki 305-8501, Japan. Y. Kameda is with NEC Corporation, Device Platform Research Laboratory, Kanagawa 229-1198, Japan. S. Yorozu is with NEC Corporation, Nano Electronics Research Laboratory, Ibaraki 305-8501, Japan. M. Hidaka is with International Superconductivity Technology Center, Ibaraki 305-8501, Japan. K. Miyahara is with Tokyo Denki University, Chiba 270-1382, Japan. Digital Object Identifier 10.1109/TASC.2008.2007273 for miniaturizing large-scale switches. We therefore have devel- oped a miniaturized 2 2 switch cell. Fig. 1 shows a micropho- tograph of an 8 8 cross-bar switch chip, which was designed and fabricated using the 2 2 switch cell. In our previous work [3], [4], switches were designed using our conventional cell-based design approach [6]. This approach enables easy designing of any logic circuit. However, cell-based circuits tend to occupy a large area, which is the result of two problems. 1) Circuits are implemented by combining prim- itive-function cells such as AND, NOT, etc.; and 2) simple cells consisting of a few junctions (Josephson transmission lines (JTLs), splitters, etc.) produce empty area because the minimum cell size is defined as 40 m 40 m. We therefore designed a compact 2 2 switch cell as a new element in our standard cell library [6]. We did this by optimizing the cell’s circuit diagram and layout instead of designing it by combining primitive-function cells. This approach is aimed at minimizing the circuit area and the number of Josephson junctions (JJs). Using the miniaturized cell, we also designed 4 4 and 8 8 cross-bar switches. We compared these switches with conven- tional cell-based switches to verify the effectiveness of our design approach. Circuits were fabricated and demonstrated using our 2.5-kA/cm Nb standard process (SDP) [7]. In addition, we discussed large-scale switches designed for our advanced high- multilayer process (ADP) [8]. II. MINIATURIZATION OF 2 2SWITCH CELL A. Design of 2 2 Switch Cell Fig. 2 shows a circuit diagram and a state diagram of the 2 2 switch cell. The switch cell consists of two 2 : 1 multiplexers (MUXs). The switch cell has two inputs (in1 and in2), two out- puts (out1 and out2), and two control signals (cross and bar). The switch cell has two states: “cross” and “bar.” If the con- trol signal cross is applied, the switch’s state becomes “cross.” Then, the SFQ pulses applied to in1 and in2 are routed to out2 and out1, respectively. On the other hand, if the control signal bar is applied, the switch’s state becomes “bar.” Then, the SFQ pulses applied to in1 and in2 are routed to out1 and out2, re- spectively. We designed the switch cell to maintain its states even if the SFQ pulses are applied to in1 or in2. Moreover, we designed the switch cell to properly operate independent of the mutual timing between in1 and in2. These efforts were made to realize proper switch function. We placed passive transmission line (PTL) drivers and PTL receivers [9], [10] onto the input and output ports of the 2 2 switch cell so that the switch cell could be directly connected with the PTLs. Therefore, large-scale switches can be realized merely by connecting the switch cells with the PTLs. 1051-8223/$25.00 © 2008 IEEE

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Page 1: Large-Scale SFQ Switches Using Miniaturized 2$\,\times\,$2 Switch Cell

1790 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 18, NO. 4, DECEMBER 2008

Large-Scale SFQ Switches Using Miniaturized2 2 Switch Cell

Takahiro Nakagawa, Yoshihito Hashimoto, Yoshio Kameda, Shinichi Yorozu, Mutsuo Hidaka, andKazunori Miyahara

Abstract—We have developed a miniaturized 2 2 switch cell, akey component of single-flux-quantum switches. The cell was opti-mized using a full-custom design approach instead of our conven-tional cell-based design approach. The cell contains 74 Josephsonjunctions, and its power consumption is 16.8 W. Its area is signif-icantly reduced to 160 m 200 m, which is 69% smaller thanour conventional cell-based switch. We fabricated test chips usingour 2.5-kA/cm� Nb standard process and confirmed a 40-GHz op-eration with a bias margin of 8.5% by an on-chip test. We alsodesigned 4 4 and 8 8 cross-bar switches using the 2 2 switchcells. The 40-GHz operation of the 4 4 switch was confirmed witha bias margin of 4% by an on-chip test. The full function ofthe 8 8 switch was also confirmed with a bias margin of 5%at a low-frequency (10 kHz). The area of these switches was re-duced to about half of that of our conventional switches. We dis-cussed large-scale switches using our advanced high- multilayerprocess. We estimated that area of a 32 32 switch designed forthe advanced process are reduced by 83% compared to a switchdesigned for the standard process.

Index Terms—Cell-based design, miniaturization, passive trans-mission line (PTL), single-flux-quantum (SFQ), switch.

I. INTRODUCTION

S INGLE-FLUX-QUANTUM (SFQ) circuits operate atclock frequencies higher than 10 GHz with very low

power consumption [1]. One promising application of SFQcircuits is the high-speed network switch, which we have beendeveloping [2]–[4]. So far, we developed a 4 4 switch anddemonstrated it up to 40 GHz [4]. Recently, we have begun aninvestigation of the design approach for miniaturizing switchcircuits in order to realize compact large-scale switches [5].

Since any switch can be realized by connecting a 2 2 switchcell array, miniaturization of 2 2 switches is very effective

Manuscript received March 26, 2008; revised May 11, 2008. Current ver-sion published December 04, 2008. This work was supported by the New En-ergy and Industrial Technology Development Organization (NEDO) Supercon-ductors Network Device Project, and by the Next-Generation High-EfficiencyNetwork Device Project. This paper was recommended by Associate EditorO. Mukhanov.

T. Nakagawa is with Toshiba Corporation, Kanagawa 212-8583,Japan, and also with Creare B-302, Tokyo 183-0043, Japan (e-mail:[email protected]; [email protected]).

Y. Hashimoto is with NEC Corporation, Kanagawa, Japan, and also with theInternational Superconductivity Technology Center, Ibaraki 305-8501, Japan.

Y. Kameda is with NEC Corporation, Device Platform Research Laboratory,Kanagawa 229-1198, Japan.

S. Yorozu is with NEC Corporation, Nano Electronics Research Laboratory,Ibaraki 305-8501, Japan.

M. Hidaka is with International Superconductivity Technology Center,Ibaraki 305-8501, Japan.

K. Miyahara is with Tokyo Denki University, Chiba 270-1382, Japan.Digital Object Identifier 10.1109/TASC.2008.2007273

for miniaturizing large-scale switches. We therefore have devel-oped a miniaturized 2 2 switch cell. Fig. 1 shows a micropho-tograph of an 8 8 cross-bar switch chip, which was designedand fabricated using the 2 2 switch cell.

In our previous work [3], [4], switches were designed usingour conventional cell-based design approach [6]. This approachenables easy designing of any logic circuit. However, cell-basedcircuits tend to occupy a large area, which is the result of twoproblems. 1) Circuits are implemented by combining prim-itive-function cells such as AND, NOT, etc.; and 2) simplecells consisting of a few junctions (Josephson transmissionlines (JTLs), splitters, etc.) produce empty area because theminimum cell size is defined as 40 m 40 m. We thereforedesigned a compact 2 2 switch cell as a new element in ourstandard cell library [6]. We did this by optimizing the cell’scircuit diagram and layout instead of designing it by combiningprimitive-function cells. This approach is aimed at minimizingthe circuit area and the number of Josephson junctions (JJs).Using the miniaturized cell, we also designed 4 4 and 8 8cross-bar switches. We compared these switches with conven-tional cell-based switches to verify the effectiveness of ourdesign approach. Circuits were fabricated and demonstratedusing our 2.5-kA/cm Nb standard process (SDP) [7]. Inaddition, we discussed large-scale switches designed for ouradvanced high- multilayer process (ADP) [8].

II. MINIATURIZATION OF 2 2 SWITCH CELL

A. Design of 2 2 Switch Cell

Fig. 2 shows a circuit diagram and a state diagram of the 2 2switch cell. The switch cell consists of two 2 : 1 multiplexers(MUXs). The switch cell has two inputs (in1 and in2), two out-puts (out1 and out2), and two control signals (cross and bar).The switch cell has two states: “cross” and “bar.” If the con-trol signal cross is applied, the switch’s state becomes “cross.”Then, the SFQ pulses applied to in1 and in2 are routed to out2and out1, respectively. On the other hand, if the control signalbar is applied, the switch’s state becomes “bar.” Then, the SFQpulses applied to in1 and in2 are routed to out1 and out2, re-spectively. We designed the switch cell to maintain its stateseven if the SFQ pulses are applied to in1 or in2. Moreover, wedesigned the switch cell to properly operate independent of themutual timing between in1 and in2. These efforts were made torealize proper switch function.

We placed passive transmission line (PTL) drivers and PTLreceivers [9], [10] onto the input and output ports of the 2 2switch cell so that the switch cell could be directly connectedwith the PTLs. Therefore, large-scale switches can be realizedmerely by connecting the switch cells with the PTLs.

1051-8223/$25.00 © 2008 IEEE

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NAKAGAWA et al.: LARGE-SCALE SFQ SWITCHES USING MINIATURIZED 2 2 SWITCH CELL 1791

Fig. 1. Microphotograph of 8� 8 cross-bar switch chip. Chip size is 5 mm� 5mm.

Fig. 2. (a) Circuit diagram and (b) state diagram of 2� 2 switch cell.

Fig. 3. Microphotograph of new 2� 2 switch cell.

We designed the 2 2 switch cell layout by connecting twoMUXs with JTLs and splitters. The MUX was basically thesame as the one we previously reported [5]. In this work, how-ever, we modified the positions of the input/ouput ports of theoriginal MUX cell [5] and optimized the 2 2 switch cell layoutto minimize the cell area. Fig. 3 shows a microphotograph of the2 2 switch cell. The switch cell contains 74 JJs, and its powerconsumption is 16.8 W. The circuit area is 160 m 200 m.The bias margin of the switch cell in the simulation was 18.2%at our target frequency of 40 GHz.

We compared the 2 2 switch cell (Fig. 3) with a 2 2switch circuit (Fig. 4) designed using our conventional design

Fig. 4. Pattern layout of conventional 2� 2 switch circuit designed by com-bining primitive-function logic cells.

TABLE ICOMPARISON OF NEW 2� 2 SWITCH CELL WITH CONVENTIONAL 2� 2

SWITCH CIRCUIT

Fig. 5. Microphotograph of on-chip test circuit for 2� 2 switch cell.

approach. The conventional 2 2 switch was implementedby combining library cells (four nondestructive read-outs(NDROs), two confluence buffers, two PTL drivers, four PTLreceivers, JTLs, and splitters). Compared with the conventional2 2 switch circuit (Fig. 4), the circuit area, the number of JJs,and the power consumption of the 2 2 switch cell (Fig. 3)were reduced by 69%, 49%, and 63%, respectively (Table I).

B. Experimental Result of 2 2 Switch Cell

We used the on-chip test method [11], [12] to demonstratehigh-speed operation of the 2 2 switch cell. Fig. 5 shows amicrophotograph of the 2 2 switch cell with its on-chip testcircuit. This circuit consists of two 8-bit input shift registers(SRs), two 8-bit output SRs, and a high-frequency clock gener-ator (HFCG). We connected the 2 2 switch and the SRs usingthe PTLs.

The procedure of the on-chip test method is as follows. First,a test pattern is written into two 8-bit input SRs at a low fre-quency of 10 kHz with a pulse pattern generator at room temper-ature. Then, eight high-frequency clock pulses are generated byapplying trigger to the HFCG. The eight high-frequency clock

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1792 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 18, NO. 4, DECEMBER 2008

Fig. 6. Waveforms of on-chip test for 2� 2 switch cell. Rising edge and fallingedge in output waveform represent logic value 1.

Fig. 7. Measured frequency dependence of bias margin for 2� 2 switch cell.

pulses read out the data stored in the input SRs, and the 2 2switch cell operates with the high-frequency data. Output of the2 2 switch cell is stored in the output SRs. Finally, the datastored in the output SRs is read out at low frequency.

To realize 40-GHz operations, the timings of the clock anddata have to be optimized at the input ports of the output SRswith ps-order accuracy. We optimized the signal timings by in-serting a 14-JJ JTL into the clock path between the input andoutput SRs, as shown in Fig. 5. Moreover, the delay of the 14-JJJTL can be changed. We call such JTLs variable delay lines(VDLs). We used the 14-JJ VDL in order to compensate for thetiming variation due to process variation. The delay of the VDLcan be independently tuned within 12.5 ps, which covers a40-GHz clock period, by changing its bias current from 3.8 to4.6 mA.

The on-chip test circuit contains 741 JJs, and its power con-sumption is 208.1 W. The circuit area is 1.0 mm 3.0 mm.The signal timings were optimized by tuning the delay of theVDL. We have confirmed proper operation of the 2 2 switchcell at 40 GHz. Fig. 6 shows a waveform of the on-chip test. Thebias margin of the cell was 8.5% at 40 GHz. Fig. 7 shows thefrequency dependence of the bias margin for the 2 2 switchcell.

III. DESIGN AND DEMONSTRATION OF LARGE-SCALE

SWITCHES

In the next step, we designed and tested 4 4 and 8 8cross-bar switches using the miniaturized 2 2 switch cell.

Fig. 8. (a) Circuit diagram and (b) microphotograph of 4� 4 switch.

A. 4 4 Cross-Bar Switch

Fig. 8 shows a circuit diagram and a microphotograph of the4 4 switch. The 4 4 switch was designed by connecting16 2 2 switch cells with PTLs and splitters, as shown inFig. 8(b). The 4 4 switch has four inputs (in1–in4), fouroutputs (out1–out4), a bar input, and 16 cross inputs (c11–c44).The procedure for setting the routing paths of the 4 4 switchis as follows. First, the states of all 2 2 switches are set to“bar” by applying the bar signal. Second, the states of fourswitch cells are changed into “cross” from “bar” by applyingthe cross signals to four switch cells individually. For example,if cross signals c13, c22, c34, and c41 are applied, routingpaths in1-out3, in2-out2, in3-out4, and in4-out1 are realized.The switch contains 1309 JJs, and its power consumption is0.32 mW. The circuit area is 0.84 mm 1.76 mm.

Fig. 9 shows a circuit diagram and a microphotograph of anon-chip test circuit for the 4 4 switch. The test circuit con-sists of the 4 4 switch, four 8-bit input SRs, four 8-bit outputSRs, an HFCG, and two 8-bit serial-to-parallel (S/P) converters.The on-chip test circuit contains 3381 JJs, and its power con-sumption is 0.94 mW. The delay of the 4 4 switch dependson the routing path. The longest path is in1-out4, which con-tains seven switch cells, as shown in Fig. 8(a). The shortest pathis in4-out1, which contains only one switch cell. We thereforeadjusted the signal timings by inserting different-length VDLsinto each data path, as shown in Fig. 9(a), for the 40-GHz opera-tion. The estimated delay of the 4 4 switch including the VDLdelays is about 450 ps. The delays of the VDLs can be adjustedby changing their bias currents. We can, therefore, compensatefor the timing variation due to process variation.

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NAKAGAWA et al.: LARGE-SCALE SFQ SWITCHES USING MINIATURIZED 2 2 SWITCH CELL 1793

Fig. 9. (a) Circuit diagram and (b) microphotograph of on-chip test circuit for4� 4 switch.

Fig. 10. Circuit diagram of S/P converter.

There is a pin-neck problem in testing large-scale switches.This problem is caused by the quadratic increase of the numberof cross inputs (the number of cross inputs is . Here, isswitch capacity). To solve this problem, we used S/P converters.Fig. 10 shows a circuit diagram of an S/P converter. The S/P

Fig. 11. Waveforms of on-chip test for 4� 4 switch. Input signals of S/P con-verters (cross, spclk, sptrg) are left out.

Fig. 12. Measured frequency dependence of bias margin for 4� 4 switch.

converter consists of D2FFs1 and wiring cells (JTLs and split-ters). It has a data input (din), a clock input (clk), and a triggerinput (trg). By applying clk and din, serial data are stored ineach D2FF. All the stored data are read out simultaneously inparallel by applying trg. The 4 4 switch has 16 cross inputs.We reduced the number of pins from 16 (16 parallel cross in-puts) to 6 (two 8-bit serial cross inputs, two spclk inputs, andtwo sptrg inputs) by using two 8-bit S/P converters, as shown inFig. 9(a).

We have confirmed full operation of the 4 4 switch at40 GHz. Fig. 11 shows one waveform of the on-chip test. InFig. 11, we first applied c11, c22, c33, and c44 and realizedthe routing paths of in1-out1, in2-out2, in3-out3, and in4-out4.Second, we applied c14, c23, c32, and c41 and realized pathsof in1-out4, in2-out3, in3-out2, and in4-out1. Fig. 12 shows themeasured frequency dependence of the bias margin of the 4 4switch. The margin was 4% at 40 GHz, as shown in Fig. 12.

B. 8 8 Cross-Bar Switch

The 8 8 switch was designed by connecting 64 2 2switch cells with PTLs and splitters. The 8 8 switch has eightinputs (in1–in8), eight outputs (out1–out8), a bar input, and 64cross inputs. The routing path of the 8 8 switch is controlledby the same procedure as the 4 4 switch (apply eight crossinputs after applying bar). The 8 8 switch contains 5217 JJs,and its power consumption is 1.25 mW. The circuit area is1.64 mm 4.16 mm.

1[Online]. Available: http://pavel.physics.sunysb.edu/RSFQ/Lib/d2.html

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1794 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 18, NO. 4, DECEMBER 2008

Fig. 13. Circuit diagram of 8� 8 switch.

We designed a test chip by connecting the 8 8 switch andfour 16-bit S/P converters using PTLs (Fig. 13). The longestPTL used in the chip is 9.6 mm. With four 16-bit S/P converters,the 64 cross inputs were reduced to six inputs (four 16-bit serialcross inputs, a clk input, and a trg input). A microphotograph ofthe chip was already shown in Fig. 1. The chip contains 7475 JJs,and its power is 1.93 mW.

The 8 8 switch requires a large bias current of 501.7 mA.We divided the 8 8 switch into four blocks. Each block con-tains 16 switch cells and is biased separately. There are two ad-vantages in our switch design. First, concentration of the biascurrent, which may induce harmful magnetic field, is avoided.Second, the bias current of each circuit block can be tuned indi-vidually so that variation of the operating bias, which may occurdue to process variation and/or a large bias current, can be com-pensated. Moreover, we placed ground pads next to the pads forlarge bias supply (four switch biases, each about 125 mA, andfour S/P converter biases, each about 60 mA) to enable differ-ential biasing, effective for reducing the influence of the returncurrent [13], [14].

Fig. 14 shows one waveform of the test. We have confirmedfull operation of the 8 8 switch at a low-frequency (10 kHz)with a bias margin of 5%.

IV. DISCUSSION

To verify how much of an advantage our design approachhas over the conventional approach, we designed layouts of4 4, 8 8, and 16 16 switches using conventional 2 2switches (Fig. 4). We also designed layouts of a 16 16 switchusing miniaturized 2 2 switch cells for comparison. Theseresults are summarized in Table II. The circuit size was reducedto about half the size of our conventional switches, and thenumber of JJs and the power consumption were reduced by47% and 60%, respectively. The results show that our designapproach is effective for realizing compact and low-powerlarge-scale switches.

However, the ratio of PTL area to switch area is more than60%, and it increases with switch capacity, as shown in Fig. 15.Thus, an advantage of our miniaturized 2 2 switch cell cannotbe fully taken. This problem is caused by the device structure ofSDP [7] in which 2 2 switch cells and PTLs have to be placed

Fig. 14. Low-frequency experiments of 8� 8 switch. First, paths of in1-out1,in2-out2, in3-out3, in4-out4, in5-out5, in6-out6, in7-out7, and in8-out8 wererealized. Second, paths of in1-out8, in2-out7, in3-out6, in4-out5, in5-out4, in6-out3, in7-out2, and in8-out1 were realized.

TABLE IICOMPARISON OF NEW SWITCHES WITH CONVENTIONAL SWITCHES

Fig. 15. Ratio of PTL area to switch area.

in the same layer. This problem can, therefore, be solved byusing the ADP. The ADP we are developing has nine Nb wiring

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NAKAGAWA et al.: LARGE-SCALE SFQ SWITCHES USING MINIATURIZED 2 2 SWITCH CELL 1795

Fig. 16. Comparison of high-� multilayer process version switches with cur-rent process version switches.

Fig. 17. (a) Circuit diagram and (b) pattern layout of 64� 64 switch designedusing high-� multilayer process.

layers and uses 10-kA/cm JJs [8]. If using ADP, 2 2 switchcells and PTLs are placed in respective layers. Additionally, thewidth of the PTL can be reduced to 5 m from 37 m. Fig. 16shows results of a comparison between switches using SDP andADP. Areas of switches using ADP are significantly reduced

by over 60% compared to the SDP. The advantage of ADP in-creases as switch capacity becomes large (ex. area of the 32 32switch is reduced by 83% compared to SDP). As an example oflarge-scale switches using ADP and a miniaturized 2 2 switchcell, we designed a layout of 64 64 cross-bar switch (Fig. 17).The switch contains 331 769 JJs, and its power consumption is79.4 mW. The circuit area is 10.75 mm 12.8 mm.

V. CONCLUSION

We miniaturized a 2 2 switch cell towards realization oflarge-scale SFQ switches. The area of the miniaturized cell wassignificantly reduced by 69% compared to our conventional2 2 switch. We also designed 4 4 and 8 8 switches usingthe 2 2 switch cells. We confirmed the full operation ofthese switches. The areas of the 4 4 and 8 8 switches werereduced to about half of those of our conventional switches.Results show that our design approach is very effective forminiaturizing large-scale switches. We also have shown thatthe advantage of our miniaturized 2 2 switch cell can be fullytaken by using ADP.

ACKNOWLEDGMENT

The authors would like to thank the members of SRL/ISTECfor their help with the circuit fabrication technology.

REFERENCES

[1] K. K. Likharev and V. K. Semenov, “RSFQ logic/memory family: Anew Josephson junction technology for sub-terahertz clock frequencydigital systems,” IEEE Trans. Appl. Supercond., vol. 1, no. 1, pp. 3–28,Mar. 1991.

[2] S. Yorozu, Y. Kameda, Y. Hashimoto, H. Terai, A. Fujimaki, and N.Yoshikawa, “Process of single flux quantum packet switch technology,”IEEE Trans. Appl. Supercond., vol. 15, no. 2, pp. 411–414, Jun. 2005.

[3] Y. Kameda, S. Yorozu, and Y. Hashimoto, A New Automatic Place-ment and Routing Design Technology for Large-Scale Single-Flux-Quantum Logic Circuits Sydney, Report PMo18, Jul. 2003, ExtendedAbstracts of ISEC2003.

[4] Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, and N.Yoshikawa, “Implementation of a 4� 4 switch with passive intercon-nects,” IEEE Trans. Appl. Supercond., vol. 15, no. 2, pp. 356–359, Jun.2005.

[5] T. Nakagawa, Y. Hashimoto, Y. Kameda, S. Yorozu, and K. Miyahara,“Design and demonstration of high-functionality logic cells for minia-turization of SFQ switches,” Physica C, vol. 463–465, pp. 1076–1079,2007.

[6] S. Yorozu, Y. Kameda, H. Terai, A. Fujimaki, T. Yamada, and S.Tahara, “A single flux quantum standard logic cell library,” Physica C,vol. 378–381, pp. 1471–1474, 2002.

[7] S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, “A 380 ps, 9.5mW Josephson 4-Kbit RAM operated at a high bit yield,” IEEE Trans.Appl. Supercond., vol. 5, no. 2, pp. 2447–2452, Jun. 1995.

[8] S. Nagasawa, K. Hinode, T. Satoh, H. Akaike, Y. Kitagawa, and M. Hi-daka, “Development of advanced Nb process for SFQ circuits,” PhysicaC, vol. 412–414, pp. 1429–1436, 2004.

[9] S. V. Polonsky, V. K. Semenov, and D. F. Schneider, “Transmissionof single-flux-quantum pulses along superconducting microstrip lines,”IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 2598–2600, Mar. 1993.

[10] Y. Hashimoto, S. Yorozu, Y. Kameda, A. Fujimaki, H. Terai, and N.Yoshikawa, “Development of passive interconnection technology forSFQ circuits,” IEICE Trans. Electron., vol. E88-C, no. 2, pp. 198–207,Feb. 2005.

[11] F. Kirichenko, O. A. Mukhanov, and A. Ryzhikh, “Advanced on-chiptest technology for RSFQ circuits,” IEEE Trans. Appl. Supercond., vol.7, no. 2, pp. 3438–3441, Jun. 1997.

[12] T. Yamada, A. Sekiya, A. Akahori, H. Akaike, A. Fujimaki, H.Hayakawa, Y. Kameda, S. Yorozu, and H. Terai, “On-chip test of theshift register for high-end network switch based on cell-based design,”Supercond. Sci. Technol., vol. 14, no. 12, pp. 1071–1074, 2001.

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1796 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 18, NO. 4, DECEMBER 2008

[13] H. Terai, Y. Kameda, S. Yorozu, A. Fujimaki, and Z. Wang, “The ef-fects of dc bias current in large-scale SFQ circuits,” IEEE Trans. Appl.Supercond., vol. 13, no. 2, pp. 3–28, Jun. 2003.

[14] A. M. Kadin, R. J. Webber, and S. Sarwana, “Effects of supercon-ducting return currents on RSFQ circuit performance,” IEEE Trans.Appl. Supercond., vol. 15, no. 2, pp. 280–283, Jun. 2005.

Takahiro Nakagawa received the M.S. degree in information environmentfrom Tokyo Denki University, Japan, in 2008. From 2005 to 2008, he studiedsuperconducting single-flux-quantum circuits at Superconductivity ResearchLaboratory, International Superconductivity Technology Center, Ibaraki, Japan.

He is currently working on semiconductor RF analog IC design at ToshibaCorporation, Kanagawa, Japan.

Mr. Nakagawa is a Member of the Institute of Electronics, Information andCommunication Engineers.

Yoshihito Hashimoto received M.S. degree in physics from Tohoku University,Sendai, Japan, in 1992.

In 1992, he joined NEC Corporation where was engaged in the research of su-perconductor electronics. From 2000 to 2001 he worked as a Visiting ResearchScientist at State University of New York at Stony Brook. From 2002 to 2008 hewas temporarily transferred to the Superconductivity Research Laboratory as aResearch Scientist. He is currently working on optical interconnection at NanoElectronics Research Laboratories, NEC Corporation.

Mr. Hashimoto is a member of the Institute of Electronics, Information andCommunication Engineers of Japan and the Japan Society of Applied Physics.

Yoshio Kameda received the M.S. degree in computer science from Tokyo In-stitute of Technology, Japan, in 1996, and the Ph.D. degree in advanced inter-disciplinary studies from the University of Tokyo, Japan, in 1999.

In 1999, he joined NEC Corporation, where he has been engaged in the re-search of superconducting electronics and systems and CAD tools. From 2002to 2007, he was a member of Superconductivity Research Laboratory, Inter-national Superconductivity Technology Center, Ibaraki, Japan. He is currentlyworking on semiconductor digital circuit design in NEC.

Dr. Kameda is a Member of the Institute of Electronics, Information andCommunication Engineers.

Shinichi Yorozu received his M.S. and Ph.D. degrees in applied physics fromthe University of Tokyo in 1990 and 1993, respectively.

In 1993, he joined NEC Corporation, where he was engaged in the researchof superconducting electronics and systems. From 1997 to 1998, he worked asa Visiting Research Scientist at State University of New York at Stony Brook.From 2002 to 2005, he was temporally transferred from NEC to ISTEC as a Re-search Scientist. Since 2005, he has been a Senior Manager of Nano ElectronicsLaboratories, NEC Corporation.

Dr. Yorozu is a member of Physical Society of Japan and the Japan Societyof Applied Physics.

Mutsuo Hidaka was born at Miyazaki in Japan. He received the M.E. degreein applied physics from Kyushu University in 1982. He also received the Ph.D.degree in 1998 in electronics engineering from the University of Tokyo.

He joined NEC Corporation in 1982, where he worked on various researchprojects on superconducting digital electronics. He was at Arizona State Uni-versity as a visiting scientist, from 1990 to 1991. In 2002, he temporarily trans-ferred to ISTEC, where he has been working on the research and developmentof Nb-based single flux quantum (SFQ) circuits.

Dr. Hidaka is a member of the Institute of Electronics, Information, and Com-munication Engineers, and the Japan Society of Applied Physics.

Kazunori Miyahara received the B.S. and M.S. degrees in electrical commu-nications engineering from University of Electrical Communications, Tokyo,Japan, in 1973 and 1975, respectively, and the Dr. degree in electrical engi-neering from Tohoku University, Sendai, Japan, in 1979.

He joined Electrical Communication Laboratory NTT in 1979, where he hasbeen engaged in research on Josephson integrated circuits. From 1998 to 2002,he researched superconducting single flux quantum circuits at Superconduc-tivity Research Laboratory ISTEC. Since 2003, he has been with the Departmentof Information Environment, Tokyo Denki University, where he is currently aProfessor.

Dr. Miyahara is a member of the Institute of Electronics, Information andCommunication Engineers of Japan and Japan Society of Applied Physics.