k22 - assistenza apple · sch,k22,mlb power sequencing block diagram mcp standard decoupling mcp...

TABLE_TABLEOFCONTENTS_ITEM


3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

81. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

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THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

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NOTICE OF PROPRIETARY PROPERTY:

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12APPDCK

DESCRIPTION OF REVISION




















































































TABLE_TABLEOFCONTENTS_HEAD


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DRAWING


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K22

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0000774858A

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PRODUCTION RELEASED 2009-08-21

LAST_MODIFIED=Thu Aug 20 17:40:45 2009

LAST_MODIFIED=Thu Aug 20 17:40:45 2009

K51MCP CURRENT AND VOLTAGE SENSE45 54 12/08/2008

MASTERCPU/MXM CURRENT AND VOLTAGE SENSE44 53 N/A

MASTERSMBUS CONNECTIONS43 52 N/A

MASTERLPC+SPI Debug Connector4251 N/A

MASTERSMC Support4150 N/A

MASTERSMC4049 N/A

MASTERInternal USB Connections3947 MASTER

MASTEREXTERNAL USB CONNECTORS3846 N/A

MASTERSATA Connectors3745 N/A

MASTERFIREWIRE CONNECTOR3643 N/A

MASTERFW: 1394B MISC3542 N/A

MASTERFireWire LLC/PHY (XIO2213B)3441 N/A

MASTERETHERNET CONNECTOR3339 N/A

MASTEREthernet Support3238 N/A

K51Ethernet PHY (RTL8211CL)31 37 12/08/2008

MASTERPCI-E Wireless Connector30 34 N/A

K51DDR3 SUPPORT AND BITSWAPS29 33 10/13/2008

MASTERDDR3 SO-DIMM CONNECTOR B28 32 N/A

MASTERDDR3 SO-DIMMs 0 & 227 31 N/A

MASTERMEMORY CAPS26 30 N/A

MASTERFSB/DDR3 Vref Margining25 29 MASTER

MASTERSB Misc24 28 N/A

MASTERMCP Graphics Support23 26 N/A

K5122 25 12/08/2008

MASTER21 22 N/A

MASTERMCP HDA & MISC2021 N/A

MASTERMCP SATA & USB1920 N/A

MASTERMCP PCI & LPC1819 N/A

MASTERMCP Ethernet & Graphics1718 N/A

MASTER1617 N/A

MASTERMCP MEMORY CNTRL & MISC1516 N/A

MASTERMCP Memory Interface1415 N/A

MASTER1314 N/A

MASTEReXtended Debug Port (XDP)1213 N/A

MASTERCPU POWER, GND, DECAPS1112 N/A

MASTERCPU TEST & MISC.1011 N/A

MASTERCPU FSB9 N/A

MASTERSIGNAL ALIASES8 9 N/A

MASTERUNUSED SIGNAL ALIAS7 8 N/A

MASTERHOLES & STANDOFFS6 7 N/A

MASTERPower Conn / Alias5 6 N/A

MASTERBOM Configuration4 4 N/A

MASTERPower Block Diagram3 3 N/A

MASTERSystem Block Diagram2 2 N/A

K22/K23 ICT/FCT87110

MASTER

N/A

K22/K23 RULE DEFINITIONS86109

MASTER

N/A

K22/K23 SPECIFIC CONSTRAINTS85108

MASTER

N/A

GRAPHICS CONSTRAINTS84107

MASTER

N/A

SMC Constraints83106

MASTER

N/A

FireWire Constraints82105

MASTER

N/A

Ethernet Constraints81104

MASTER

N/A

MCP Constraints 280103

MASTER

N/A

MCP Constraints 179102

MASTER

N/A

Memory Constraints78101

MASTER

N/A

CPU/FSB Constraints77100

MASTER

N/A

DisplayPort Connector76 94

MASTER

N/A

DISPLAYPORT SUPPORT75 93

MASTER

N/A

DP MUX SUPPORT74 91

MASTER

N/A

INTERNAL DISPLAY73 90

MASTER

MASTER

LCD MUX & CHOKES72 89

MASTER

MASTER

MXM ALIASES71 87

MASTER

N/A

MXM PCIE CAPS70 86

MASTER

N/A

MXM I/O69 85

K51

10/31/2008

MXM PCIe, DP & Power84

K51

10/31/2008

1V8 POWER SUPPLY67 80

MASTER

N/A

1V1 S5 POWER SUPPLY66 79

K51

10/31/2008

S3 & S0 FETs6578

MASTER

N/A

FSB VTT/3.3V S5 SUPPLIES6476

MASTER

N/A

1.5V DDR SUPPLY6375

MASTER

N/A

MCP CORE REGULATOR6274

MASTER

N/A

5V_S3 REGULATOR6173

MASTER

N/A

VREG: PPVCORE_S0_CPU6072

MASTER

N/A

VREG: PPVCORE_S0_CPU5971

MASTER

N/A

PGOOD and Power Sequencing5870

MASTER

N/A

5769

K51

12/08/2008

AUDIO: Mikey5668

SKIPAUDIO

06/01/2009

AUDIO: Detects/Grounding5567

SKIPAUDIO

06/01/2009

Audio: MLB to I/O Conn.54 66

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP53 65

SKIPAUDIO

06/01/2009

AUDIO: SPEAKER AMP52 64

SKIPAUDIO

06/01/2009

AUDIO: FILTER/BUFFER51 63

SKIPAUDIO

06/01/2009

AUDIO: CODEC/REGULATOR50 62

SKIPAUDIO

06/01/2009

SPI ROM49 61

K51

12/08/2008

CPU FAN48 57

MASTER

N/A

HD AND OD FAN47 56

MASTER

N/A

(.csa) Date

Contents SyncPageThermal Sensors46 55

MASTER

N/A

ABBREV=DRAWING

TITLE=K22

MASTERTable of Contents1 1 N/A

Page(.csa) Date

SyncContents

SCH,K22,MLB

POWER SEQUENCING BLOCK DIAGRAM

MCP Standard Decoupling

MCP Power & Ground

MCP PCIe Interfaces

MCP CPU Interface

10

68

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:


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INTERNAL

J9410

PORTCONN

FW643

MXM CONNECTOR

64-Bit

XDP CONNPG 10

MEMORY

PG 15

LPC+SPI CONN

PG 56,57

PG 51

PG 53

PG 55

U4900

J3100, J3200

PG 31,32

PG 61

PG 49

J4780

PG 47

PG 20

27

11

J4720

PG 21

SATA-A0

LVDS OUT

U3900

PG 39

PG 37

PG 17

Mini PCI-E

ConnAirPort

J3400

U4100

PG 43

PG 41

GPIOs

PG 34

PG 18

DP OUT

DVI OUT

RGB OUT

TMDS OUT

J8400

HDMI OUT

65

84

13

CLK

PG 13

SYNTH

J5100Ser

PrtADC

SMCBSBB,0

SPI

U1000

U1300

PG 13

PG 20

SATA-A1

E-NET

MAGNETICS

ConnFireWire

J4300

CPU DIE

CPU HEATSINKMXM - GPU DIE

TEMP SENSORS

J5600, J5601, J5700

PG 19

Boot ROM

PG 21

Port80,serial

PG 21

Bluetooth

PWR

U1400

CTRL

PG 84

PG 45

J4510

HD

SATA1.05V/3GHZ.

1.05V/3GHZ.

Conn

SATA

ODDConn PG 45

J4520

PG 94DISPLAY

J9002

PG 90

DISP

INTEL CPU

LCD TEMP

LPC

DDR3-1067MHZ

MAIN

3.X GHZ

LGA775 - WOLFDALEPG 10-12

4 SO-DIMMs

MCP7A

PG 47

IR

J4700

PG 47

CAMERA

PG 47

J47xx

WHICH PORT?

EXTERNAL J4610,4620,4630,4640

ConnectorsUSB

PG 47

SD CARD

SPIU6100

MiscPG 24

USB

(UP TO 12 DEVICES)

910

Fan

MCP DIE

AMBIENT INTAKE

HARD DRIVEOPTICAL DRIVE

MCP HEATSINK

FAN CONN AND CONTROL

POWER SENSE

FSB INTERFACE

GPU HEATSINK

TEMP, CURRENT SENSE

POWER SUPPLY

1333 MHZ

FSB

DIMM

NVIDIA

SATA

UP TO 20 LANES3

X16 PCI-E

T3900

PG 39

ConnsAudio

U3700 Audio

U6201

Mikey

U6806

Codec

PG 19

PCI

0

RGMII

PCI-E

SMBMIKEY

HDA(UP TO FOUR PORTS)

DIMM’s

PG 18

E-NET

SpeakerAmps

U6400, U6500

GB

RTL8211CLGR

Line InInt/Ext MicsHeadphones

J6600,J6601,J6602,J6603

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<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_DATE=N/ASYNC_MASTER=MASTER

System Block Diagram




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PAGE 6

MXM20" INVERTER

CPU_CORE

PAGE 76

PPVTT_S0_FSB

PM_SLP_S3

CPU_AVDD

DDR3 MAIN MEMORYPPVCORE_CPU

PAGE 71-72

PAGE 74

MCP, CPU FSB (VTT)

MCP_PLLCPU_VCCP

PP1V8_S0_REG

MCP

PP1V1_S5

SMBUS

PAGE 78

PPDDR_S3_REGPP5V_S3_REG CAMERA

MEM_VTT

AP PCIE

AUDIO

20" PANEL24" PANEL

FANS

MCP_ENET

FW

AP

ETHERNET

PAGE 78

USB

PP12V_S0

MCP

PAGE 76

BT

HDD

20" PANEL

PP12V_S5

CLOCK

PAGE 38

PP1V2_S3

PAGE 75

PP1V5_S0

PP0V75_S0

ENET

PAGE 75

PM_SLP_S3_OD12V_S5

MAIN MEMORY

MCP79 MEM

TEMP SENSOR

CONTROL

PP12V_S0_INVPP12V_S0_HDD

HARD DRIVE

PAGE 79

PP5V_S0

IR

BOOT ROM

AC/DC POWER SUPPLY

PAGE 76

MCP_CORE

DCM/FCM

PAGE 80OPTICAL

MCP_VDD_AUXC

MXM

PAGE 74

P5VS0_EN

FIREWIRE PORTS

AUDIO

PPMCPCORE_S0_REG

MXM

FW

PP3V3_S3

P3V3S3_EN

P3V3S0_EN

PP3V3_S0

PAGE 78

AUDIO

PAGE 42

PP1V_S5

SMCPP3V3_S5_REG

3 OF 110

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Power Block Diagram

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM


PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM




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TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

BOM GROUPS

ALTERNATES

MCP -D SKU DOES NOT

SIGNAL

SIGNAL

BOARD STACK-UP

POWER

SIGNALTOP

32 GROUND

POWER

SIGNAL

BOTTOM

4567 GROUND

MCP -J SKU HAS INTEGRATED GPU

COMMON

K22 PARTS

(338S0563 - BLNK)

BOM Variants

CPUS

4 OF 110

051-7845

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COMMON,ALTERNATE,MCP7A,XDP,BETTER,MCP_ISL9563A,MLB_PNL_PWR,PRODUCTION

WLF,SLGU9,PRQ,2.80G,65W,1066,R0,2M,LGA

337S3807

337S3766

337S3745

337S3742

337S3726

337S3715

337S3727

WLF,SLB9K,PRQ,3.16G,65W,1333,E0,6M,LGA

WLF,SLB9L,PRQ,3.33G,65W,1333,E0,6M,LGA



CPU

PCBA,MLB,DEV,K22607-4426 DEVELOPMENT,DEV_GROUP

K22,2P80GHZ_2M_CPU,BASIC,MXM,K22_MXMPCBA,2.8 GHZ-2M CPU,MXM,K22639-0393

K22,2P80GHZ_2M_CPU,BASIC,IGPCBA,2.8 GHZ-2M CPU,IG,K22639-0392

K22,2P80GHZ_CPU,BASIC,MXM,K22_MXMPCBA,2.8 GHZ CPU,MXM,K22639-0036

2P80GHZ_2M_CPU337S3804 CRITICAL1 CPU

CPU1 3P06GHZ_CPUCRITICAL

CPU

CRITICAL

3P16GHZ_CPU

2P93GHZ_CPU

CRITICAL

CRITICAL

K22,2P80GHZ_CPU,BASIC,IG

K22,3P33GHZ_CPU,BASIC,MXM,K22_MXM






639-0324 PCBA,MLB,3.16GHZ,MXM,K22

639-0206 PCBA,MLB,3.33GHZ,IG,K22

630-9878 PCBA,MLB,CTO,K22

639-0037 PCBA,3.0 GHZ CPU,IG,K22

PCBA,3.06 GHZ CPU,IG,K22(Investigation)639-0183

639-0186 PCBA,2.93 GHZ CPU,MXM,K22 K22,2P93GHZ_CPU,BASIC,MXM,K22_MXM

639-0184 PCBA,2.93 GHZ CPU,IG,K22 K22,2P93GHZ_CPU,BASIC,IG

PCBA,MLB,3.33GHZ,MXM,K22639-0207

SYNC_MASTER=MASTER SYNC_DATE=N/A

BOM Configuration

630-9768 PCBA,MLB,GOOD,K22

825-7122 MLB LABEL,48.0X4.8 X14 CRITICAL1

CRITICAL1 WLF,QXXX,QS,2.80G,65W,1066,R0,3M,LGA 2P80GHZ_CPU

2P83GHZ_CPUWLF,SLB9J,PRQ,2.83G,65W,1333,E0,6M,LGA1 CRITICALCPU

DEV_GROUP XDP_CONN,LPCPLUS,VREFMRGN,MCP_PWR_SENSE,MCP_CPU_TDIODE,PECI_SMB,MOJOMUX 1 U4900 CRITICAL341T0168 IC,SMC,K22 K22

IC,XIO2211ZAY,1394B,167BGA338S0765 U41001 CRITICAL

IC,MCP,MCP7A-DA,B03,35X35MM,BGA1437,DT1 MXM338S0732 U1400

127S0060 C6211127S0111 AUDIO, NEED QUAL

CPU1 3P0GHZ_CPUWLF,SLB9J,PRQ,3.0G,65W,1333,E0,6M,LGA

PCBF,K22,MLB MLB11820-2494 K22

U3700 CRITICAL1 IC,RTL8251CA,GIGE TRANSCEIVER, 48P TQFP338S0694

341T0170 1 CRITICALU6100IC,EFI BOOTROM,K22/K23

IC,GMCP,MCP7A-JA,B03,35X35MM,BGA1437,DT1338S0731 IGU1400

SCH,K22,MLB SCH1051-7845 1 K22

BOOT_MODE_USER,MEMRESET_HW,MEMRESET_MCPMCP7A

BASIC

CRITICAL1 CPU

CRITICAL1

CRITICAL 3P33GHZ_CPU1 CPU




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D

G S

D

IN

G S

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IN




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ON IN RUN AND SLEEP

SILKSCREEN:4

518-0352

ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)PLACE AT J600.

"S5" RAILS

GND RAILS

SILKSCREEN:2SILKSCREEN:1

ONLY ON IN RUN

EMC: C600,C626,C627,C628,C629,C630,C631

SILKSCREEN:3

"S0" RAILS "S3" RAILS

6 OF 110

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9

8

7

6

5

4

3

2

14

13

12

11

10

1

J600

2

1 C631

2

1 C630

2

1 C623

2

1 C600

2

1

3

Q610

2

1 C626

2

1 C624

2

1 C627

2

1

3

Q602

2

1

LED602

2

1R602

2

1

3

Q604

2

1

LED604

2

1R604

2

1

LED603

2

1R603

2

1

LED605

2

1R600

2

1

LED601

2

1R601

=PP1V05_S0_MCP_PEX_DVDD

PP3V3_S3

NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

MAX_NECK_LENGTH=3 MM

VOLTAGE=3.3VMAKE_BASE=TRUE

=PP3V3_S3_MINI

=PP1V05_S0_MCP_HDMI_VDD_R

=PP5V_S3_1V8

=PP5V_S3_MCPREG=PP5V_S3_CAMERA=PP5V_S3_IR

=PP1V5_S3_MEM_B=PP1V5_S3_MEMRESET=PPDDR_S3_S0FET

PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm


MIN_LINE_WIDTH=0.3 MM

=PP3V3_S0_VRD

=PPSPD_S0_MEM_B

=PP3V3_S0_MCP_GPIO=PP3V3_S0_MCP_VPLL_UF=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

PPVTT_S0_FSB_REG

MIN_LINE_WIDTH=0.6 mm

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUEVOLTAGE=1.2V

=PPVTT_S0_FSB_CPU

PPMCPCORE_S0_REG

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.05VMAKE_BASE=TRUE

NET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

=PP1V05_S0_MCP_PLL_UFPM_ACDC_PS_ON

=PP5V_S3_PWRCTL

=PP5V_S3_VTTCLAMP

=PP1V5_S3_MEM_A

PP3V3_S5_REG

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mmVOLTAGE=3.3VMAKE_BASE=TRUE

=PP3V3_S5_PWRCTL=PP3V3_S5_S3FET=PP3V3_S5_S0FET=PP3V3_S5_ENET_FET

LCD_PWM

=PP3V3_S3_SMBUS_SMC_A_S3=PP3V3_S3_MCPREG

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR

PPVTT_S0_DDR_LDOMAKE_BASE=TRUEVOLTAGE=0.75VMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.2 mm

=PP3V3_S5_MCP=PP3V3_S5_MCP_GPIO

=PP0V75_S0_MEM_VTT_A=SMB_ACDC_SDA

PP12V_S5

=PP5V_S3_S0FET

PP1V1_S5_REG

MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.1V =PP1V1_S5_ENET_FET

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S5_ROM=PP3V3_S5_RTC_D

=PP3V3_S5_SMC

=PP3V3_S5_LPCPLUS

=PP3V3_S5_MEMRESET

ITS_ALIVE

PP3V3_S5_REG

=PP5V_S5_AVREF

=PP3V3_S5_SMCUSBMUX

MXM_GOOD

PP3V3_S3

CORE_VOLTAGES_ON

ITS_PLUGGED_IN

LCD_SHOULD_ON

PP3V3_S3

GPU_PRESENT_R

=PP12V_S5_PWRCTL

PPDDR_S3_REG

NET_SPACING_TYPE=PPDDR_MEMMAX_NECK_LENGTH=3 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.5V


=PP3V3_S5_P1V1S5

PPVCORE_S0_CPU

MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.1VMIN_LINE_WIDTH=0.6MM


MAKE_BASE=TRUE

NET_SPACING_TYPE=PWR

=PP3V3_S5_SMBUS_SMC_BSA

PM_SLPS3_BUF2_L

=PPDDR_S3_PGCMP

CORE_VOLTAGES_ON_R

LCD_BKL_ON

=PPVTT_S0_CPU

=PP3V3_S3_VREFMRGN

PP5V_S5_LDO

NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V



MAKE_BASE=TRUE

=PP12V_S5_FW=PPVIN_S5_DDRREG=PPVIN_S5_P3V3S5=PPVIN_S5_P5VS3=PP12V_S5_REG

PP12V_S5

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm


MAKE_BASE=TRUEVOLTAGE=12V

=PP5V_S0_SATA=SMB_ACDC_SCL

GPU_PRESENT_DRAIN

PP5V_LCD_CONN

ALL_SYS_PWRGD_R

PP3V3_S0

=PP5V_S0_VRD=PP5V_S0_MXM

=PP5V_S0_LCD

=PP5V_S0_ISENSE=PP5V_S0_DP_AUX_MUX

=PP5V_S0_AUDIO

=PPSPD_S0_MEM_A

=PP3V3_S0_XDP

=PP3V3_S0_VIDEO

=PP3V3_S0_TSENS

=PP3V3_S0_SMC_LS

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_MGMT

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SATALED

=PP3V3_S0_PWRCTL

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_FAN

=PP3V3_S0_DPCONN

=PP3V3_S0_AUDIO=PP3V3R1V5_S0_MCP_HDA

=PPV_S0_MXM_PWR=PPVIN_S0_PPVTT_FSB

=PPVIN_S0_MCPCORE

=PP12V_S0_VRD

=PP1V05_S0_MCP_AVDD_UF

=PPVTT_S0_XDP=PP1V05_S0_MCP_FSB

=PP3V3R1V8_S0_MCP_IFP_VDD_R=PP1V8_S0_PGCMP

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MXM

=PP3V3_S0_ODD

=PP5V_S0_SATA

=PP5V_S0_PWRCTL

=PP12V_S0_FAN=PP12V_S0_AUDIO_SPKRAMP

PP12V_S0


VOLTAGE=12VMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMNET_SPACING_TYPE=AUDIO

PP1V8_S0_REG

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWR


MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.1 MM

VOLTAGE=1.8V

=PP1V05_S0_MCP_SATA_DVDD0

PP12V_S0

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BT

=PP3V3_S3_MCP_GPIO=PP3V3_S3_SDCARD

=PP3V3_S3_SMC

=PP5V_S3_USB=PP5V_S3_DDRREG

PP5V_S3_REG


VOLTAGE=5V


MAKE_BASE=TRUE

=PPVCORE_S0_MCP

=PPVCORE_S0_CPU

=PP0V75_S0_MEM_VTT_B=PPVTT_S0_VTTCLAMP

=PP1V5_S0_AUD_DIG

=PP1V5_S0_CPU_VCCPLL

=PP1V5_FWRS0_FWXIO

PP1V5_S0

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM




=PP3V3_FW_FWPHY

PP5V_S0MAKE_BASE=TRUE


VOLTAGE=5.0V


=PP5V_S0_LPCPLUS

=PP3V3_FWRS0_FWXIO

PP3V3_S0


MAKE_BASE=TRUE


VOLTAGE=3.3V


MAX_NECK_LENGTH=4.1 MMMAKE_BASE=TRUE

GNDMIN_LINE_WIDTH=0.6 mm

VOLTAGE=0VMIN_NECK_WIDTH=0.2MM

NET_SPACING_TYPE=AUDIO

Power Conn / AliasSYNC_MASTER=MASTER SYNC_DATE=N/A

70

2N7002SOT23-HF1

2.0X1.25MM-SMGREEN-3.6MCD

1/16W

1K5%

MF-LF402

9

2N7002SOT23-HF1

MXM

MXM


MF-LF

5%1/16W

1K

402

MXM


5%

MF-LF1/16W

1.5K

402

GREEN-3.6MCD

DEVELOPMENT

2.0X1.25MM-SM

DEVELOPMENT

1K5%1/16WMF-LF402

MF-LF402

5%1/16W

1K

GREEN-3.6MCD2.0X1.25MM-SM

CRITICAL

76833-0100M-RT-TH

0.001UF

402

10%

X7R50V 50V

X7R

0.001UF10%

402

10UF20%10VX5R805

0.001UF50VX7R402

10%2N7002SOT23-HF1

402

10%

X7R50V

0.001UF10%16V

1210

10UF

X5R-CERM

70 50 49 9

0.001UF

402

50VX7R

10%

28 25

110 78 6 34

26

80

74

47

47

108 32 30

33

78

75

71

32

21 19 18

26

25 22 21

30 25 16

76

12 11

74 54

25

70

78

108 31 30

76 6

70

78

78

38

90

52

74

75

25 22

20 18

31 52

6

78

79

38

25 22

61 51

28

50 49

51

33

76 6

50

46

110 78 6

110 78 6

78 70 38

75

79

72 71

52

70 90 89

71 55 50 10

29

76

43

75

76

73

76

6

45 6

52

90

78 6

71

84

90

53

93

68 62

31

13

90 89

55

55 50

54 53 50

52

52

45

70

25

55

57 56

94

68 67 66 65 64 62

25 21

53

76

74

71 70

25

13

25 22 14

26

70

52

52

85 84

45

45 6

80

57 56

67

70 6

80

28 20

70 6

29

47

21

47

46

75 30

110 73

25 22

12

32

78

62

12

41

54

43 42 41

110 78 51

41

78 6




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

BACKER PLATE NUTS

REAR COVER STANDOFFS

4 MM PLATED HOLES FOR CPU HEATSINK

DIMM CONNECTOR NUTS

998-0850

870-1125FOR MCP HEATSINK

870-1125FOR MCP HEATSINK

7 OF 110

051-7845

A.0.0


1

SDF0717

1

SDF0716

1

SDF0715

1

SDF0714

1

SDF0750

1

SDF0751

1

SDF0752

1

SDF0753

1

SDF0703

1

SDF0702

1

SDF0701

1

SDF0700

1

SDF0713

1 SC07011 SC0700

1

ZH07031

ZH07021

ZH07011

ZH0700

HOLES & STANDOFFSSYNC_MASTER=MASTER SYNC_DATE=N/A

CRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICALCRITICAL

STDOFF-6.8OD15.0H-1.56-THSTDOFF-6.8OD15.0H-1.56-TH

CRITICAL

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

CRITICAL

NUT-4.25OD1.4H-1.40-3.25-TH

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICALCRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

CRITICAL

NUT-6.5OD1.4H-1.56-3.8-TH

STDOFF-6.8OD15.0H-1.56-TH

CRITICAL

CLIP-SM1

CRITICAL

EMI-SPRINGCLIP-SM1

EMI-SPRING

CRITICAL

OMIT

4P75R4

OMIT

4P75R44P75R4

OMITOMIT

4P75R4




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


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B

C

345678

D

B

8 7 5 4 2 1

NC ON UNUSED ALIASES

MCP HAS INTERNAL 15K PULL-DOWNS

UNUSED MEMORY SIGNALS

UNUSED GMUX JTAG FROM MCP

8 OF 110

051-7845

A.0.0


TP_PE4_CLKREQ_L NC_PE4_CLKREQ_LNO_TEST=TRUEMAKE_BASE=TRUE

TP_ENET_PWRDWN_L

USB_MINI_N NC_USB_MINI_NNO_TEST=TRUEMAKE_BASE=TRUE

TP_USB_10P

TP_USB_10N

NC_USB_MINI_PNO_TEST=TRUEMAKE_BASE=TRUE

USB_MINI_P

NO_TEST=TRUENC_USB_EXCARD_PMAKE_BASE=TRUE

NO_TEST=TRUENC_USB_EXCARD_NMAKE_BASE=TRUE

USB_EXCARD_P

USB_EXCARD_N

MAKE_BASE=TRUENC_ENET_INTR_L

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_MCP_KBDRSTIN_L

TP_PCIE_PE4_D2RN

MAKE_BASE=TRUENC_PCIE_EXCARD_D2R_P

NO_TEST=TRUE

NC_MCP_PCI_GNT0_LMAKE_BASE=TRUE NO_TEST=TRUE

TP_PCI_AD<8>NO_TEST=TRUE

NC_PCI_AD<8>MAKE_BASE=TRUE

TP_PCI_AD<12..10>NO_TEST=TRUE

NC_PCI_AD<12..10>MAKE_BASE=TRUE

EXCARD_CLKREQ_LNO_TEST=TRUEMAKE_BASE=TRUE

NC_EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_NNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_EXCARD_PNO_TEST=TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARD_P

ODD_PWR_EN_LMAKE_BASE=TRUE NO_TEST=TRUENC_ODD_PWR_EN_L

NO_TEST=TRUEMAKE_BASE=TRUENC_USB_10P

NO_TEST=TRUENC_USB_10NMAKE_BASE=TRUE

TP_SB_A20GATENO_TEST=TRUEMAKE_BASE=TRUE

NC_SB_A20GATE

TP_PE4_PRSNT_LNO_TEST=TRUE

NC_PE4_PRSNT_LMAKE_BASE=TRUE

PCIE_EXCARD_PRSNT_LMAKE_BASE=TRUENC_PCIE_EXCARD_PRSNT_L

NO_TEST=TRUE

TP_PCIE_CLK100M_PE6NMAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_PE6PMAKE_BASE=TRUE NO_TEST=TRUE




TP_PCI_PAR

TP_PCI_INTZ_L

TP_PCI_INTW_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

TP_PCI_FRAME_L

TP_PCI_CLK1

TP_PCI_CLK0

TP_PCI_C_BE_L<3>

PCIE_EXCARD_D2R_N

TP_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_PE4_R2D_CP

PCIE_EXCARD_D2R_P

NO_TEST=TRUENC_USB_TPAD_PMAKE_BASE=TRUE

TP_PCIE_PE4_D2RP

NC_PCIE_PE4_D2RNMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_PE4_D2RP

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUENC_MEM_A_CLK2P

NO_TEST=TRUE

GMUX_JTAG_TMS

NC_MCP_BUF_SIO_CLKNO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_IRDY_L

NC_MCP_TV_DAC_RSETMAKE_BASE=TRUE NO_TEST=TRUE

CRT_IG_G_Y_Y

TP_PCI_AD<31..15>

NC_PCI_FRAME_LMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_ENET_PWDWN_L

NO_TEST=TRUE

NO_TEST=TRUENC_MCP_CLK27M_XTALINMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_CLK0

NC_PCI_CLK1NO_TEST=TRUEMAKE_BASE=TRUE

USB_TPAD_N

NC_CRT_IG_HSYNCMAKE_BASE=TRUE NO_TEST=TRUE

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MAKE_BASE=TRUE NO_TEST=TRUENC_PCI_AD<31..15>

NC_PCI_PERR_LMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE NO_TEST=TRUEMAKE_BASE=TRUENC_MCP_GPIO_18

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_INTW_L

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_INTY_L

NO_TEST=TRUENC_PCI_INTZ_LMAKE_BASE=TRUE

MCP_TV_DAC_RSET

MCP_CLK27M_XTALOUT

TP_PCI_IRDY_L

TP_MCP_RGB_VSYNC

TP_MCP_RGB_HSYNC

TP_PCI_C_BE_L<1..0>

TP_ENET_INTR_L

TP_MCP_KBDRSTIN_L

NC_MCP_TV_DAC_VREFMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_MCP_RGB_VSYNCMAKE_BASE=TRUE

NC_MCP_RGB_HSYNCMAKE_BASE=TRUE NO_TEST=TRUE

TP_MCP_BUF_SIO_CLK

MAKE_BASE=TRUENC_LPC_DRQ0_L

NO_TEST=TRUETP_LPC_DRQ0_L

TP_PCI_PERR_LMAKE_BASE=TRUENC_MEM_A_CLK2N

NO_TEST=TRUE

NC_MEM_A_CLK5PNO_TEST=TRUEMAKE_BASE=TRUE

TP_MEM_A_CLK5P

NC_MEM_A_CLK5NMAKE_BASE=TRUE NO_TEST=TRUE

NC_GMUX_JTAG_TCK_LNO_TEST=TRUEMAKE_BASE=TRUE

GMUX_JTAG_TCK_L

MAKE_BASE=TRUE NO_TEST=TRUENC_GMUX_JTAG_TDO

MAKE_BASE=TRUE NO_TEST=TRUENC_GMUX_JTAG_TDIGMUX_JTAG_TDI

MAKE_BASE=TRUENC_GMUX_JTAG_TMS

NO_TEST=TRUE

NC_PCI_C_BE_L<1..0>NO_TEST=TRUEMAKE_BASE=TRUE

CRT_IG_VSYNC

NO_TEST=TRUENC_MEM_B_CLK2PMAKE_BASE=TRUE

TP_MEM_B_CLK2P

NO_TEST=TRUENC_MEM_B_CLK2NMAKE_BASE=TRUE

TP_MEM_B_CLK2N

NO_TEST=TRUENC_MEM_B_CLK5PMAKE_BASE=TRUE

TP_PCI_INTY_L

NC_MLB_RAM_SIZEMAKE_BASE=TRUE NO_TEST=TRUE

NC_CRT_IG_R_C_PRMAKE_BASE=TRUE NO_TEST=TRUE

TP_MEM_B_CLK5P

MAKE_BASE=TRUE NO_TEST=TRUENC_CRT_IG_VSYNC

TP_PCI_DEVSEL_L

TP_PCI_SERR_L NC_PCI_SERR_LMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCI_DEVSEL_LMAKE_BASE=TRUE NO_TEST=TRUE

TP_MEM_A_CLK5N

NC_CRT_IG_G_Y_YMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUENC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_PE4P

PCIE_EXCARD_R2D_C_N

TP_PCI_RESET1_L

TP_PCI_STOP_L

NO_TEST=TRUENC_PCIE_CLK100M_PE5PMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_PE5N

TP_PCI_TRDY_L

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_PE4N

TP_MEM_A_CLK2N

TP_MEM_A_CLK2P

NC_PCI_TRDY_LNO_TEST=TRUEMAKE_BASE=TRUE

NO_TEST=TRUENC_PCI_GNT1_LMAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCI_STOP_L

TP_MEM_B_CLK5N

NO_TEST=TRUENC_PCI_INTX_LMAKE_BASE=TRUE

NC_PCI_C_BE_L<3>MAKE_BASE=TRUE NO_TEST=TRUE

TP_MLB_RAM_SIZE

TP_MCP_GPIO_18

NC_MEM_B_CLK5NMAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_PE4_R2D_CP

GMUX_JTAG_TDO

USB_TPAD_P

NC_PCIE_PE4_R2D_CNMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUENC_PCIE_EXCARD_R2D_C_P

NO_TEST=TRUE

MAKE_BASE=TRUENC_PCIE_EXCARD_R2D_C_N

NO_TEST=TRUE

NC_USB_TPAD_NNO_TEST=TRUEMAKE_BASE=TRUE

TP_PCI_INTX_L

NO_TEST=TRUENC_PCI_PARMAKE_BASE=TRUE

NO_TEST=TRUENC_PCI_RESET1_LMAKE_BASE=TRUE


UNUSED SIGNAL ALIAS

17

18

20

20

20

20

20

20

17

19

19

17

17

17

21

21

17

17

17

17

17

17

17

17

19

19

19

19

19

19

19

19

19

17

17

17

17

17

19

18

19

20

18

18

18

18

18

18

18

19

18

18

19

18

21

21

19

19

16

17

19

18

15

15

19

16

19

19

16

17

19

19

19

15

15

16

21

17

17

20

19

OUT

OUTIN

IN

IN

IN

OUT

OUT

IN

IN OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

IN

IN

IN

IN

IN

BI

IN

OUT

OUT

OUT

OUTIN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUTIN

IN OUT

IN

OUT




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

USB PORT 2 AND 3 (C AND D) SHARE OVER-CURRENT WITH PORT 2

PREVIOUSLY, PORT 3 HAD ITS OWN BUT EFI MAPS THAT TO EXPRESSCARDSEE RDAR://6250424

K22/K23 Use one GPIO for both ports 2&3 OC

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

MCP_CPUVDD_EN WILL ASSERT AFTER MCP_PS_PWRGD IS UP

Audio Mux aliasing

K23 Uses this to control the DP audio mux. K22 does not need this signal

K23 uses a mux between the DP audio source and the audio in portthis alias connects spdif directly from the I/O port to the codec

SIGNAL ALIAS

(P50 HAS A 100K TO GROUND)

MCP79 PCIe PRSNT# Straps

DisplayPort / TMDS Support

PEG Slot Support

9 OF 110

051-7845

A.0.0


21

R993

2

1R912

21

R911

21

R910

21

R930

2

1R955

21

R983

21

R981

21

R992

21

R990

21

R991

21

R971

2

1 C973

21

R925

21

R972

21

R926

21

R929

21

R900

PCIE_RESET_L

PCA9557D_RESET_L

LPC_RESET_L

PM_CLK32K_SUSCLKPM_CLK32K_SUSCLK_R

LPC_CLK33M_SMC

PEG_RESET_L

MINI_RESET_L

MCP_MII_NUMAKE_BASE=TRUE

LPC_CLK33M_SMC_R

=MCP_MII_CRS

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

FW_RESET_L

=MCP_MII_COL

=MCP_MII_RXER

DEBUG_RESET_L

MEM_VTT_EN_R DDRVTT_EN

CARDREADER_PLT_RST_L

MCP_CPUVDD_EN MCP_CPU_VLD

AUD_SPDIF_IN_CODEC

TP_AUD_MUX_CNTRLMAKE_BASE=TRUE

MAKE_BASE=TRUEAUD_SPDIF_IN

AUD_MUX_CNTRL

PM_SLPS3_BUF1_LMAKE_BASE=TRUE

PM_SLP_S3_LMAKE_BASE=TRUEPM_SLPS3_BUF2_L

PCIE_FW_PRSNT_L

PCIE_MINI_PRSNT_L

GPU_CLK100M_PCIE_PMAKE_BASE=TRUEGPU_CLK100M_PCIE_N

MAKE_BASE=TRUEPEG_R2D_C_P<0..15>MAKE_BASE=TRUE

MAKE_BASE=TRUEPEG_R2D_C_N<0..15>

MAKE_BASE=TRUEPEG_D2R_P<0..15>

MAKE_BASE=TRUEPEG_D2R_N<0..15>

MAKE_BASE=TRUEMXM_DETECT_L

MAKE_BASE=TRUEDP_IG_ML_P<3>

MAKE_BASE=TRUEDP_IG_ML_N<3>

DP_IG_ML_P<2..0>MAKE_BASE=TRUEDP_IG_ML_N<2..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUEDP_IG_DDC_CLK

MAKE_BASE=TRUEDP_IG_DDC_DATA

DP_IG_HPDMAKE_BASE=TRUE

HPLUG_DET2MAKE_BASE=TRUE

=DVI_HPD_GMUX_INT

PEG_CLK100M_P

PEG_CLK100M_N

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

=PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

PEG_PRSNT_L

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

TP_MLB_RAM_VENDOR MXM_GOODMAKE_BASE=TRUE

USB_EXTD_OC_L

MAKE_BASE=TRUEUSB_EXTC_OC_L


SIGNAL ALIASES

47

5%

402MF-LF

0

1/16W

62

62 103 66

402

100K5%1/16WMF-LF

402MF-LF1/16W5%

15

5%1/16W

402MF-LF

15

21

PLACEMENT_NOTE=Place close to U1400

22

1/16W5%

MF-LF402

21

1/16W

47K

402MF-LF

5%

51

49

41

34

90 87

29

78 75

103 49

103 51

103 49

402

1/16W5%

MF-LF

33


MF-LF1/16W5%

33

402

PLACEMENT_NOTE=Place close to U1400103 19

402

0

5%1/16WMF-LF

402

0

5%

MF-LF1/16W

1/16W

0

MF-LF

5%

402

1/16W

0

MF-LF

5%

402

0.47UF6.3VCERM-X5R

10%

402

NO STUFF

402

33PLACEMENT_NOTE=Place close to U1400

5%1/16WMF-LF

402MF-LF

33

1/16W5%

402

5%1/16WMF-LF

33


1/16W5%

MF-LF

22

402


17

19

103 19

103 21

1/16W5%

20K

MF-LF402

17 85

17

17

18

18

18

18

18

18

18

91

93

93

107 91

107 91

107 91

107 91

102 87

102 87 17

17

17

17

102 86

102 86

17

17 102 86

102 86

18

18

18

94 73

102 21 70 50 49 6

18

21 6

46

46 20

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

A_34*

A_35*

REQ_4*

A_7*

DBSY*

INIT*

A_20*

A20M*

ADS*

ADSTB_0*

ADSTB_1*

A_3*A_4*

A_6*

A_8*

A_10*

A_14*A_15*A_16*

A_17*A_18*A_19*

A_21*

A_22*A_23*A_24*A_25*

A_26*A_27*A_28*A_29*

A_30*A_31*A_32*A_33*

BCLK_0BCLK_1

BNR*

BPRI*

BR_0*

DEFER*DRDY*

FERR_PBE*

IERR*

IGNNE*

LINT0LINT1

REQ_0*

REQ_1*

REQ_3*

RS_0*RS_1*RS_2*

SMI*

STPCLK*

REQ_2*

A_13*

A_12*A_11*

A_9*

A_5*

LOCK*

RESET*

TRDY*

HIT*

HITM*CONTROL

ADDR GROUP0

(1 OF 7)

CLK

SB

ADDR GROUP1

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

D_11*D_10*

D_9*

D_1*

D_2*

D_8*D_7*D_6*

DBI_0*

DBI_1*

DBI_2*

DBI_3*

DSTBN_0*

DSTBN_1*

DSTBN_2*

DSTBN_3*

DSTBP_0

DSTBP_1

DSTBP_2

DSTBP_3

D_0*

D_3*D_4*D_5*

D_12*D_13*D_14*

D_15*

D_16*D_17*D_18*

D_19*D_20*D_21*D_22*D_23*

D_24*D_25*D_26*D_27*

D_28*D_29*D_30*D_31*

D_32*D_33*

D_34*D_35*D_36*D_37*

D_38*D_39*D_40*D_41*

D_42*D_43*D_44*D_45*D_46*

D_47*

D_48*D_49*D_50*

D_51*D_52*D_53*D_54*D_55*

D_56*D_57*D_58*D_59*

D_60*D_61*D_62*D_63*

(2 OF 7)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE W/ A TESTPOINT W/ A GND NEARBY

CPU GTLREF

(63.5% OF 1.2V) = 0.762VGTLREF VOLTAGE SHOULD BE 0.635 * VTT

10 OF 110

051-7845

A.0.0


2

1R1044

2

1R1043

2

1R1001

2

1 C1042

21

R1045

2

1 C1043

2

1R1041

2

1 C1040

2

1R1040

2

1 C1041

21

R1042

C17

G19

E12

B9

A16

G20

G12

C8

C20

D19

G11

A8

A11A10

A7

B22A22A19

B19

B7

B21C21B18

A17B16C18B15

C14C15A14

B6

D17

D20

G22D22E22G21

F21E21F20E19

A5

E18F18F17G17G18

E16E15G16

G15F15

C6

G14

F14G13E13D13

F12F11D10E10

D7

A4

E9F9F8

G9

D11C12B12D8

C11B10

C5B4

J1000

E3

M3

P2

A3F5

B3G23

J6K6

M6J5K4

C3

L1K1

P3

N2

AB2

E4D4

R3

C1G7

B2

F3

G8C2

G28F28

AD5

R6

D2

T5

R4

M4

L4

M5

P6

AJ6

AJ5

AH5

AH4

AG5

AG4

L5

AG6

AF4

AF5

AB4

AC5

AB5

AA5

AD6

AA4

Y4

Y6

W6

AB6

W5

V4

V5

U4

U5

T4

U6

K3

J1000

2

1R1004

2

1R1003

2

1R1000

PPCPU_VTT_OUT_LEFT

FSB_BPRI_L

FSB_DEFER_L

FSB_DBSY_L

FSB_BREQ0_L

CPU_FERR_L

PPCPU_VTT_OUT_RIGHT

CPU_STPCLK_L

CPU_NMI

FSB_HIT_LFSB_HITM_L

FSB_CPURST_L

CPU_IERR_LCPU_INIT_L

FSB_RS_L<0>FSB_RS_L<1>

PPCPU_VTT_OUT_RIGHT

FSB_RS_L<2>FSB_TRDY_L

FSB_A_L<20>

FSB_A_L<19>FSB_A_L<18>FSB_A_L<17>

FSB_D_L<27>

CPU_GTLREF1

FSB_BNR_L

FSB_DSTB_L_P<1>FSB_DSTB_L_N<1>FSB_DINV_L<1>

FSB_D_L<29>FSB_D_L<28>

FSB_D_L<25>

FSB_DSTB_L_P<0>

FSB_DINV_L<0>

FSB_D_L<13>

FSB_D_L<11>

FSB_ADS_L

=PPVTT_S0_CPU

CPU_IGNNE_L

FSB_DSTB_L_N<0>

FSB_D_L<12>

FSB_D_L<9>

FSB_LOCK_L

FSB_A_L<3>

FSB_D_L<10>


FSB_D_L<8>FSB_D_L<7>FSB_D_L<6>

FSB_DINV_L<2>

FSB_DINV_L<3>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_D_L<0>


FSB_D_L<5>



FSB_D_L<18>FSB_D_L<19>FSB_D_L<20>FSB_D_L<21>


FSB_D_L<26>

FSB_D_L<30>

FSB_D_L<31>

FSB_D_L<32>







FSB_D_L<54>FSB_D_L<55>FSB_D_L<56>FSB_D_L<57>FSB_D_L<58>


FSB_D_L<63>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF0CPU_GTLREF_DIV0

FSB_REQ_L<4>

FSB_A_L<7>

CPU_A20M_L

FSB_ADSTB_L<0>

FSB_A_L<4>

FSB_A_L<6>

FSB_A_L<10>

FSB_A_L<14>FSB_A_L<15>

FSB_A_L<16>

FSB_A_L<21>FSB_A_L<22>FSB_A_L<23>FSB_A_L<24>

FSB_A_L<25>FSB_A_L<26>FSB_A_L<27>FSB_A_L<28>


FSB_CLK_CPU_PFSB_CLK_CPU_N

FSB_DRDY_L

FSB_REQ_L<0>FSB_REQ_L<1>

FSB_REQ_L<3>

CPU_SMI_L

FSB_REQ_L<2>


FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<5>

FSB_A_L<31>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<34>FSB_A_L<35>FSB_ADSTB_L<1>

CPU_INTR

FSB_A_L<8>

PPCPU_VTT_OUT_LEFT

CPU_GTLREF_DIV1

SYNC_MASTER=MASTER

CPU FSBSYNC_DATE=N/A

1001%1/16WMF-LF402

MF-LF

57.6

402

1%1/16W

MF-LF

5%

402

621/16W

1UF6.3VCERM402

10%

MF-LF402

1%

10

1/16W

X7R-CERM

NOSTUFF

220PF10%

402

50V

1%1/16WMF-LF

100

402 CERM

10%6.3V

1UF

402

1/16W

57.6

402MF-LF

1%

10%

402X7R-CERM50V

220PF

NOSTUFF1/16W

10

1%

MF-LF402

CPU

CRITICAL

WOLFDALE-SKT-1BGA-NOHSK

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

CPU

CRITICAL

WOLFDALE-SKT-1BGA-NOHSK

2001/16W

402

5%

MF-LF402

62

MF-LF

5%1/16W

MF-LF

5%

402

621/16W

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14 13

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

100 14

12 11 10

12 11 10

100

12 11 10

100 29 11

71 55 50 6

12 11 10

100 29 11

12 11 10

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

IN

BI

TESTHI_0

BPM_0*BPM_1*BPM_2*BPM_3*BPM_4*

BPM_5*

DBR*

FC3FC8

FC10FC15

FC18FC23FC26

FC27/BPMB0*

FC28/TDO_M

FC29

FC30FC31FC32FC33

FC34FC35FC36FC37FC39

FC40

FC41/BPMB1*

ITPCLK_0ITPCLK_1

RSVD_A20

RSVD_AC4RSVD_AE4

RSVD_AE6

RSVD_AH2

RSVD_D1

RSVD_D14

RSVD_D16

RSVD_E5RSVD_E6

RSVD_E7

RSVD_E23RSVD_F23

RSVD_F29

RSVD_G6

RSVD_J3

RSVD_N4

RSVD_N5

RSVD_P5

RSVD_V2

TCKTDITDO

TESTHI_1

TESTHI_2TESTHI_3TESTHI_4TESTHI_5

TESTHI_6TESTHI_7

TESTHI_8/BPMB3*TESTHI_9/BPMB2*

TESTHI_10

TESTHI_12/TDI_M

TMS

TRST*

(4 OF 7)

RESERVED

TEST

JTAG

XDP/ITP

PROCHOT*THERMTRIP*

GTLREF1GTLREF0

THERMDC

FC5/GTLREF2

BOOTSELECT

BSEL_0BSEL_1BSEL_2

COMP_0COMP_1

COMP_2COMP_3COMP_8

DPRSTP*DPSLP*

IMPSEL

MSID_0MSID_1

PECI

PSI*

PWRGOOD

SKTOCC*

SLP*

THERMDA

VRDSEL

FC38/GTLREF3

(3 OF 7)

THERMAL

PWR MGMT

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

OUT

OUT OUT

IN

OUT

OUT

OUTOUT

OUT

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(TDI)WITHIN 38MM (1.5IN) OF THE CPU

FROM 975X PDG: IMPSEL0 - 51 PD TO GND

IPU

NC

NC

NCNC

PLACE TMS/TMI/TCK TERMINATION

(TMS)

(TCK)

NC

(ALSO WRITTEN AS BPM2)CPU BPMB TERM

KENTSFIELD CPU SUPPORT

CPU BPM TERM

(SELECTS 50 OHM SYSTEM IMPEDANCE)

11 OF 110

051-7845

A.0.0


2

1R1150

2

1R1120

2

1R1121

2

1R1122

2

1R1123

2

1R1128

2

1R1151 2

1R1109

2

1R1129

2

1R1180

2

1R1181

2

1R1182

2

1R1183

2

1R1130

2

1R1133

2

1R1132

2

1R1135

AL3M2

AK1AL1

L2

AE8

N1

Y3AL2

G5

V1

W1

F6

H2H1F2G10

P1T2

B13

R1G2T1A13

G30

H30G29

Y1

J1000

AG1AC1

G4G3

F24

G24G26G27G25

F25

W2

H5

W3F26

AF1AD1

AE1

V2

P5

N5

N4

J3

G6

F29

F23

E7

E6E5

E23

D16

D14

D1

AH2

AE6

AE4AC4

A20AJ3AK3

AK6

C9

AM6AA2AB3AD3

H4J17H16H15

J16U3

J2

U2

U1

G1

E29A24

AE3H29E24

AC2

AG3AF2AG2AD2

AJ1AJ2

J1000

2

1R1191

2

1R1195

2

1R1190

2

1R1192

2

1R1193

2

1R1194

21

R1102

21

R1101

21

R1100

CPU_PWRGDCPU_DPRSTP_L

CPU_DPSLP_L

CPU_PROCHOT_L

PPCPU_VTT_OUT_RIGHT

CPU_GTLREF1

CPU_BOOT

CPU_BSEL<0>CPU_BSEL<1>

CPU_PSI_LFSB_CPUSLP_L

CPU_BSEL<2>

CPU_THERMD_NCPU_THERMD_P

CPU_PECI_L

CPU_COMP<3>CPU_COMP<2>

CPU_COMP<0>

CPU_GTLREF0


CPU_COMP<8>


=PPVTT_S0_FSB_CPU

PPCPU_VTT_OUT_LEFT

CPU_XDP_BPM_L<3>CPU_XDP_BPM_L<4>

CPU_XDP_BPM_L<5>

CPU_XDP_BPM_L<1>CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<0>

PPCPU_VTT_OUT_RIGHT

PPCPU_VTT_OUT_RIGHT

CPU_XDP_TCKCPU_XDP_TDI

CPU_XDP_TMS

CPU_TESTHI_M

CPU_TESTHI_2_7

PPCPU_VTT_OUT_RIGHT

PPCPU_VTT_OUT_LEFT

CPU_TESTHI_0CPU_TESTHI_1

CPU_TESTHI_10PM_PGOOD_PVCORE_CPU

CPU_XDP_BPMB<0>CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3>

CPU_XDP_BPMB<2>


CPU_XDP_TDO

CPU_XDP_TRST_L

CPU_XDP_BPM_L<0>CPU_XDP_BPM_L<1>CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<3>CPU_XDP_BPM_L<4>CPU_XDP_BPM_L<5>


XDP_DBRESET_L

PM_THRMTRIP_L

CPU_COMP<1>

CPU_COMP<8>

CPU_PD_IMPSEL


CPU TEST & MISC.

71 70

100 50 14

100 50 14 71

100 14

100 14

100 14 13

100 14

402

1/16WMF-LF

1301%

NOSTUFF

MF-LF1/16W

402

1%49.9

402MF-LF

49.91%1/16W 1/16W

1%

402MF-LF

49.9 49.91%1/16WMF-LF402

1%

402MF-LF1/16W

24.9

402

5%1/16WMF-LF

51

108 55

108 55

108 55

51

402

1/16W5%

MF-LF

100 14

100 14

100 14

MF-LF

511/16W

5%

402

100 13 11

100 13 11

100 13 11

100 13 11

5%1/16W

402MF-LF

515%1/16W

402

51

MF-LF

5%

402MF-LF1/16W

515%1/16WMF-LF402

51

100 13 11

100 13 11

100 13 11

MF-LF402

511/16W

5%

MF-LF402

1/16W5%51 51

1/16W5%

402MF-LF MF-LF

515%

402

1/16W

BGA-NOHSKWOLFDALE-SKT-1

CPU

CRITICAL


CRITICAL

CPU

1/16W5%

MF-LF402

51

MF-LF

511/16W5%

402402

1/16W

51

MF-LF

5%51

402MF-LF1/16W5%

51

402MF-LF1/16W5%

511/16W5%

MF-LF402

100 13 11

51

5%

402

1/16WMF-LF

5%

51

402MF-LF1/16W

5%

51

402

1/16WMF-LF

28 13

100 13 11

100 13 11

100 13 11

100 13 11

100 13 11

100 13 11

100 13

100 13

100 13

100 13

100 13

12 11 10

100 29 10

100 11

100 11

100 11

100 29 10

100 11

100 11

100 11

100 11

100 11

12 6

12 11 10

100 13 11

100 13 11

100 13 11

100 13 11

100 13 11

100 13 11

12 11 10

12 11 10

12 11 10

12 11 10

100 11

100 11

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

VCCP

VCCP

VTT_C29

VTT_C30VTT_D25VTT_D26VTT_D27

VTT_D28VTT_D29VTT_D30

VTT_OUT_RIGHT

VTT_OUT_LEFTVTT_SEL

VTT_C28VTT_C27VTT_C26

VTT_C25

VTT_B29VTT_B28

VTT_B27VTT_B26VTT_B25VTT_A30VTT_A29

VTT_A28VTT_A27VTT_A26VTT_A25

VTT_B30

VCCA

VCCIOPLL

VCCP

VCCPLL

VCC_MB_REGULATIONVCC_SENSE

VID_0VID_1

VID_2VID_3VID_4VID_5

VID_6VID_7

VID_SELECT

VSSA

VSS_MB_REGULATIONVSS_SENSE

VCCP

(7 OF 7)

OUT

GND GND

(5 OF 7)

GNDGND

(6 OF 7)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

POWER

GND

VCC PLL DECOUPLING

(SEE VREG PAGE)

VCCP CORE DECOUPLING

~125MA CURRENT

THIS IS FOR OLDER CPU SUPPORT

GND

WILL PLACE FILTER BUT NOT CONNECT FOR WOLFDALE

VID PULLUPS WITH VREG

FSB VTT DECOUPLING

12 OF 110

051-7845

A.0.0


2

1R1200

V25

E20

R7

V27

R5

V28V29

R2

V30

V26

E26

P7P4

N7N6

N3M7M1L7

L6

C13

V7

B8B5

B1

D3D5

R30

D6

C4

D9

E2

H6

T7

Y2

H3

AN24AN27AN28

E27

H12

B11K7B14

C22

K2

C24

D12

C10

C19

AN2

D18

F7

D21

E11

Y5

L28

E14

H7H8

H28

H9AN23AN20

J4

K5

J7

L25

D24

E28

F10F13F16

F22F4

E17

F19

C16

H13H14

H17H18H19H20

H21H22

H10

H23H24H25

B17

H26

B20

E8

H27

L3

B24

L23

L24

H11

L26L27

Y7

D15

L29

L30

C7

P23

W7

P25

W4

P26P27

V6

P28

P29

V3

P30

R23R24

U7

R25R26

R27R28R29

E25

T6

V23V24

T3

P24

J1000

AN10

AA24AA25

AA26AA27

AN13

AA28

AM4

AA29

AA30

AB23AB24AB25

AN16

AB26

AB1

AB27

AN17

AB28AB29AB30

AK24

AJ27

AH1

AE26

AJ4

A9

A6

A2A18

AF13

AE10

AF16AF17

AG24

AF23AF24AF25AF26

AF27

AL7 AJ7AH7

AK7

AF7

AK23

AL10

AF28

AE16

AN1

AF29

AL17

AL13

AM1

AM27

AK20

AK16

AL20

AK13

AL24

AL16

AM24

AE24

AF10

AE30AE29

AF30

AE28

A12

AL23

AK30

AG7

AE13

AJ23

AM10

AK10

AH3

AJ17

AK29

AF6

AG10

AE17

AJ16

AK5

AF3

AJ10

AJ30

AH24

AM13

AE7

AH23

AE5

AH20

AH17

AK17

AH16

AD7

AH13

AJ28

AE27

AG13

AE25

AM16

AH6

AC7AC6AC3

AM17

AG16

AJ24

AB7

AA6

AG17

AA7

AA3

AM20

AK28

AK27

AJ29

AE2

A21

AH10

A15

AM23

AG20

AD4

AL27

AG23

AJ20

AJ13

AM28

AF20

AK2

AL28

AA23

AE20

J1000

F27

AA1J1

D30

D29D28D27D26

D25C30C29C28C27

C26C25B30B29

B28B27B26B25

A30A29A28A27

A26A25

B23

AN4

AN6

AN7

AM7AM5AL4AK4

AL6AM3AL5AM2

D23

AM15

AD23

AF11

AK15

AG27

J21

J18

J26

AL15

AF18

AD29

AH15

AN9

AG26

AJ15

J10

AK26

AG11

AN29

AK22

AF22

AL29

AF9

N26

AG9

AN12

AK8

T27

AJ19

U26

AJ8

AN15

AG8

AL22

AH12

N28

T26

AM8

AL19

K23

P8

K25

J11

AA8

J29

AH9

AJ25

AL30

N29

AG14

AK11

AJ9

AL12

AH25

AG18

AN30

AL14

K30

AJ11

AL11

AM11

AJ21

AG30

AK21

AK14

J30

Y24

AF21

AD30

AL9

AG19

J27

J12

W28

T28

J13

AF14

J24

AM12

AL26

AG28

AH27

AH29

AH19

J15

AL8

AE11

AE12

AM26

K29

AG22

AJ14

AB8

AM19

AM18

AC27

J23

U24

M29

AC29

Y26

AD28

AH11

AN14

Y30

W30

AC25

AL18

Y28

T25

W25W24W23

AK9

M27

Y25

Y27

AN18

AN11

AN25

AN26

Y23

AC23

AC24

U29

M28

W29

N23

AE14

AC8

AF15

AM9

T30

J28

J8

AC26

AF12

W26

AE18

N25

AC28

T8

AN21

M24

K27

M30

AE15

N8

AC30

AE19

AM30

AE21

K8

V8

AN19

AE22AE23

AD24

AF19

K28

U28

AM22

N27

AG29

M23

U23

AD27

AJ12

Y8

K26

U25

L8

M26

M25

AM29

AJ26

AD26

N30

M8

AD25

J14

AM21

AG21

T24

J22

AG15

AK19

AK25

Y29AE9

AM25

AN22

AM14

T29

AH22

AK12

AH21

AH28

K24

AD8AK18

U8

N24

R8

T23

AH14

AN8

AL25

W27

AH26

AH18

J20

AJ22

AH8

AG12

AH30

J19

AJ18

AG25

AL21

U30

J25

AF8

W8

J9

U27

C23

A23

AN3AN5

J1000

2

1 C1200

2

1 C1201

2

1 C12812

1 C1280

2

1 C1210

2

1 C12132

1C1211

2

1 C1212

21

R1211

21

R121021

L1210

2

1 C12382

1 C12372

1 C1236

2

1 C12352

1 C12342

1 C1226

CPU_VCC_PKG_SENSE_PCPU_VCC_SENSE

CPU_VID_SELECT

PPCPU_VTT_OUT_RIGHT

=PPVCORE_S0_CPU

PPCPU_VTT_OUT_RIGHT

MIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWR

MIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

CPU_VID_SELECT

=PPVTT_S0_FSB_CPU

TP_CPU_VSS_SENSE

=PPVTT_S0_FSB_CPU

CPU_VID<4>

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

CPU_VCCIOPLL

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmVOLTAGE=1.2V

CPU_VCCA

CPU_VID<3>


VOLTAGE=1.2VPPCPU_VTT_OUT_LEFT

NET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

PPCPU_VTT_OUT_LEFT


CPU_VCCA_FLTCPU_VID<0>

CPU_VSSA

CPU_VID<6>CPU_VID<5>

CPU_VID<2>

CPU_VCCIOPLL

CPU_VCCA

PPCPU_VTT_OUT_RIGHT

TP_VTT_SEL

CPU_VID<1>

CPU_VCC_PKG_SENSE_N

CPU_VID<7>

=PPVTT_S0_FSB_CPU

MAX_NECK_LENGTH=3 MMNET_SPACING_TYPE=PWRMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

CPU_VSSAVOLTAGE=0V


CPU POWER, GND, DECAPS

CERM402

20%0.1UF10V

20%

40210VCERM

0.1UFCERM10V402

20%0.1UF

40210V20%CERM

0.1UF

402

0.1UF10V20%CERM

10V20%0.1UFCERM402

MF-LF1/16W5%680

402


CPU

CRITICAL


CPU

CRITICAL

100 71


CPU

CRITICAL

20%0.1UF10VCERM402

0.1UF

CERM402

20%10V

0.01UFCERM10%16V

402

20%10UFX5R6.3V

603

22UF20%6.3VCERM-X5R805-3

20%

603

10uF

X5R6.3V

6.3VCERM402

10%1UF

NOSTUFF

402CERM

10%1UF6.3V

NOSTUFF

0

5%1/10WMF-LF603

1/10W

0

603

5%

MF-LF

CONROE

0603

FERR-120-OHM-0.2A

100 71

100 71

108 53

100 71

100 71

100 71

100 71

100 71

100 71

100 71

12

12 11 10

6

12 11 10

12

12 11 6

12 11 6

12

12

12 6

12 11 10

12 11 10

12 6

12

12

12

12 11 10

12 11 6

12

IN

BI

BI

BI

BI

OUT

IN

BI

IN

IN

IN

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

NC

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PWRGD/HOOK0

OBSDATA_A3OBSDATA_A2

TRSTn

DBR#/HOOK7RESET#/HOOK6

OBSFN_D1OBSFN_D0

OBSDATA_C1OBSDATA_C0

OBSFN_C1OBSFN_C0

OBSDATA_C2OBSDATA_C3

OBSDATA_B3

OBSDATA_D1

OBSDATA_A1

MCP79-specific pinout

OBSFN_A1

HOOK3

OBSFN_B1

OBSDATA_B2

TDO

TDI

XDP_PRESENT#TMSTCK0

TCK1SCL

SDA

OBSDATA_B1OBSDATA_B0

OBSFN_A0

HOOK1

OBSDATA_D0

VCC_OBS_CD

OBSDATA_A0

OBSFN_B0

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

HOOK2

VCC_OBS_AB

13 OF 110

051-7845

A.0.0


2

1R1301

2

1R1316

9

8 7

60

6

59

58 57

56 55

54 53

52 51

50

5

49

48 47

46 45

44 43

42 41

40

4

39

38 37

36 35

34 33

32 31

30

3

29

28 27

26 25

24 23

22 21

20

2

19

18 17

16 15

14 13

12 11

10

1

J1300

21

R1303

2

1 C1301

2

1C1300

2

1R1315

21

R1399

TP_XDP_OBSFN_B0

FSB_CLK_ITP_P

CPU_XDP_TDO

XDP_CPURST_L

FSB_CLK_ITP_N

JTAG_MCP_TDIJTAG_MCP_TMS

MCP_DEBUG<3>MCP_DEBUG<2>

MCP_DEBUG<1>MCP_DEBUG<0>

JTAG_MCP_TRST_LJTAG_MCP_TDO

=PP3V3_S0_XDP

CPU_XDP_BPMB<1>

CPU_XDP_BPMB<3> MCP_DEBUG<4>MCP_DEBUG<5>

CPU_XDP_BPM_L<0>

CPU_XDP_BPM_L<2>

CPU_XDP_BPM_L<1>

CPU_XDP_BPM_L<4>

CPU_XDP_TMSCPU_XDP_TDI

MCP_DEBUG<6>

FSB_CPURST_L

MCP_DEBUG<7>

CPU_XDP_BPM_L<5>

CPU_PWRGD

CPU_XDP_BPM_L<3>

=PPVTT_S0_XDP

TP_XDP_OBSFN_B1

XDP_DBRESET_L

XDP_PWRGD

JTAG_MCP_TCKPM_LATRIGGER_L

SMBUS_MCP_0_CLK CPU_XDP_TRST_L

CPU_XDP_TCK

SMBUS_MCP_0_DATA

XDP_OBS20

CPU_XDP_BPMB<0>

CPU_XDP_BPMB<2>


eXtended Debug Port (XDP)

51

402

5%

XDP

1/16WMF-LF

100 11

100 11

100 11

100 11

MF-LF1/16W

XDP

625%

402

19

28 11

100 11

100 11

100 11

100 11

100 14

100 14

21

21

19

19

19

19

19

19

19

19

21

21

21

100 11

100 11

100 11

100 11

LTH-030-01-G-D-A-TR

XDP_CONNCRITICAL

F-ST-SM

5%1/16W

XDP

1K

402

PLACEMENT_NOTE=Place close to CPU to minimize stub.

MF-LF

100 14 10

100 11

100 11

100 11

X5R16V

402

10%0.1uF

XDP

16V

402X5R

10%0.1uF

XDP

XDP

MF-LF1/16W

1%54.9

402

106 52 21

106 52 21

XDP

1/16W5%

MF-LF

1K

402

100 14 11

100

6

6

IN

IN

IN

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

CPU_ADSTB0*

CPU_BPRI*

CPU_A25*CPU_A24*

CPU_D4*

BCLK_OUT_CPU_N

BCLK_VML_COMP_GNDBCLK_VML_COMP_VDD

CPU_A14*CPU_A15*

CPU_A10*CPU_A11*

CPU_A13*

CPU_A12*

CPU_A16*

CPU_A31*

CPU_A18*

CPU_A30*

CPU_A26*

CPU_A33*

CPU_A21*CPU_A20*

CPU_A23*

CPU_A19*

CPU_A22*

CPU_A28*CPU_A29*

CPU_A7*

CPU_A17*

CPU_A27*

CPU_A35*

CPU_A34*

CPU_A32*

CPU_REQ2*

CPU_A9*

CPU_REQ3*

CPU_A4*

CPU_A8*

CPU_A3*

CPU_ADSTB1*

CPU_BSEL0CPU_BSEL1

CPU_BSEL2

CPU_COMP_GNDCPU_COMP_VCC

CPU_D1*

CPU_D3*

CPU_D15*

CPU_D11*CPU_D10*

CPU_D8*

CPU_D13*

CPU_D9*

CPU_D23*

CPU_D19*

CPU_D21*

CPU_D22*

CPU_D2*

CPU_D18*

CPU_D20*

CPU_D17*

CPU_D31*

CPU_D28*CPU_D27*

CPU_D25*CPU_D26*

CPU_D24*

CPU_D7*

CPU_D30*CPU_D29*

CPU_D38*

CPU_D33*CPU_D32*

CPU_D39*

CPU_D37*CPU_D36*

CPU_D5*

CPU_D42*

CPU_D44*

CPU_D43*

CPU_D40*CPU_D41*

CPU_D45*

CPU_D49*

CPU_D55*

CPU_D6*

CPU_D50*

CPU_D53*CPU_D52*

CPU_D51*

CPU_D48*

CPU_D54*

CPU_D59*

CPU_D57*

CPU_D62*

CPU_D58*

CPU_D0*

CPU_D61*

CPU_D60*

CPU_D63*

CPU_D56*

CPU_D14*

CPU_D12*

CPU_DBI1*

CPU_DBI2*

CPU_DPRSTP*

CPU_DPSLP*CPU_DPWR*

CPU_DSTBN0*

CPU_DSTBN2*

CPU_DSTBN3*

CPU_DSTBP0*

CPU_DSTBP1*

CPU_DSTBP2*

CPU_DSTBP3*

CPU_FERR*

CPU_HIT*

CPU_LOCK*

CPU_NMI

CPU_PECICPU_PROCHOT*

CPU_REQ0*

CPU_REQ1*

CPU_A6*

CPU_RESET*

CPU_RS0*

CPU_RS1*CPU_RS2*

CPU_SLP*

CPU_SMI*

CPU_THERMTRIP*

CPU_TRDY*

V1P1_DLLDLCELL_AVDD

V1P1_PLL_CPU

V1P1_PLL_FSBV1P1_PLL_MCLK

CPU_D16*

CPU_D47*CPU_D46*

CPU_A5*

CPU_DBI3*

CPU_D35*

CPU_D34*

BCLK_OUT_ITP_N

CPU_DEFER*

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_IN_N

BCLK_OUT_NB_NBCLK_OUT_NB_P

CPU_INIT*

BCLK_IN_P

CPU_A20M*CPU_IGNNE*

CPU_INTR

CPU_PWRGD

CPU_STPCLK*

CPU_BR0*CPU_BR1*

CPU_DBSY*CPU_DRDY*

CPU_HITM*

CPU_BNR*CPU_ADS*

CPU_REQ4*

CPU_DBI0*

CPU_DSTBN1*

FSB

(1 OF 11)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

20 mA29 mA

15 mA

206 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Loop-back clock for delay matching.

270 mA (A01)

NC

14 OF 110

051-7845

A.0.0


2

1R1420

2

1R1421

2

1R1422

AH27AG28AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42AB41AC41

H38

AC39AC37

AE38AA33AC38

AH43

AJ41E41

AG41

AC43

AF42AH42

AH39

AD40AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32AN33

AN32

AA40

AD39

J41

N35

V35

V41

T43T41W41

H39

H43K41J40

V42

H41H42

L41M43M42K42

N41N40M40P41

Y39

L42H40J39J38J37

L39L38L37N38

N36

Y42

R39N33R37

R38N34P35R34

R35U38R33

W42

U37U36

U35U34U33W38

W35W34W33AA34

Y40

AA37AA36AA35AA38R42

P42R41U41T39

T42

Y43Y41

AM43

AM42

F42D42F41

AL32AE40

AA41

AD43

AK35AE36

AD42

AE34AE35AC34AC35

AC33AE37

AN34AR39AN36AN35

AN38AL33

AB35

AN37AL34AL35

AJ33AL38AL39AJ36

AL37AJ35

AF41

AJ37AJ38

AG33AJ34AG34AG35

AF35AG37AG38AE33AG39

AM39AM40

AL41AK42

AL43AL42

G42

G41

AJ40AK41

U1400

2

1R1416

2

1R1440

2

1R1410

2

1R1435

2

1R1430

2

1R1431

2

1R1436

=PP1V05_S0_MCP_FSB

CPU_FERR_L

=PP1V05_S0_MCP_FSB

FSB_ADSTB_L<0>

FSB_DEFER_LFSB_BPRI_L

FSB_A_L<25>

FSB_D_L<4>

FSB_CLK_CPU_NFSB_CLK_CPU_P

FSB_CLK_ITP_NFSB_CLK_ITP_P

FSB_CLK_MCP_N

FSB_CLK_MCP_P

FSB_A_L<14>

FSB_A_L<11>


FSB_A_L<16>

FSB_A_L<31>

FSB_A_L<18>

CPU_A20M_L

FSB_A_L<26>

FSB_A_L<33>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<28>

FSB_A_L<7>

FSB_A_L<27>


FSB_A_L<32>

FSB_REQ_L<2>

FSB_A_L<9>

FSB_REQ_L<3>

FSB_A_L<4>

FSB_A_L<8>

FSB_A_L<3>

FSB_ADS_L

FSB_ADSTB_L<1>

FSB_BNR_LFSB_BREQ0_L

FSB_D_L<1>

FSB_D_L<3>

FSB_D_L<15>


FSB_D_L<8>

FSB_D_L<13>

FSB_D_L<9>

FSB_D_L<23>

FSB_D_L<19>


FSB_D_L<2>

FSB_D_L<18>

FSB_D_L<20>

FSB_D_L<17>

FSB_D_L<31>



FSB_D_L<24>

FSB_D_L<7>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<35>

FSB_D_L<38>


FSB_D_L<34>

FSB_D_L<39>


FSB_D_L<5>



FSB_D_L<49>

FSB_D_L<55>

FSB_D_L<6>

FSB_D_L<50>


FSB_D_L<48>

FSB_D_L<54>

FSB_D_L<59>

FSB_D_L<57>

FSB_D_L<62>

FSB_D_L<58>

FSB_D_L<0>


FSB_D_L<63>

FSB_D_L<56>

FSB_D_L<14>

FSB_D_L<12>

FSB_DINV_L<0>

FSB_DINV_L<1>

FSB_DINV_L<2>

FSB_DBSY_L

CPU_DPRSTP_L

FSB_DRDY_L

FSB_DSTB_L_N<0>

FSB_DSTB_L_N<1>

FSB_DSTB_L_N<2>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0>

FSB_DSTB_L_P<1>

FSB_DSTB_L_P<2>

FSB_DSTB_L_P<3>

FSB_HITM_LFSB_LOCK_L

CPU_PECI_MCP

FSB_REQ_L<0>FSB_REQ_L<1>

FSB_REQ_L<4>

FSB_A_L<6>

FSB_CPURST_L

FSB_RS_L<0>

CPU_STPCLK_L

FSB_D_L<16>

FSB_D_L<47>

FSB_D_L<46>

FSB_A_L<5>

FSB_DINV_L<3>

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<17>

FSB_A_L<23>

CPU_PWRGD

CPU_SMI_LCPU_NMICPU_INTR

CPU_IGNNE_L

FSB_D_L<45>

FSB_D_L<42>

FSB_A_L<24>

MCP_CPU_COMP_GND

MCP_BCLK_VML_COMP_GND

MCP_BCLK_VML_COMP_VDD

FSB_CPUSLP_LCPU_DPSLP_L

MCP_CPU_COMP_VCC

PP1V05_S0_MCP_PLL_FSB

FSB_RS_L<2>FSB_RS_L<1>

FSB_HIT_L

CPU_BSEL<2>CPU_BSEL<1>CPU_BSEL<0>



PM_THRMTRIP_L

CPU_PROCHOT_L

FSB_TRDY_L

FSB_BREQ1_L

CPU_INIT_L

MCP CPU InterfaceSYNC_MASTER=MASTER SYNC_DATE=N/A

402

470

MF-LF1/16W

5%1/16WMF-LF

5%470

402

1/16WMF-LF

5%470

402

OMIT

BGAMCP7A

5%62

MF-LF402

1/16W

5%

MF-LF402

1/16W

150

NO STUFF

1/16WMF-LF402

625%

MF-LF402

1%1/16W

49.9

1/16W1%

402MF-LF

49.9

49.9

MF-LF402

1%1/16W

MF-LF402

1%1/16W

49.9

100 10

100 10

100 50 11

100 50 11

108 55

100 11

100 10

100 11

100 11

100 13 11

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 13

100 13

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 10

100 13 10

100 10

100 11

100 11

100 11

25 22 14 6

25 22 14 6

100

100

100

100

100

100

25

100

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

MDQ0_1

MDQ0_2MCLK0A_1_N

MCLK0A_0_P

MCS0A_0*

MDQ0_63MDQ0_62

MDQ0_61

MDQS0_1_P

MDQS0_0_P

MDQ0_57

MDQ0_41MDQ0_40

MDQ0_28

MDQ0_42MDQ0_43MDQ0_44

MDQ0_45MDQ0_46MDQ0_47MDQ0_48

MDQ0_49

MDQ0_38

MA0_0MA0_1

MA0_10MA0_11MA0_12

MA0_13MA0_14

MA0_2

MA0_4MA0_5MA0_6MA0_7

MA0_8MA0_9

MBA0_0MBA0_1MBA0_2

MCAS0*

MCKE0A_0MCKE0A_1

MCLK0A_0_N

MCLK0A_1_P

MCLK0A_2_NMCLK0A_2_P

MCS0A_1*

MDQ0_0

MDQ0_10MDQ0_11MDQ0_12MDQ0_13MDQ0_14




MDQ0_27

MDQ0_29

MDQ0_3

MDQ0_30MDQ0_31


MDQ0_36MDQ0_37

MDQ0_39

MDQ0_4MDQ0_5

MDQ0_55MDQ0_56

MDQ0_58MDQ0_59

MDQ0_6

MDQ0_60

MDQ0_7

MDQ0_9

MDQM0_0MDQM0_1MDQM0_2MDQM0_3


MDQS0_0_N

MDQS0_1_N

MDQS0_2_N

MDQS0_2_PMDQS0_3_NMDQS0_3_PMDQS0_4_NMDQS0_4_P

MDQS0_5_NMDQS0_5_PMDQS0_6_NMDQS0_6_P

MDQS0_7_NMDQS0_7_P

MODT0A_0

MODT0A_1

MRAS0*

MWE0*

MDQ0_54MDQ0_53


MA0_3

MDQ0_19

MDQ0_8 0A

MEMORYCONTROL

MEMORY PARTITION 0

(2 OF 11)

MDQ1_43

MA1_0MA1_1

MA1_10MA1_11MA1_12

MA1_13MA1_14

MA1_2MA1_3

MA1_4MA1_5MA1_6MA1_7

MA1_8MA1_9

MBA1_0MBA1_1MBA1_2

MCAS1*

MCKE1A_0

MCS1A_0*

MDQ1_0MDQ1_1



MDQ1_19

MDQ1_2




MDQ1_3

MDQ1_30MDQ1_31



MDQ1_4


MDQ1_44


MDQ1_49

MDQ1_5



MDQ1_58MDQ1_59

MDQ1_6

MDQ1_61

MDQ1_62MDQ1_63

MDQ1_7MDQ1_8MDQ1_9



MDQS1_0_N

MDQS1_0_PMDQS1_1_NMDQS1_1_P

MDQS1_2_PMDQS1_3_NMDQS1_3_PMDQS1_4_NMDQS1_4_P

MDQS1_5_NMDQS1_5_PMDQS1_6_NMDQS1_6_P

MDQS1_7_NMDQS1_7_P

MODT1A_1

MRAS1*

MWE1*

MDQ1_60

MDQS1_2_N

MCLK1A_2_PMCLK1A_2_N



MCS1A_1*

MODT1A_0

MCKE1A_1

MEMORYCONTROL

1A

MEMORY PARTITION 1

(3 OF 11)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 110

051-7845

A.0.0


BA16

AW16

BB13AY15

AT2AT1AY2AY1

BB6BA6BA10AY11

BB33BA33BB37BA37

BA43AY42AT42AT43

AT5BA2

AY7BA11BB34BB38

AY43AR42

AW42

AW41AT40

AT4AT3AV2AV3

AT41

AR4AR3AU2AU3

AY4AY3BB3BC3

AW4AW3

AP41

BA3BB2BB5

BA5BA8BC8BB4

BC4BA7AY8

AN40

BA9

BB10BB12AW12BB8BB9

AY12BA12BC32AW32

AU40

BA35AY36BA32BB32

BA34AY35BC36AW36

BA39AY40

AU41

BA36BB36BA38

AY39BB40AW40AV42

AV41BA40BC40

AR41AP42

BB14BB16

BA42

BB42

BB22

BA22

BA19AY19

AY31BB30

BA15

BB29

BB18BB17

BB28AY28BA28

AY27BA27BA26BB26

BA25

BA29BA14AW28BC28

BA17

BB25BA18

U1400

AR17

AV17

AP15AV15

AL10AL11AR8AR9

AW7AW8AP13AR13

AV25AW25AU30AU29

AT35AU35AU39AT39

AN5AU5

AR10AN13AN27AW29

AV35AR34

AT37

AU37AW39

AL8AL9AP9AN9

AV39

AL6AL7AN6AN7

AR6AR7AV6AW5

AN10AR5

AR37

AU6AV5AU7

AU8AW9

AP11AW6

AY5AU9AV9

AR38

AU11

AV11AV13AW13AR11AT11

AR14AU13AR26AU25

AV38

AT27AU27AP25AR25

AP27AR27AP29AR29

AP31AR31

AW38

AV27AN29AV29

AN31AU31AR33AV37

AW37AT31AV31

AR35AP35

AT15AR18

AW33

AV33

BA24

AY24

BB20BC20

AU23AT23

AP17

AP23

AP19AW17

AV21AR22AU21

AP21AR21AN21AV19

AU19

AR23AU15AN23AW21

AN19

AT19AR19

U1400

MEM_A_DQ<9>MEM_A_DQ<8>

MEM_A_ODT<1>

MEM_B_DQ<43>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<10>MEM_B_A<11>MEM_B_A<12>MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<2>MEM_B_A<3>MEM_B_A<4>

MEM_B_A<5>MEM_B_A<6>MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>

MEM_B_BA<0>

MEM_B_BA<1>MEM_B_BA<2>

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_DQ<1>

MEM_B_DQ<10>

MEM_B_DQ<11>MEM_B_DQ<12>MEM_B_DQ<13>MEM_B_DQ<14>MEM_B_DQ<15>

MEM_B_DQ<16>MEM_B_DQ<17>MEM_B_DQ<18>MEM_B_DQ<19>

MEM_B_DQ<2>



MEM_B_DQ<29>

MEM_B_DQ<3>

MEM_B_DQ<30>MEM_B_DQ<31>MEM_B_DQ<32>



MEM_B_DQ<4>

MEM_B_DQ<40>MEM_B_DQ<41>

MEM_B_DQ<42>



MEM_B_DQ<5>



MEM_B_DQ<59>

MEM_B_DQ<6>


MEM_B_DQ<63>


MEM_B_DM<0>

MEM_B_DM<1>MEM_B_DM<2>MEM_B_DM<3>MEM_B_DM<4>

MEM_B_DM<5>MEM_B_DM<6>MEM_B_DM<7>

MEM_B_DQS_N<0>MEM_B_DQS_P<0>

MEM_B_DQS_N<1>MEM_B_DQS_P<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>MEM_B_DQS_P<3>MEM_B_DQS_N<4>MEM_B_DQS_P<4>MEM_B_DQS_N<5>

MEM_B_DQS_P<5>MEM_B_DQS_N<6>MEM_B_DQS_P<6>MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_ODT<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_DQ<60>

MEM_B_DQS_N<2>

TP_MEM_B_CLK2PTP_MEM_B_CLK2N

MEM_B_CLK_P<1>MEM_B_CLK_N<1>


MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_A_DQ<55>


MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CS_L<0>

MEM_A_DQ<63>


MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQ<57>


MEM_A_DQ<28>

MEM_A_DQ<42>MEM_A_DQ<43>MEM_A_DQ<44>MEM_A_DQ<45>


MEM_A_DQ<38>

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<10>MEM_A_A<11>MEM_A_A<12>MEM_A_A<13>

MEM_A_A<14>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<5>MEM_A_A<6>MEM_A_A<7>MEM_A_A<8>MEM_A_A<9>

MEM_A_BA<0>

MEM_A_BA<1>MEM_A_BA<2>

MEM_A_CAS_L

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<1>

TP_MEM_A_CLK2NTP_MEM_A_CLK2P

MEM_A_CS_L<1>

MEM_A_DQ<0>

MEM_A_DQ<10>

MEM_A_DQ<11>MEM_A_DQ<12>MEM_A_DQ<13>MEM_A_DQ<14>MEM_A_DQ<15>

MEM_A_DQ<16>MEM_A_DQ<17>MEM_A_DQ<18>



MEM_A_DQ<29>

MEM_A_DQ<3>

MEM_A_DQ<30>MEM_A_DQ<31>MEM_A_DQ<32>


MEM_A_DQ<37>

MEM_A_DQ<39>


MEM_A_DQ<56>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<6>

MEM_A_DQ<60>

MEM_A_DQ<7>

MEM_A_DM<0>

MEM_A_DM<1>MEM_A_DM<2>MEM_A_DM<3>MEM_A_DM<4>

MEM_A_DM<5>MEM_A_DM<6>MEM_A_DM<7>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<2>MEM_A_DQS_P<2>

MEM_A_DQS_N<3>MEM_A_DQS_P<3>MEM_A_DQS_N<4>MEM_A_DQS_P<4>MEM_A_DQS_N<5>

MEM_A_DQS_P<5>MEM_A_DQS_N<6>MEM_A_DQS_P<6>MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_ODT<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<54>


MEM_A_A<3>

MEM_A_DQ<19>

MEM_B_DQ<0>

MEM_B_ODT<0>

MEM_B_CKE<0>

MCP Memory InterfaceSYNC_MASTER=MASTER SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGAMCP7A

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 32

101 32

101 32

101 32

101 32

101 32

101 33

101 33

101 33

101 33

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 32

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 31

101 31

101 31

101 31

101 31

101 31

101 33

101 33

101 33

101 33

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 31

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

101 33

8

8 8

8

MRESET0*

MCLK0B_0_P

MCLK0B_1_P MCLK1B_1_P

MCLK1B_2_P

GND

MCKE1B_0MCKE1B_1

MCLK0B_2_NMCLK0B_2_P

MCLK1B_0_NMCLK1B_0_P

MCLK1B_1_N

MCS0B_0* MCS1B_0*MCS1B_1*

MODT0B_1 MODT1B_1

V1P1_PLL_DP

V1P8_MEM_VDDPGND

MEM_COMP_1P8V

MEM_COMP_GND

V1P1_PLL_XREF_XS

V1P1_PLL_CORE

V1P1_PLL_V

MCKE0B_1

MODT0B_0

MCLK0B_0_N

MCLK0B_1_N

MODT1B_0

MCLK1B_2_N

MCS0B_1*

MCKE0B_0 MEMORY CONTROL 1B

MEMORY CONTROL 0B

(4 OF 11)

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA12 mA


19 mA

39 mATP or NC for DDR2.

87 mA (A01)

16 OF 110

051-7845

A.0.0


AR16

AV16AP24AP20AN22

BC29

AN16AM29AM27AM25

AP16

AM31

AL30BC25AW24AW19

AY26AM23AY25AU18

AM15

AT17

AY18AY17AV20BC17

AW27AU22AU20AM21

AV24AY29

AN24

AT21AU24

AN18AU16AP18AP22AW15

AR24AM19AR20

AN20

AM17

T27

T28U28U27

AY32

BC13AY16

AN15AN17

AM41AN41

BA13

BC16

AR15

AU17

BA41

BB41

AY23BA23

BA20AY20

AU33

AU34

BB24BC24

BA21BB21

BA31BA30

AN25AV23

W5V34

V10

U22U20U18T9

T7

T6

T38T37T35

T34T33

T26T24

AK11T20

T18

T10

R5R43R40

R36P7P40P4

P37P34P33

P10

N8N39

M9M7M6M5

M38K7H31G32

G30

F24D34BC9AY9

BC21

F28AU10AR36AP30

AT25

AP12

AM28AK7

AH35

AG24AF24AE20AD22AB7

AB22AA39

AA22

U1400

2

1R1611

2

1R1610MCP_MEM_RESET_L

MEM_B_CKE<3>

MEM_A_CLK_P<3>

MEM_A_CLK_P<4> MEM_B_CLK_P<4>

TP_MEM_B_CLK5P

MEM_B_CKE<2>

TP_MEM_A_CLK5P

MEM_B_CLK_N<4>

MEM_B_CS_L<3>

MEM_A_ODT<3> MEM_B_ODT<3>

MEM_A_CKE<3>

MEM_A_CLK_N<3>

MEM_B_ODT<2>

TP_MEM_B_CLK5N

MEM_A_CS_L<3>

MEM_A_CKE<2>


MEM_A_CS_L<2>

MEM_A_ODT<2>

MEM_A_CLK_N<4>

TP_MEM_A_CLK5N

PP1V05_S0_MCP_PLL_CORE



MEM_B_CS_L<2>

MCP_MEM_COMP_VDDMCP_MEM_COMP_GND


MCP MEMORY CNTRL & MISC

33

40.2

MF-LF

1%1/16W

402

1%40.2

1/16W

402MF-LF

MCP7ABGA

OMIT

101 32

101 33

101 33 101 33

8

101 32

8

101 33

101 32

101 31 101 32

101 31

101 33

101 32

8

101 31

101 31

30 25 16 6

101 31

101 31

101 33

8

25

30 25 16 6

101 33

101 33

101 32

101

101

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

PEB_CLKREQ*/GPIO_49

PEB_PRSNT*

PE0_RX13_N

PE0_RX14_P

PEE_CLKREQ*/GPIO_16

V1P1_PEX_AVDD0

V1P1_PEX_AVDD1

V1P1_PEX_DVDD0

V1P1_PEX_DVDD1

V1P1_PLL_PEX

PE_WAKE*

PE0_PRSNT_16* PE0_REFCLK_NPE0_REFCLK_P

PE0_RX0_NPE0_RX0_P

PE0_RX1_NPE0_RX1_P

PE0_RX10_NPE0_RX10_P



PE0_RX13_P

PE0_RX14_N


PE0_RX2_NPE0_RX2_P

PE0_RX3_N

PE0_RX3_P

PE0_RX4_P

PE0_RX6_NPE0_RX6_P

PE0_RX7_N

PE0_RX7_P

PE0_RX8_NPE0_RX8_P

PE0_RX9_NPE0_RX9_P

PE0_TX0_NPE0_TX0_P

PE0_TX1_NPE0_TX1_P

PE0_TX10_P

PE0_TX11_NPE0_TX11_P





PE0_TX2_NPE0_TX2_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_NPE0_TX4_P

PE0_TX5_N

PE0_TX5_P

PE0_TX6_NPE0_TX6_P

PE0_TX7_N

PE0_TX7_P

PE0_TX8_NPE0_TX8_P

PE0_TX9_NPE0_TX9_P

PE1_REFCLK_N

PE1_REFCLK_P

PE1_RX0_NPE1_RX0_P

PE1_RX1_NPE1_RX1_P

PE1_RX2_NPE1_RX2_P

PE1_RX3_N

PE1_RX3_P

PE1_TX0_NPE1_TX0_P

PE1_TX1_NPE1_TX1_P

PE1_TX2_NPE1_TX2_P

PE1_TX3_N

PE1_TX3_P

PE3_REFCLK_NPE3_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P



PEC_CLKREQ*/GPIO_50PEC_PRSNT*

PED_CLKREQ*/GPIO_51PED_PRSNT*

PEE_PRSNT*/GPIO_46

PEF_CLKREQ*/GPIO_17PEF_PRSNT*/GPIO_47

PEX_CLK_COMP

PEX_RST0*

PE0_RX5_P

PE0_RX5_N

PE0_RX4_N

PE0_TX10_N


PEG_PRSNT*/GPIO_48PEG_CLKREQ*/GPIO_18

PCI EXPRESS

(5 OF 11)

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU


84 mA (A01)

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Minimum 1.025V for Gen2 support

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Int PU

Int PU

Int PU

57 mA (A01, DVDD0 & 1)


Int PU

17 OF 110

051-7845

A.0.0


T16

U19T19

U16W18W17W16V19

U17W19T17

P13

N13M13

R12P12

M12AB12AA12W12V12

AD12

U12

T12N12

AC12Y12

K11

A11

M19M17

M18M16

L18L16

B10

M15

C10E8

D9D5

F17

N14M14

L14K14

J13H13

G13

F13

J11J10

B6C6

A7B7

B8A8

D8C8

H7G7

F9E9

H9G9

K9J9

G11F11

H3H2

G3

H4

F3F4

E2

F2

D2E1

C1D1

B3B2

A4A3

C4B4

M2M1

M4M3

L4L3

K2K3

J2J3

H1

J1

C5D4

L11L10

J5

J4

J7J6

G5

H5

C3D3

E4E3

E5F5

E6F6

D7C7

N5N4

N7N6

N9P9

N11N10

L7L6

L9

L8

F7E7

E11

D11C9

U1400

2

1R1710

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

=PEG_R2D_C_N<10>

=PEG_D2R_N<4>

=PEG_D2R_N<5>=PEG_D2R_P<5>

PCIE_RESET_L

TP_PCIE_CLK100M_PE6PTP_PCIE_CLK100M_PE6N



TP_PCIE_CLK100M_PE4PTP_PCIE_CLK100M_PE4N

PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_N

TP_PCIE_PE4_R2D_CPTP_PCIE_PE4_R2D_CN

PCIE_EXCARD_R2D_C_P

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

TP_PCIE_PE4_D2RP

PCIE_EXCARD_D2R_P

PCIE_CLK100M_MINI_PPCIE_CLK100M_MINI_N

=PEG_R2D_C_P<9>=PEG_R2D_C_N<9>





=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<15>


=PEG_R2D_C_P<13>

=PEG_R2D_C_N<13>


=PEG_R2D_C_P<11>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<10>


=PEG_R2D_C_P<0>

=PEG_R2D_C_N<0>

=PEG_D2R_P<9>=PEG_D2R_N<9>




=PEG_D2R_P<4>



=PEG_D2R_N<14>

=PEG_D2R_P<13>


=PEG_D2R_P<11>

=PEG_D2R_N<11>



=PEG_D2R_N<0>

PEG_CLK100M_PPEG_CLK100M_N

=PP1V05_S0_MCP_PEX_AVDD1


PCIE_MINI_PRSNT_L


=PEG_D2R_P<0>


=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

MCP_PEX_CLK_COMP

PP1V05_S0_MCP_PLL_PEX

=PP1V05_S0_MCP_PEX_DVDD1

PCIE_EXCARD_D2R_N PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_D2RN

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

GMUX_JTAG_TDO

TP_PE4_CLKREQ_L

PCIE_FW_PRSNT_L

=PEG_D2R_P<15>

=PEG_D2R_N<15>

PEG_PRSNT_L

MINI_CLKREQ_L

FW_CLKREQ_L

EXCARD_CLKREQ_LPCIE_EXCARD_PRSNT_L

PCIE_WAKE_L

PCIE_MINI_D2R_P


TP_PE4_PRSNT_L

AUD_IP_PERIPHERAL_DET

GMUX_JTAG_TCK_L

CARDREADER_RESET

MCP PCIe InterfacesSYNC_MASTER=MASTER SYNC_DATE=N/A

47

MCP7ABGA

OMIT

67

8

8

9

2.37K

402MF-LF

1%1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

9

8

8

102 34

102 34

8

8

102 41

102 41

102 41

102 41

102 34

102 34

8

8

9

34

8

8

102 41

102 41

34

42

9

102 34

102 34

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

8

8

8

8

8

8

8

8

8

28

28 25

102

25

28

8

8

28 25

8

IN

BI

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

BI

XTALIN_TV

RGB_DAC_RSET

MII_COMP_GNDMII_COMP_VDD

V1P1_DUAL_MACPLL

MII_COL/GPIO_20/MSMB_DATA

BUF_25MHZ

DDC_CLK0

DDC_CLK2/GPIO_23

DDC_CLK3

DDC_DATA0

DDC_DATA2/GPIO_24

DDC_DATA3

DP_AUX_CH0_NDP_AUX_CH0_P

GPIO_6/FERR*/IGPU_GPIO6GPIO_7/NFERR*/IGPU_GPIO7

HDMI_RSET

HDMI_TXC_N/ML0_LANE3_NHDMI_TXC_P/ML0_LANE3_P

HDMI_TXD0_N/ML0_LANE2_N

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD1_N/ML0_LANE1_NHDMI_TXD1_P/ML0_LANE1_P

HDMI_TXD2_N/ML0_LANE0_NHDMI_TXD2_P/ML0_LANE0_P

HDMI_VPROBE

HPLUG_DET2/GPIO_22HPLUG_DET3

IFPA_TXC_NIFPA_TXC_P

IFPA_TXD0_NIFPA_TXD0_P

IFPA_TXD1_N



IFPAB_RSETIFPAB_VPROBE

IFPB_TXC_N

IFPB_TXC_P

IFPB_TXD4_N

IFPB_TXD4_P

IFPB_TXD5_NIFPB_TXD5_P

IFPB_TXD6_N

IFPB_TXD6_P

IFPB_TXD7_NIFPB_TXD7_P

LCD_BKL_CTL/GPIO_57

LCD_BKL_ON/GPIO_59LCD_PANEL_PWR/GPIO_58

MII_RESET*

MII_RXER/GPIO_36

MII_VREF

V3P3_DUAL_RMGT0V3P3_DUAL_RMGT1

V1P0_DUAL_RMGT_0V1P0_DUAL_RMGT_1

V3P3_PLL_HDMIV3P3_PLL_IFPAB

V3P3_RGBDAC_VDDV3P3_TVDAC_VDD

V1P1_HDMI_VDD

V1P8_IFPA_VDDV1P8_IFPB_VDD

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_RED

RGB_DAC_VREF

RGB_DAC_VSYNC

MII_MDCMII_MDIO

MII_PWRDWN/GPIO_37

MII_RXCLKMII_RXDV

MII_RXD0

MII_RXD1MII_RXD2MII_RXD3

MII_TXD0

MII_TXD1MII_TXD2

TV_DAC_BLUETV_DAC_GREEN

TV_DAC_HSYNC/GPIO_44

TV_DAC_RED

TV_DAC_RSET

TV_DAC_VREF

TV_DAC_VSYNC/GPIO_45

XTALOUT_TV

MII_TXENMII_TXCLK

MII_TXD3

RGB_DAC_GREEN

IFPA_TXD1_P

MII_CRS/GPIO_21/MSMB_CLK

MII_INTR/GPIO_35

DACS

LAN

FLAT PANEL

(6 OF 11)

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

LVDS: Power +VDD_IFPx at 1.8VDual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: HDMI port requires level-shifting. IFP interface can

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

TP_DP_IG_AUX_CHP/NTMDS_IG_HPD

TMDS_IG_DDC_CLKTMDS_IG_TXD_P/N<2>TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXD_P/N<1>=MCP_HDMI_TXD_P/N<2>

be used to provide HDMI or dual-channel TMDS without

DP_IG_DDC_DATADP_IG_DDC_CLK

Interface Mode

level-shifters.

DP_IG_AUX_CH_P/N

NOTE: 20K pull-down required on DP_HPD_DET.

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)103 mA103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals.DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

TMDS_IG_DDC_DATA

MCP Signal

=MCP_HDMI_DDC_CLK=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

8 mA8 mA

16 mA (A01)

95 mA (A01)


TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

DP_IG_AUX_CH_P/NDP_IG_HPD

DP_IG_ML_P/N<0>

(See below)

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are lowby default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

18 OF 110

051-7845

A.0.0


D38C38

K32J32

M28M29

K24J24

M26M27

T25

T23

V23U23

C37

A35E36

A36

D36

B36

C36

A41

B38C39

B39

A40

A39

B40

E28

C26

D25C25

C24B24

D24F23

C22

A24

E24B23C23

A23

J23

G23

C21D21

J22

B22

C27

B27

B26

F40E37G39

N30

M30

L30K30

L29K29

J29H29

L31K31

G31E32

B34C34

D33C33

D32C32

B32

A32

B35C35

F31C31

J30

J33H33

F33

G33

G35F35

D35E35

J31

B15E16

D43C43

E31

B30

A31

D31

C30

B31

E23

U1400

2

1R1820

2

1R1860

2

1R1861

2

1R1850

2

1R1811

2

1R1810

MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN

TP_MCP_RGB_DAC_RSET

MCP_MII_COMP_GNDMCP_MII_COMP_VDD

PP1V05_ENET_MCP_PLL_MAC

=MCP_MII_COL

MCP_CLK25M_BUF0_R

MCP_DDC_CLK0

LVDS_IG_DDC_CLK

=MCP_HDMI_DDC_CLK

MCP_DDC_DATA0

LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_DATA

DP_IG_AUX_CH_NDP_IG_AUX_CH_P

LPCPLUS_GPIODP_IG_CA_DET

MCP_HDMI_RSET

=MCP_HDMI_TXC_N

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<0>=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_N<1>=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<2>

=MCP_HDMI_TXD_P<2>

MCP_HDMI_VPROBE

=DVI_HPD_GMUX_INT=MCP_HDMI_HPD

LVDS_IG_A_CLK_NLVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0>LVDS_IG_A_DATA_P<0>


LVDS_IG_A_DATA_P<3>

MCP_IFPAB_RSETMCP_IFPAB_VPROBE

LVDS_IG_B_CLK_NLVDS_IG_B_CLK_P

LVDS_IG_B_DATA_N<0>LVDS_IG_B_DATA_P<0>




LVDS_IG_BKL_PWMLVDS_IG_BKL_ONLVDS_IG_PANEL_PWR

ENET_RESET_L

=MCP_MII_RXER

MCP_MII_VREF

=PP3V3_ENET_MCP_RMGT


PP3V3_S0_MCP_VPLL

PP3V3_S0_MCP_DAC

=PP1V05_S0_MCP_HDMI_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_VSYNC

ENET_MDC

ENET_MDIO

TP_ENET_PWRDWN_L

ENET_CLK125M_RXCLKENET_RX_CTRL

ENET_RXD<0>ENET_RXD<1>ENET_RXD<2>ENET_RXD<3>

ENET_TXD<0>ENET_TXD<1>ENET_TXD<2>

CRT_IG_B_COMP_PBCRT_IG_G_Y_Y

CRT_IG_HSYNC

CRT_IG_R_C_PR

MCP_TV_DAC_RSET

CRT_IG_VSYNC

MCP_CLK27M_XTALOUT

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

TP_MCP_RGB_GREEN

LVDS_IG_A_DATA_P<1>

=MCP_MII_CRS

TP_ENET_INTR_L

=PP3V3_S5_MCP_GPIO


=PP3V3_S0_MCP_GPIO

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_N<3>


MCP Ethernet & Graphics

104 37

104 37

104 37

102 26

104 37

102 26

9

9

89

89

107 89

107 89

107 89

107 89

107 89

104 37

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

104 37

107 89

107 89

107 89

107 89

107 89

104 37

MCP7ABGA

OMIT

5%47K

402MF-LF1/16W

51

402MF-LF

5%1/16W

100K

402

5%100K

1/16WMF-LF

10K

402

1/16W5%

MF-LF

9

9

9

8

8

93

MF-LF

49.9

402

1%1/16W

1%1/16WMF-LF402

49.9

8

8

8

8

8

107 26

107 26

9

9

107 93

107 93

9

9

9

9

9

9

9

9

89

89

89

8

8

37

104 37

104 37

104 37

104 37

104 37

104 37

104 38

104 37

25

104

104

25

38 25 18

38 25

26

26

26

26

8

8

8

8

20 6

38 25 18

21 19 6

OUT

OUT

BI

BI

BI

BI

IN

BI OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

(7 OF 11)

PCI

GND

LPC

PCI_AD28

PCI_REQ4*/GPIO_52/RS232_SIN*

PCI_REQ2*/GPIO_40/RS232_DSR*

PCI_AD31

LPC_PWRDWN*/GPIO_54/EXT_NMI*

LPC_RESET0*

LPC_AD1LPC_AD2LPC_AD3

LPC_CLK0

LPC_FRAME*

PCI_TRDY*

PCI_STOP*PCI_SERR*

PCI_RESET1*PCI_RESET0*

PCI_REQ3*/GPIO_38/RS232_CTS*

PCI_REQ1*/FANRPM2PCI_REQ0*

PCI_PME*/GPIO_30

PCI_PERR*/GPIO_43/RS232_DCD*PCI_PAR

PCI_IRDY*

PCI_INTZ*

PCI_INTY*PCI_INTX*PCI_INTW*

PCI_GNT4*/GPIO_53/RS232_SOUT*PCI_GNT3*/GPIO_39/RS232_RTS*

PCI_GNT2*/GPIO_41/RS232_DTR*PCI_GNT1*/FANCTL2

PCI_GNT0*

PCI_FRAME*

PCI_DEVSEL*

PCI_CLKRUN*/GPIO_42

PCI_CLKIN

PCI_CLK2PCI_CLK1PCI_CLK0

PCI_CBE3*PCI_CBE2*PCI_CBE1*

PCI_CBE0*

PCI_AD30PCI_AD29

PCI_AD27

PCI_AD26PCI_AD25PCI_AD24PCI_AD23


PCI_AD18PCI_AD17PCI_AD16PCI_AD15PCI_AD14



PCI_AD5PCI_AD4PCI_AD3PCI_AD2PCI_AD1

PCI_AD0

LPC_SERIRQ

LPC_DRQ0*

LPC_AD0

GND GND

LPC_DRQ1*/GPIO_19




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PUInt PU

Int PU

Int PU (S5)

19 OF 110

051-7845

A.0.0


Y3

Y2AA7

R11R10

T4U9T3V9T2

T1

AB9Y1AA10

N1N2N3P2

P3U11R4U10R3

Y4AA9

AD11

R9

R8

R7R6

W10

AA11AA6AA3

AA2AC8AC7

AB2AC6AB3

U7T5

AE11

U6

U1U5U2W11

U3W9V2W8V3

AC4

W7W4W6W3

Y5AA5AA1

AC11

AC10AC9

AE10AC3

AE6

AE5

AE12

AD4

AE2AE1

AE9

AD5

AD1AD2AD3

Y27Y26

Y25

Y24Y22Y20Y19

Y18Y17Y16W43W40

W36W24W22W20

V7V40V4V37

V33V28V27V26V24

V22V20V18V17

V16U8U4U39

U26U24

AD34

AD33AD28AD27AD26

AD25AD24AD20AD19AD18

AD17AD16AC5AB33

AC40AC36AC22AB40

AB4AB37AB34AB28AB27

AB26AB25AB24AB23

AB21AB20H34AB18

U1400

21R195321R195221R195121R1950

21R1960

2

1R1961

21R199221R1994

21R199021R1991

21R1989

2

1R1910TP_PCI_AD<26>

PCI_CLK33M_MCP

TP_PCI_GNT0_L

TP_PCI_AD<28>

MCP_RS232_SIN_L

CRTMUX_SEL_TV_L

TP_PCI_AD<31>

LPC_PWRDWN_L

LPC_RESET_L

LPC_AD_R<1>LPC_AD_R<2>LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

TP_PCI_TRDY_L

TP_PCI_STOP_LTP_PCI_SERR_L

TP_PCI_RESET1_L

MEM_VTT_EN_R

AUD_IPHS_SWITCH_EN

PCI_REQ1_LPCI_REQ0_L

PM_LATRIGGER_L

TP_PCI_PERR_L

TP_PCI_PARTP_PCI_IRDY_L

TP_PCI_INTZ_LTP_PCI_INTY_L

TP_PCI_INTX_LTP_PCI_INTW_L

MCP_RS232_SOUT_LGMUX_JTAG_TDIGMUX_JTAG_TMS

TP_PCI_GNT1_L

TP_PCI_FRAME_LTP_PCI_DEVSEL_L

PM_CLKRUN_L

PCI_CLK33M_MCP_RTP_PCI_CLK1TP_PCI_CLK0

TP_PCI_C_BE_L<3>TP_PCI_C_BE_L<2>TP_PCI_C_BE_L<1>TP_PCI_C_BE_L<0>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<27>

TP_PCI_AD<25>TP_PCI_AD<24>TP_PCI_AD<23>TP_PCI_AD<22>

TP_PCI_AD<21>TP_PCI_AD<20>TP_PCI_AD<19>TP_PCI_AD<18>TP_PCI_AD<17>



TP_PCI_AD<8>MCP_DEBUG<7>MCP_DEBUG<6>MCP_DEBUG<5>

MCP_DEBUG<4>MCP_DEBUG<3>MCP_DEBUG<2>MCP_DEBUG<1>MCP_DEBUG<0>

LPC_SERIRQTP_LPC_DRQ0_L

LPC_AD_R<0>

FW_PME_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2>LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_LPCI_REQ1_LCRTMUX_SEL_TV_L

MCP PCI & LPCSYNC_MASTER=MASTER SYNC_DATE=N/A

MCP7ABGA

OMIT

8

8

68

13

13

13

13

13

13

13

13

13

19

19

42

9

402MF-LF1/16W5%22

225% 1/16W MF-LF 402

5% 1/16W MF-LF22

402

5% 1/16W MF-LF22

402

1/16W MF-LF 40222

5%

MF-LF402

1/16W5%10K

19

8.2K5% 1/16W MF-LF 402

402MF-LF1/16W8.2K

5%

402MF-LF1/16W5%8.2K

402MF-LF1/16W5%8.2K

402MF-LF1/16W5%8.2K

PLACEMENT_NOTE=Place close to pin R8

MF-LF402

1/16W5%22

51 49

103 9 51 49

51 49

103 51 49

103 51 49

103 51 49

103 51 49

103 9

103 51 49

8

103

8

8

8

103

103

103

103

8

8

8

8

103 19

103 19

8

8

8

8

8

8

8

8

8

8

103

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

103

21 18 6

19

19

103 19

103 19

19

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

USB9_PUSB9_N

USB8_PUSB8_N

USB7_PUSB7_N

USB6_P

USB6_N

USB5_PUSB5_N

USB4_PUSB4_N

USB3_P

USB3_N

USB2_PUSB2_N

USB11_PUSB11_N

USB10_PUSB10_N

USB1_PUSB1_N

USB0_P

USB_RBIAS_GND

USB_OC3*/GPIO_28/MGPIO

USB_OC2*/GPIO_27/MGPIOUSB_OC1*/GPIO_26USB_OC0*/GPIO_25

SATA_TERMP

SATA_C1_RX_PSATA_C1_RX_N

SATA_C0_TX_PSATA_C0_TX_N

SATA_C0_RX_P

SATA_C0_RX_N

SATA_B1_TX_PSATA_B1_TX_N

SATA_B1_RX_PSATA_B1_RX_N

SATA_B0_TX_PSATA_B0_TX_N

SATA_B0_RX_PSATA_B0_RX_N

SATA_A1_TX_PSATA_A1_TX_N

SATA_A1_RX_PSATA_A1_RX_N

SATA_A0_TX_N

SATA_A0_RX_N

V3P3_PLL_USB

V1P1_SATA_DVDD1

V1P1_SATA_DVDD0

V1P1_SATA_AVDD1

V1P1_SATA_AVDD0

GND

SATA_A0_TX_P

SATA_C1_TX_NSATA_C1_TX_P

SATA_LED*

V1P1_PLL_SATA

USB0_N

SATA_A0_RX_P

USB

SATA

(8 OF 11)

BI

BI




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

19 mA (A01)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

127 mA (A01, AVDD0 & 1)


Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

External D

External A

Camera

Bluetooth

IR

External B

External C


43 mA (A01, DVDD0 & 1)

84 mA (A01)

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.


ExpressCard

20 OF 110

051-7845

A.0.0


L28

AH19AH17

AG19

AG17AG16AF19

AM14AM13AL14AN14

AL13AN12AM12

AM11AL12AK13AK12AN11

AJ12

AE16

A27

H21J21K21L21

H25J25

K25

L25

D27E27

F27G27

J26

J27

K27L27

F29G29

A28

B28

C28D28

K23L23

F25G25

C29D29

AE3

E12

AP3AP2

AN2AN3

AN1

AM1

AM3AM2

AM4

AL3

AK3AL4

AK2AJ3

AJ1

AJ2

AJ11AJ10

AK9

AJ9

AJ7AJ6

AJ4AJ5

AH24AH22

AH20AH18AG40AG36

AG26AG22AG20AG18

AF40AF37AF34AF33AF28

AF27AF26AF22AF20

AF18AF17AF16AD6

AE4AE39AE24AE22AD38

AD37AD35

U1400

2

1R2050

2

1R2051

2

1R2052

2

1R2053

2

1R2060

2

1R2010

USB_EXTA_OC_LUSB_EXTB_OC_L

USB_EXTC_OC_LEXCARD_OC_L

PP3V3_S0_MCP_PLL_USB

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

SATA_HDD_D2R_P

USB_EXTA_N

PP1V05_S0_MCP_PLL_SATA

TP_MCP_SATALED_L

TP_SATA_F_R2D_CPTP_SATA_F_R2D_CN

SATA_HDD_R2D_C_P

=PP1V05_S0_MCP_SATA_AVDD0




SATA_HDD_D2R_N

SATA_HDD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

TP_SATA_C_D2RNTP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_R2D_CNTP_SATA_D_R2D_CP

TP_SATA_E_D2RNTP_SATA_E_D2RP

TP_SATA_E_R2D_CNTP_SATA_E_R2D_CP

TP_SATA_F_D2RNTP_SATA_F_D2RP

MCP_SATA_TERMP

MCP_USB_RBIAS_GND

USB_EXTA_P

USB_MINI_NUSB_MINI_P

TP_USB_10P

USB_EXTD_NUSB_EXTD_P

USB_CAMERA_NUSB_CAMERA_P

USB_IR_N

USB_IR_P

USB_TPAD_P

USB_BT_N

USB_EXTB_P

USB_EXCARD_NUSB_EXCARD_P

USB_EXTC_NUSB_EXTC_P

SATA_ODD_D2R_N

TP_SATA_D_D2RN

USB_EXTB_N

USB_SDCARD_NUSB_SDCARD_P

TP_USB_10N

MCP SATA & USBSYNC_MASTER=MASTER SYNC_DATE=N/A

103 47

103 47

MCP7ABGA

OMIT

102 45

102 45

102 45

102 45

102 45

102 45

102 45

102 45

402

1/16WMF-LF

5%8.2K

5%8.2K

1/16W

402MF-LF

402

1/16WMF-LF

5%8.2K

5%8.2K

MF-LF1/16W

402

806

MF-LF

1%1/16W

402

MF-LF

1%1/16W

402

2.49K

46 9

46

46

103 46

103 46

8

8

103 46

103 46

103 47

103 47

8

8

103 47

103 47

103 47

103 47

103 46

103 46

8

8

103 46

103 46

25

18 6

25

45

28

28

28 6

28

102

103

8

8

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

IN

IN OUT

IN

IN

OUT

IN

EXT_SMI*/GPIO_32

V1P1_PLL_NV_H

A20GATE

BUF_SIO_CLK

CPU_DPRSLPVR

CPU_VLD CPUVDD_EN

FANCTL0/GPIO_61

FANCTL1/GPIO_62

FANRPM0/GPIO_60

FANRPM1/GPIO_63

GPIO_1/PWRDN_OK/SPI_CS1

GPIO_12/SUS_STAT*/ACCLMTR_EXT_TRIG

HDA_BITCLK

HDA_RESET*

HDA_SDATA_IN0

GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK

GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA

HDA_SDATA_OUT

HDA_SYNC

INTRUDER*

JTAG_TCK

JTAG_TDIJTAG_TDO

JTAG_TMSJTAG_TRST*

KBRDRSTIN*

LID*LLB*

GPIO_13/MCP_VID0

GPIO_14/MCP_VID1GPIO_15/MCP_VID2

V3P3_DUAL_HDA_0V3P3_DUAL_HDA_1

V1P1_PLL_SP_SPREF

PKG_TEST

PS_PWRGD

PWRBTN*

PWRGD_SB

RSTBTN*

RTC_RST*

SIO_PME*

SLP_RMGT*

SLP_S3*

SMB_ALERT*/GPIO_64

SMB_CLK0

SMB_CLK1/MSMB_CLKSMB_DATA0

SMB_DATA1/MSMB_DATA

GPIO_11/SPI_CLKGPIO_10/SPI_CS0

GPIO_8/SPI_DI

GPIO_9/SPI_DO

SPKR

SUS_CLK/GPIO_34

TEST_MODE_EN

THERM_DIODE_NTHERM_DIODE_P

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

SLP_S5*

GPIO_5/HDA_DOCK_RST*/PS2_MS_DATAGPIO_4/HDA_DOCK_EN*/PS2_MS_CLKHDA_PULLDN_COMP

HDA

MISC

(9 OF 11)

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)Int PU (S5)

17 mA

20 mA37 mA (A01)

7 mA (A01)


HDA Output CapsFor EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PUInt PU

25 MHz

42 MHz 0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

1

0

SPI_CLKSPI_DO

0

1

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM bydefault, LPC+ debug card pulls

1

1

0

0

LPC_FRAME#

0

1

0

1

Int PD

Int PD

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

SAFE mode: For ROMSIP

recovery

USER mode: Normal

Connects to SMC for

(MXM_OK for MXM systems)

automatic recovery.Int PU

NC

21 OF 110

051-7845

A.0.0


B19

B16

A19

A16

K16J16

AE17AE18

B11C11

K22

B18

C13

F21

K19G21

L19

M23

H17

G17J17

C19

C20

D16

D20

C16

E20

L22

M24

M25

L13

J18

J19F19E19

G19

B20

L15

F15G15

K15

A15

E15

B14C15

L17

K17

J15

J14

L24

M21M20L20

L26

D13

C14

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

2

1R2140

2

1R2143

1

2R2154

2

1R2151

2

1R2155

2

1R2156

2

1R2157

2

1R2141

2

1R2142

2

1R21472

1C2172

2

1C2170

2

1 C2173

2

1 C2171

2

1R2150

2

1R2110

21

R2172

2

1R2181

2

1R2180

2

1R2160

2

1R2163

21

R2173

21

R2171

21

R2170

2

1R2190

2

1R2120

2

1R2121

MCP_PS_PWRGD

SMC_RUNTIME_SCI_L

PP1V05_S0_MCP_PLL_NV

TP_SB_A20GATE

MCP_CPUVDD_EN

ODD_PWR_EN_LMEM_EVENT_L

SMC_IG_THROTTLE_L

=SPI_CS1_R_L_USE_MLBSMC_ADAPTER_EN

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDIN0

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

HDA_SDOUT_R

HDA_SYNC_R

SM_INTRUDER_L

JTAG_MCP_TDI

JTAG_MCP_TDOJTAG_MCP_TMS

TP_MCP_KBDRSTIN_L

TP_MCP_LID_LPM_BATLOW_L

MCP_VID<0>MCP_VID<1>

=PP3V3R1V5_S0_MCP_HDA

PM_RSMRST_L

PM_SYSRST_DEBOUNCE_L

SMC_WAKE_SCI_L

PM_SLP_RMGT_LPM_SLP_S3_L

SMBUS_MCP_0_CLK

SMBUS_MCP_1_CLK

SPI_CLK_RSPI_CS0_R_L

SPI_MISOSPI_MOSI_R

MCP_SPKR

PM_CLK32K_SUSCLK_R

MCP_TEST_MODE_EN

MCP_THMDIODE_N

MCP_THMDIODE_P

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

PM_SLP_S4_L

AUD_I2C_INT_LMCP_GPIO_4MCP_HDA_PULLDN_COMP

AP_PWR_ENAUD_I2C_INT_LMCP_GPIO_4

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC


HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

ARB_DETECT

HDA_SYNC

MEM_EVENT_LSMC_IG_THROTTLE_L

=PP3V3_S0_MCP

TP_MCP_BUF_SIO_CLK

=PP3V3_S3_MCP_GPIO

MCP_CPU_VLD

PM_PWRBTN_L

MCP_VID<2>MCP_VID<1>

MCP_VID<0>

=PP3V3_S0_MCP_GPIO

JTAG_MCP_TRST_LJTAG_MCP_TCK

ARB_DETECT

AP_PWR_ENSMBUS_MCP_1_DATA

SMBUS_MCP_0_DATA

MCP_VID<2>

RTC_RST_L

MCP HDA & MISCSYNC_MASTER=MASTER SYNC_DATE=N/A

103 51

103 61 51

103 61 51

28

49

49

70

103 28

103 28

103 28

103 28

MCP7ABGA

OMIT

50 21

50

10K5%

MF-LF1/16W

402MF-LF402

1/16W5%10K

1/16WMF-LF

5%100K

402

402MF-LF

5%1/16W

100K

402

1/16W

22K5%

MF-LF

22K5%

MF-LF1/16W

402

22K5%

MF-LF1/16W

402

402

1/16WMF-LF

5%10K 10K

5%1/16W

402MF-LF

402

1/16WMF-LF

5%100K

55 49 32 31 21

50 49

9 9

68 21

8

50V

10PF5%

402CERM

50V

10PF5%

402CERM

50V

10PF5%

402CERM

10PF50V5%

402CERM

13

13

13

13

13

402

1/16WMF-LF

5%10K

49.9

MF-LF1/16W1%

402

51

402

5%

22

1/16WMF-LF

5%10K

402MF-LF

BOOT_MODE_USER

1/16W

5%10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

MF-LF

8.2K5%1/16W

402

MF-LF402

5%10K

1/16W

5%

22

MF-LF1/16W

402

MF-LF

5%1/16W

402

22

MF-LF402

5%

22

1/16W

49

49

103 9

402MF-LF

1K1%1/16W

1%49.9K

MF-LF402

1/16WMF-LF1/16W1%

402

49.9K

103 62

103 62

103 62

103 62

103 62

49

70

108 55

21

74 21

74 21

108 55

74 21

52

106 52 13

52

106 52 13

102 70

102 9

103 61 51

25

8

103 21

103 21

8

9

103 21

103 21

8

25 21 6

21 103

21

68 21

21

28 22

25 21 6

103 21

103 21

103 21

103 21

21

55 49 32 31 21

50 21

25 22 6

8

6

74 21

74 21

74 21

19 18 6

21

V1P0_CORE_VDD

V3P3

V3P3_DUAL_USB

V3P3_DUAL

V3P3_VBATV1P0_VDD_AUXC

V1P2_CPU_VTT

V1P2_CPUCLK_VTT

(10 OF 11)(11 OF 11)

GNDGND




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

23065 mA (A01, 1.2V)

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

80 uA (S0)


10 uA (G3)

16 mA 266 mA (A01)

1182 mA (A01)

450 mA (A01)

22 OF 110

051-7845

A.0.0


T22AH16

Y11V11T11Y6

P11AY13AB19AA4

M11AD7AN26AB16AB17

Y38Y37Y35Y34

Y33Y28M37M35

M34M10L5L43L40

AU1K8K40K4

K37K26K18K12

K10J8J12G40AN8

H23AW35H15H11

G8G6G43G4

G34AW20G24G22BC12

G16G14G12G10

F8F32F16F12

E33E29E25E21

E17E13D6D37D30

D26D23D22D19

D18D15D14D10

C2BC5AY14BC41BC37

BC33L35AY6AW31

BA4BA1AV40

AY41AY38AY37

AY34AY33AY30AV12

AY10AW43AR43G20

AW11AV7AV4

AV36AV32

AV28F20G28AU4

AU38AU36AR30AU32

AP33AU28AU12L12

AY22

AY21AT9AT7AT6

AT33AT29AT13AR12

AT10AR40AR32AR28AW23

AP7AP40AP4

AP37

AP36AP34AP32AP28

AU14AP14AU26AP10Y7

AN4AN39AN30AN28

AP26AM9AM7AM6

AM5AM38AM37AM35

AM34AM30AM26AM24AM22

AM20AM18AM16AM10

AL5AL40AL36AK40

AK4AK37AK34AK33AK10

AJ8AJ39AH38AH37

AH34AH33AH26

U1400

A20

K28J28

H27G26

K20

J20H19G18

Y9AA8AB11Y10

AD9AB10AE8AD10

AG32

AL31AD32AK32

AK31

W32V32

AJ32

U32T32AA32Y32

P32N32N31M33

M32M31

AH32

L34L33L32

K35K34K33J36

J35J34H37

AE32

H35

G38G37G36F39

F38F37E40E39E38

AF32

D41D40D39C42

C41C40B42B41

AC32AB32

P31R32

V21U21

T21

AC21

AA16

AC20

AF12W25Y23W23

W21AA24AH9AH7

AH6AH5

AC19

AH4AH3

AH21Y21

AH25W28

AA23

AH2W26

AH11

AC18

AH10

AH1AG9AG8AG5

AG7AG6

AA21AG4AG3

AC17

AG25AG23AG21AG12

AG11AG10AA20AF9

AH23AF7

AC16

AF4AF3

AF25

AF23AF21AF2

AH12

AA19AF11AF10

AA28

AE28

AE27AE26AE25AE23

AE21AE19U25

AA18V25

AA27

W27AD23AD21AC28

AC27AC26AC25AC24

AC23AA17

AA26AA25

U1400


PP3V3_G3_RTC

=PP3V3_S5_MCP

=PP3V3_S0_MCP

=PPVCORE_S0_MCP =PP1V05_S0_MCP_FSB

MCP Power & GroundSYNC_MASTER=MASTER SYNC_DATE=N/A

MCP7A

OMIT

BGA

OMIT

BGAMCP7A

25 6

28 21

25 6

25 21 6

25 6 25 14 6




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

23 OF 110

051-7845

A.0.0


BLANK PAGESYNC_MASTER=MASTER SYNC_DATE=N/A




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

24 OF 110

051-7845

A.0.0


BLANK PAGESYNC_DATE=12/08/2008SYNC_MASTER=K51

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD

QTY DESCRIPTIONPART#TABLE_5_ITEM

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) PowerNV: 1X 4.7UF 0402, 2X 1UF 0402, 2X 0.1UF 0402 (6.9UF)

84 mA (A01)

270 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)Apple: 1x 2.2uF 0402 (2.2 uF)

19 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

5 mA (A01)

87 mA (A01)

562 mA (A01)

84 mA (A01)

BALLS FOR AVDD0 SO 80% OFCAPACITANCE ON AVDD0

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)


450 mA (A01)

57 mA (A01)

127 mA (A01)

206 mA (A01)

37 mA (A01)

83 mA (A01)

131 mA (A01)

16996 mA (A01, 1.0V)23065 mA (A01, 1.2V)

(No IG vs. EG data)

MCP 3.3V Ethernet Power

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

4771 mA (A01, DDR3)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 1.05V AUX Power

105 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

MCP PCIE (DVDD) Power

APPLE: 4X 4.7UF 0402, 4X 1UF 0402, 6X 0.1UF 0402 (23.4 UF)MCP Core Power

DIFFERENT THAN ON T18

PEX_AVDD RAIL SPLIT BASEDON IG VS. EG. 12 OUT OF 15

PEX_DVDD RAIL SPLIT BASEDON IG VS. EG. 8 OUT OF 10CAPACITANCE ON DVDD0BALLS FOR DVDD0 SO 80% OF

Apple: 7x 2.2uF 0402 (15.4 uF)

43 mA (A01) 333 mA (A01)

MCP 1.05V RMGT Power

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

K50: 2X 2.2UF 0402, 2X 1UF 0402, (6.4 UF)

25 OF 110

051-7845

A.0.0


2

1C2597

2

1C2528

2

1 C2529

2

1 C2596

2

1 C2587

2

1 C2585

2

1 C2583

2

1 C2581

2

1 C2518

2

1 C2521

2

1R2591

2

1 C2591

2

1R2590

21

L2595

2

1C2595

2

1 C2590

2

1 C2589

2

1 C2560

2

1 C2525

2

1 C2526

21

L2580

2

1C2501

2

1C2500

21

L2555

21

L2586

21

L2588

21

L2584

21

L2582

21

L2575

21

L2570

2

1C2580

2

1 C2564

2

1 C2562

2

1C2540

2

1 C2541

2

1 C2542

2

1 C2543

2

1 C2544

2

1 C2545

2

1 C2546

2

1 C2547

2

1 C2548

2

1 C2549

2

1 C2550

2

1 C2551

2

1 C2552

2

1 C2553

2

1 C2575

2

1 C2576

2

1 C2573

2

1 C2574

2

1 C2570

2

1C2520

2

1 C2571

2

1 C25722

1C2515

2

1 C2516

2

1 C2517

2

1 C2530

2

1 C2531

2

1 C2532

2

1 C2533

2

1 C2534

2

1 C2535

2

1 C2536

2

1 C2512

2

1 C2513

2

1 C2508

2

1 C2509

2

1 C2510

2

1 C2511

2

1 C2504

2

1 C2505

2

1 C2506

2

1 C2507

2

1C2502

2

1 C2555

2

1C2586

2

1C2584

2

1C2588

2

1C2582

2

1C2503

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

=PP3V3_S0_MCP_PLL_UF=PP3V3_S0_MCP

=PP1V05_S0_MCP_AVDD_UF

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV



=PP3V3_ENET_MCP_RMGT=PP3V3_S5_MCP


MCP_MII_VREF


=PP1V05_ENET_MCP_PLL_MAC

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MMPP1V05_ENET_MCP_PLL_MAC

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM


PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V



=PP1V05_S0_MCP_FSB


=PP1V05_S0_MCP_SATA_DVDD


PP1V05_S0_MCP_PEX_AVDDMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

=PPVCORE_S0_MCP


=PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD0

SYNC_MASTER=K51 SYNC_DATE=12/08/2008

MCP Standard Decoupling

C2574,C25182 IGRES,0,5%,0402116S0004

4.7UF

X5R402

20%4V

4V

4.7UF20%

402X5R

20%

402X5R4V

4.7uF10V20%

402

0.1uF

CERM

4.7UF

X5R4V20%

402

4.7UF4VX5R

20%

402

4.7UF

X5R4V20%

402

4.7UF20%4VX5R402

20%4V

4.7UF

402X5R

MXM

402-LF

6.3VCERM

20%2.2UF

0.1uF20%10V

402CERM

18

402

1.47K

1/16W1%

MF-LF

402

10V20%

CERM

0.1UF

402MF-LF

1%1/16W

1.47K

0402

30-OHM-1.7A

402X5R4V

4.7UF20%

402

20%2.2UF

X5R4V

4.7UF

402

20%4VX5R

CERM402-LF

20%2.2UF6.3V

402

10V

0.1uF20%

CERM402

10V

0.1uF20%

CERM

30-OHM-1.7A

0402

402X5R

20%4.7UF

4V

4.7UF

402X5R

20%4V

0402

30-OHM-1.7A

30-OHM-1.7A

0402

0402

30-OHM-1.7A

0402

30-OHM-1.7A

30-OHM-1.7A

0402

30-OHM-5A

0603

30-OHM-5A

0603

4.7UF20%

X5R402

4V

6.3V

2.2UF20%

402-LFCERM

CERM

20%2.2UF6.3V

402-LF

4V

402X5R

4.7UF20%

402

10V20%

CERM

0.1UF

402CERM10V

0.1UF20%

0.1UF

CERM402

10V20%

402

10VCERM

20%0.1UF

402CERM10V20%0.1UF 0.1UF

CERM402

20%10V

402

10VCERM

20%0.1UF

402

10VCERM

20%0.1UF

402

10VCERM

20%0.1UF

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%6.3V

2.2UF

402-LF

20%2.2UF6.3VCERM CERM

402-LF

20%6.3V

2.2UF

402-LF

2.2UF

CERM

20%6.3V

2.2UF6.3V20%

402-LFCERM

MXM

2.2UF20%

402-LFCERM6.3V

2.2UF20%

402-LFCERM6.3V

MXM

20%2.2UF6.3VCERM402-LF

X5R

4.7UF4V

20%

402

MXM

6.3V

2.2UF20%

402-LFCERM

MXM

6.3V20%

402-LFCERM

2.2UF20%

CERM6.3V

MXM

402-LF

2.2UF

10VX5R402-1

1UF10%

X5R

MXM

10V10%1UF

402-1

6.3V

2.2UF20%

402-LFCERM

2.2UF

CERM6.3V20%

402-LFCERM402-LF

20%2.2UF6.3V

402-LFCERM

20%2.2UF6.3V

CERM402-LF

20%6.3V

2.2UF

CERM402-LF

20%2.2UF6.3V

2.2UF20%6.3VCERM402-LF

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

10%1UF

402-1X5R10V

1UF

402-1

10%

X5R10V 10V

X5R402-1

1UF10%

4.7UF

402X5R

20%4V

CERM

20%6.3V

2.2UF

402-LF

402X5R

20%4.7UF

4V

402X5R4V

20%4.7UF

402X5R4V

4.7UF20%

402X5R

20%4.7UF

4V

14

6 22 21 6

6

28

16

6

20

21

28 17

38 25 18 22 6

21 6

38 25 18

38 18

17

20

22 6

22 14 6

38 18

28 28

22 6

30 16 6

28 6 28 17



TABLE_5_ITEM








36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

16 mA (A01)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)Apple: 1x 2.2uF 0402 (2.2 uF)

190 mA (A01, 1.8V)

95 mA (A01)


Apple: ???

16 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 110

051-7845

A.0.0


21

R2680

21

R2690

21

R2650

2

1 C2616

2

1 C2641

21

L2640

2

1C2640

2

1C2615

2

1C2630

2

1R2630

2

1C2620

2

1 C2610

2

1R2620MCP_HDMI_VPROBEMCP_HDMI_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD_R


PP1V05_S0_MCP_HDMI_VDDMAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUEPP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD_R

VOLTAGE=3.3VMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_VPLL

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_DACMAKE_BASE=TRUE

POWER_MCP_DAC

=PP3V3_S0_MCP_VPLL_UF

MCP_IFPAB_RSET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V05_S0_MCP_HDMI_VDD

MXMC26411 RES,0,5%,402116S0004

1116S0004 RES,0,5%,402 MXMC2610

116S0004 1 RES,0,5%,402 C2616 MXM


MCP Graphics Support

CERM

20%6.3V

402-LF

2.2UF

IG

MF-LF

1%1/16W

402

1K

IG

1/16WMF-LF

5%

0

402

MF-LF

IG

0

402

5%1/16W

1/16WMF-LF

5%

402

0

0.1UF

CERM

IG

20%

402

10V

IG

CERM

20%10V

402

0.1uF

IG

0402

30-OHM-1.7A

4.7UF20%6.3V

IG

X5R-CERM402

X5R402

IG

4.7UF20%4V

402CERM10V20%

0.1UF

NO STUFF

NO STUFF

1%1K

402

1/16WMF-LF

0.1UF

402CERM10V20%

NO STUFF

107 18

107 18

6

6

18

102 18

18

6

102 18

18

18




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

27 OF 110

051-7845

A.0.0


SYNC_DATE=12/08/2008SYNC_MASTER=K51

BLANK PAGE

IN OUT

NCNC

IN

OUT

IN

OUT

NCNC

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

10K pull-up to 3.3V S0 inside MCP

RTC Power Sources

Reset Button

Coin-Cell HolderIMAC

PEG POWER ALIAS/OPTION TO GND UNUSED POWER PIN

UNPOWER PEG INTERFACE WHEN IG IS USED

DVDD DOES NOT NEED FILTER

AVDD IS FILTERED ON P25

UNPOWER PEG INTERFACE WHEN IG IS USED

SATA ALIAS/GROUNDING UNUSED DVDD1 AND AVDD1

PLACE AT LEAST 1 CAP NEAR MCP PIN A20

511S0054 fault protection for RTC battery.NOTE: R2800 and D2800 form the double-

RTC Crystal

MCP 25MHz Crystal

28 OF 110

051-7845

A.0.0


2

1Y2815

41

Y2810

21

R2882

21

R2880

2

1R2898 2

1 C2899

21

R2899

2

1R2816

21

R2815

21

C2816

21

C2815

2

1 C2801

2

1 C2802

1

2

J2800

25

3

6

4

1

D2800

21

R2896

2

1R2811

21

R2810

21

C2811

21

C2810

12

R2800

2

1C2800MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMPPVBATT_G3_RTC

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MMPPVBATT_G3_RTC_R

VOLTAGE=3.3V

PM_SYSRST_DEBOUNCE_L


PP3V3_G3_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

PM_SYSRST_L

=PP3V3_S5_RTC_D

XDP_DBRESET_L





=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDDMAKE_BASE=TRUE

PP1V05_S0_MCP_PEX_DVDD0

MIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 mm



PP1V05_S0_MCP_PEX_AVDD0


MAKE_BASE=TRUE


VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDDMAKE_BASE=TRUE

=PP1V05_S0_MCP_PEX_DVDD

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALIN




SB Misc

6.3V

1UF10%

CERM402

25.0000MSM-3-LF

CRITICAL

32.768K-12.5PFSM-HF

CRITICAL 5%1/16WMF-LF402

0

MXM

0

5%

402

1/16WMF-LF

MXM

SILK_PART=RESET_BTN

603

1/10W

NO STUFF

MF-LF

5%0

49

NO STUFF

X5R

10%1UF10V

402

33

MF-LF1/16W

402

5%

103 21

103 21

NO STUFF

10M

1/16W

402MF-LF

5%

402

0

MF-LF

5%1/16W

20PF

5%

402CERM50V

20PF

402CERM50V5%

0.1UF20%

402CERM10V

402

10V

0.1UF20%

CERM

103 21

103 21

SM

CRITICAL

BB10201-C1403-7H

BAT54DW-X-GSOT-363

XDP

5%1/16W

0

402MF-LF

10M

1/16WMF-LF

402

5%

MF-LF402

0

5%1/16W

5%

402CERM

12pF

50V

12pF

402

5%50VCERM

1/16WMF-LF

1K

402

5%

21 13 11

20 6

22 21 6

25 17

17

25 17

20

25

25

17

25

25 6

20

20

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

OUT

V-

V+

RESET*

A0A1A2

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPADIN

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI

OUT

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Place close to J3200.1

PRODUCTION

- =I2C_VREFDACS_SCLSignal aliases required by this page:

- =PPVTT_S3_DDR_BUF

Required zero ohm resistors when no VREF margining circuit stuffed

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

DAC channel A B A B C

ADDR=0x30(WR)/0x31(RD)

MEM B VREF DQ

Min DAC code 0x00 0x00 0x00 0x00 0x00Max DAC code 0x87 0x87 0x87 0x87 0x55Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 VMax Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

CPU FSB VREFMEM B VREF CAPower aliases required by this page:

Page NotesMEM A VREF DQ MEM A VREF CA

(per DAC LSB)

- =I2C_PCA9557D_SDA- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

- =PP3V3_S3_VREFMRGN- =PP3V3_S5_VREFMRGN

BOM options provided by this page:VREFMRGN

10mA max load

PLACE CLOSE TO U1000



(i.e. not simultaneously) due to current limitation of TPS51116 regulator. SO-DIMM A and SO-DIMM B Vref settings should be margined separately


Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

PLACE CLOSE TO U1000

ADDR=0x98(WR)/0x99(RD)

29 OF 110

051-7845

A.0.0


B4

B1

A4

A1

A2

A3

U2904

21

R2913

21

R2914

21

R2903

21

R2905

21

R2909

21

R2911

B4

B1

A4

A1

A2

A3

U2902

B4

B1

C4

C1

C2

C3

U2902

B4

B1

A4

A1

A2

A3

U2903

B4

B1

C4

C1

C2

C3

U2904

21

R2912

21

R2916

21

R2910

21

R2906

21

R2904

B4

B1

C4

C1

C2

C3

U2903

21

R2915

2

1 C2905

2

1 C2900

2

1 C2901

5

4

2

1

8

7

6

3

10

9

U2900

21

R2908

2

1 C2904

21

R2907

21

R2901

21

R2902

2

1 C2902

2

1 C2903

16

17

2

1

15

14

13

12

11

10

9

7

6

8

5

4

3

U2901

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CPUFSB_EN0

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_BMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

TP_PCA9557_P7TP_PCA9557_P6=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

VREFMRGN_CA_SODIMMB_ENVREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN1VREFMRGN_CPUFSB_EN0

PCA9557D_RESET_L

VREFMRGN_CPUFSB1

=PPVTT_S3_DDR_BUF

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_AMIN_LINE_WIDTH=0.3 mm

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

CPU_GTLREF0

VREFMRGN_CPUFSB_EN1

VREFMRGN_DQ_SODIMMA_EN

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFDQ_AMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMM

=PP3V3_S3_VREFMRGN

VREFMRGN_CPUFSB0

CPU_GTLREF1VREFMRGN_CPUFSB_BUF1

VREFMRGN_CPUFSB_BUF0

CRITICALR29031116S0004 RES,MTL FILM,0,5%,0402,SM,LF PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF116S0004 1 CRITICALR2905 PRODUCTION

RES,MTL FILM,0,5%,0402,SM,LF R2909116S0004 CRITICAL1 PRODUCTION

VREFMRGNRES,MTL FILM,200,1%,0402,SM,LF114S0149 1 CRITICALR2911

1114S0149 RES,MTL FILM,200,1%,0402,SM,LF VREFMRGNR2909 CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF R2911116S0004 1 CRITICAL PRODUCTION

CRITICAL1114S0149 VREFMRGNR2905RES,MTL FILM,200,1%,0402,SM,LF

CRITICALR29031114S0149 RES,MTL FILM,200,1%,0402,SM,LF VREFMRGN

FSB/DDR3 Vref MarginingSYNC_MASTER=MASTER SYNC_DATE=MASTER

100 11 10

0.1UF20%

402

10VCERM

VREFMRGN

100K VREFMRGN

MF-LF402

5%1/16W

20%

CERM402

10V

VREFMRGN

0.1UF

6.3V

2.2UF

CERM

20%

VREFMRGN

402-LF

10V

VREFMRGN

20%

CERM402

0.1UF

52

52 MSOP

VREFMRGN

DAC5574

52

52

9

402

100K

MF-LF

5%1/16W

VREFMRGN

402

VREFMRGN

20%0.1UF10VCERM

QFNPCA9557

VREFMRGN

1/16WMF-LF

402

5%100K VREFMRGN

5% VREFMRGN

MF-LF402

100K1/16W

MF-LF1/16W

100K

402

5%VREFMRGN

MAX4253

VREFMRGN

UCSP

VREFMRGN1/16W

100K5%

402MF-LF

FSB_VREFMRGN

1%1/16WMF-LF402

100100 11 10

OMIT

402MF-LF1/16W

200

1%

OMIT

200

402

1/16W1%

MF-LF

OMIT

402

1/16W

200

1%

MF-LF

200OMIT

402MF-LF1/16W1%

MAX4253

VREFMRGN

UCSP

UCSP

VREFMRGN

MAX4253

VREFMRGN

UCSPMAX4253

VREFMRGN

0.1UF20%10V

402CERM

MAX4253

VREFMRGN

UCSP

402

1/16W

VREFMRGN

1%

MF-LF

100

FSB_VREFMRGN

1/16W1%

MF-LF402

100

VREFMRGN

100

1%1/16WMF-LF402

VREFMRGN

1/16W

100

1%

402MF-LF

VREFMRGN

1%1/16W

100

MF-LF402

UCSPMAX4253

VREFMRGN

29

29

29

29

32

32

29

29

29

29

29

6

31

29

29

31

29

6




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

EXTRA DECOUPLING CAPS FOR MCP MEM RAIL

CAPS TO COUPLE PP5V_S3 UNDER DIMM CONNECTORS

DIMM B (CLOSER TO MCP)CAPS TO COUPLE MCP 1V5_S0_MEMDIMM A (FURTHER FROM MCP)

4771 mA (A01, DDR3)

DECOUPLING CAPS FOR DIMM ON CHANNEL A - AT CONNECTOR

DECOUPLING CAPS FOR DIMM ON CHANNEL B - AT CONNECTOR

30 OF 110

051-7845

A.0.0


2

1 C30A5

2

1 C30C0

2

1 C30C1

2

1 C30C2

2

1 C30C3

2

1 C30C4

2

1 C30C5

2

1 C30C6

2

1 C30C7

2

1 C30C8

2

1 C30C9

2

1 C30CA

2

1 C30CB

2

1 C30CC

2

1 C30CD

2

1 C30CE

2

1 C30CF

2

1 C30E0

2

1 C30E1

2

1 C30E2

2

1 C30E3

2

1 C30B0

2

1 C30B1

2

1 C30B2

2

1 C30B3

2

1 C30B4

2

1 C30D1

2

1 C30D2

2

1 C30B5

2

1 C30B6

2

1 C30B7

2

1 C30B8

2

1 C30B9

2

1 C30BA

2

1 C30BB

2

1 C30BC

2

1 C30BD

2

1 C30BE

2

1 C30BF

2

1 C30D0

2

1 C30D3

2

1 C30A0

2

1 C30A1

2

1 C30A2

2

1 C30A3

2

1 C30A4

2

1 C3002

2

1 C3001

2

1 C3000

2

1 C3099

2

1 C3098

2

1 C3040

2

1 C3043

2

1 C3045

2

1 C3047

2

1 C3048

2

1 C3049

2

1 C3090

2

1 C3091

2

1 C3092

2

1 C3093

2

1 C3094

2

1 C3095

2

1 C3096

2

1 C3097

2

1 C3070

2

1 C3071

2

1 C3072

2

1 C3073

2

1 C3074

2

1 C3075

2

1 C3076

2

1 C3077

2

1 C3078

2

1 C3079

2

1 C3080

2

1 C3081

2

1 C3082

2

1 C3083

2

1 C3084

2

1 C3085

2

1 C3050

2

1 C3051

2

1 C3052

2

1 C3053

2

1 C3054

2

1 C3055

2

1 C3056

2

1 C3057

2

1 C3058

2

1 C3059

2

1 C3060

2

1 C3061

2

1 C3062

2

1 C3063

2

1 C3064

2

1 C3065

2

1 C3010

2

1 C3019

2

1 C3018

2

1 C3017

2

1 C3016

2

1 C3035

2

1 C3034

2

1 C3033

2

1 C3032

2

1 C3031

2

1 C3030

2

1 C3014

2

1 C3023

2

1 C3022

2

1 C3021

2

1 C3020

2

1 C3029

2

1 C3028

2

1 C3027

2

1 C3026

2

1 C3025

2

1 C3041

2

1 C3042

2

1 C3044

2

1 C3046


=PP1V8R1V5_S0_MCP_MEM=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S3_MEM_A

=PP1V5_S3_MEM_B


=PP5V_S3_DDRREG

=PP5V_S3_DDRREG


MEMORY CAPS

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

402

10VCERM

0.1UF20%20%

0.1UF

CERM10V

402

0.1UF10VCERM402

20%20%0.1UF

CERM10V

402CERM

20%10V

402

0.1UF

402

20%0.1UF

CERM10V

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

402

10VCERM

0.1UF20%

10VCERM402

20%0.1UF

402

10VCERM

0.1UF20%

10VCERM

0.1UF20%

402402CERM

0.1UF20%10V

402

10VCERM

20%0.1UF

402

10VCERM

20%0.1UF0.1UF

402

20%10VCERMCERM

20%0.1UF10V

402

0.1UF

402

10V20%

CERM402

20%10VCERM

0.1UF 0.1UF

402

10VCERM

20%

402

10VCERM

20%0.1UF

402CERM

10%1UF6.3V

402CERM6.3V

1UF10%

402

10%

CERM6.3V

1UF10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402 402

CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V 6.3V

1UF10%

CERM402

402CERM6.3V

1UF10%

402

10%

CERM6.3V

1UF10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402 402

CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

6.3V

1UF10%

CERM402

402CERM

1UF6.3V10%

402CERM

10%1UF6.3V 6.3V

402CERM

10%1UF

402CERM

10%1UF6.3V 6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402402

CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402CERM

10%1UF6.3V

402

10%

CERM6.3V

1UF10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402 402

CERM

10%1UF6.3V

20%6.3VX5R603

10UF

603

10UF6.3VX5R

20%

402

10%

CERM

1UF6.3V

10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

603

20%6.3VX5R

10UF

603

10UF6.3VX5R

20%

402

10%

CERM

1UF6.3V

10%6.3V

1UF

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

6.3V

1UF10%

CERM402

30 25 16 6

30 25 16 6 30 25 16 6

108 31 6

108 32 6

30 25 16 6

75 30 6

75 30 6

S1*A13VDD_14

CAS*

VDD_12BA0

A10_AP

WE*

A3

DQ54DQ55

VSS_44

VSS_0

VSS_2

VSS_5DQS0

DQS0*

DQ5DQ4

DQ6DQ7

VREFDQ

VSS_1

VSS_3

DQ0DQ1

DM0VSS_4

VSS_7DQ12

DQ20VSS_13

DQ15DQ14

VSS_11RESET*

VSS_9DQ13

DM1

DQ21VSS_15

DQ22VSS_16

VSS_18DQ23

DQ28

DQS3*VSS_20DQ29

DM2

VSS_23DQS3

DQ30DQ31

VSS_25

VDD_1

CKE1

A15A14

VDD_3

VDD_9

VDD_5

VDD_7

A7A11

A4A6

A2A0

CK1

NC_1ODT1

VDD_15

ODT0

VDD_13RAS*

VDD_11CK1*

BA1

S0*

DQ39DQ38

VSS_30

VSS_29DQ37DQ36

VSS_27

VREFCAVDD_17

DM4

VSS_32

DQ47

DQ44

DQ46VSS_37DQS5

DQS5*

VSS_39

VSS_34DQ45

DQ52

VSS_46DQ61DQ60

VSS_42

VSS_41DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*VSS_51

DQ63DQ62

VSS_49

SDASCL

DQ2DQ3

VSS_6DQ8DQ9VSS_8DQS1*

DQS1VSS_10

DQ16VSS_12

DQ11DQ10

DQ17

DQ18

DQS2VSS_17

DQS2*

VSS_14

VSS_21

DQ24DQ25

DQ19

VSS_19

VSS_24

DQ27DQ26

DM3VSS_22

CKE0

A5

VDD_4

CK0

VDD_8A1

VDD_6

VDD_10CK0*

DQ33

VSS_26

VDD_16TEST

DQ32

DQ34VSS_31DQS4DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43DQ42VSS_36

DQ48

VSS_43

DQS6*DQS6

VSS_40DQ49

DQ50

VSS_45DQ56DQ57VSS_47

DM7

DQ58VSS_48

DQ59

SA0VSS_50

A8

A9A12/BC*

VDD_2BA2NC_0VDD_0

DQ51

VTT_0SA1VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9VSS_8DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0SA1VDDSPD

VSS_50

VSS_47

DM7

DQ58DQ59

DQ57DQ56VSS_45

DQ51DQ50

DQS6VSS_43

DQS6*


DQ43DQ42VSS_36DM5

VSS_35DQ41DQ40

DQ35

DQ34VSS_31DQS4DQS4*

VSS_28

VSS_26DQ32DQ33

TESTVDD_16S1*A13

CAS*

VDD_14

WE*VDD_12

VDD_10

CK0

A1A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0NC_0

DQ11

DQ16VSS_12

DQ10

DQ8

DM0VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3DQ1

VSS_1

SCLSDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41DQ53

DQ55VSS_44

DQ54VSS_42

DQ61

DQ52

DQ44

VSS_34DQS5*

VSS_37DQ46DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCAVDD_17

DQ37

DQ38DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0A2

A6A4

A7A11

VDD_9

VDD_7

VDD_5

VDD_3

A15A14

CKE1

VDD_1

DM1

DQ15DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13DQ20

DQ12

DQ7DQ6

DQ5DQ4

VSS_7

DQS0*VSS_2

VSS_0

DQS0VSS_5

DQ21VSS_15

DM2VSS_16DQ22

VSS_18DQ23

DQ28

VSS_20DQ29

DQS3VSS_23

DQS3*

DQ30DQ31

VSS_25

VSS_14DQ17

DQS2*

VSS_17DQS2

DQ18DQ19

DQ25DQ24

DM3VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

- ALL DQ, DQS, DM SIGNALS;TO FACILITATE BITSWAPS WITH ALIASES

- =I2C_SODIMMA_SCL

Page Notes

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

(NONE)

Power aliases required by this page:

Signal aliases required by this page:

DIMM0 SPD ADDR=0XA0(WR)/0XA1(RD) DIMM2 SPD ADDR=0XA4(WR)/0XA5(RD)

DIMM 2

DIMM 0

31 OF 110

051-7845

A.0.0


113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B178B

173B172B

168B167B

9B

162B161B

156B155B

151B150B

145B144B

139B138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B54B

49B48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B188B

169B171B

152B154B

135B137B

62B64B

45B47B

27B29B

10B12B

23B21B

18B

16B

194B

192B

182B180B

6B

193B

191B

183B181B

176B

174B

166B164B

177B175B

4B

165B163B

160B

158B

148B146B

159B

157B

149B

147B

17B

142B

140B

132B130B

143B141B

131B129B

70B

68B

15B

58B56B

69B

67B

59B57B

52B

50B

42B40B

7B

53B51B

41B39B

36B

34B

24B22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B102B

103B101B

115B

79B

108B109B

85B

89B

86B

90B91B 92B

95B 96B97B

78B80B

119B

83B 84B

107B

98B

J3100

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A178A

173A172A

168A167A

9A

162A161A

156A155A

151A150A

145A144A

139A138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A54A

49A48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A188A

169A171A

152A154A

135A137A

62A64A

45A47A

27A29A

10A12A

23A21A

18A

16A

194A

192A

182A180A

6A

193A

191A

183A181A

176A

174A

166A164A

177A175A

4A

165A163A

160A

158A

148A146A

159A

157A

149A

147A

17A

142A

140A

132A130A

143A141A

131A129A

70A

68A

15A

58A56A

69A

67A

59A57A

52A

50A

42A40A

7A

53A51A

41A39A

36A

34A

24A22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A102A

103A101A

115A

79A

108A109A

85A

89A

86A

90A91A 92A

95A 96A97A

78A80A

119A

83A 84A

107A

98A

J3100

2

1R3143

2

1R3142

2

1 C3140

2

1R3140

2

1R3141

2

1 C3150

2

1 C3151

2

1 C3135

2

1 C3136

2

1 C3130

2

1 C3131

=MEM_A_DQS_P<5>

=MEM_A_DM<4>

=MEM_A_DQ<58>=MEM_A_DQ<59>

MEM_DIMM0_SA<0>=PPSPD_S0_MEM_A

=MEM_A_DM<7>

=PP0V75_S0_MEM_VTT_A

=MEM_A_DQ<57>

=MEM_A_DQS_P<6>

=MEM_A_DQ<49>

=MEM_A_DQ<43>

=MEM_A_DQ<34>

MEM_A_A<10>

=PP1V5_S3_MEM_A

=MEM_A_DQS_P<7>=MEM_A_DQS_N<7>

=MEM_A_DQS_N<0>=MEM_A_DQ<1>=MEM_A_DQ<0>

=MEM_A_DQ<51>

=MEM_A_DQ<56>

=I2C_SODIMMA_SCL

=MEM_A_DQ<50>

MEM_A_A<13>

MEM_A_CS_L<1>


=MEM_A_DQS_N<4>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3>MEM_A_A<1> MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<7>

MEM_A_A<11>

=MEM_A_DQ<3>

=MEM_A_DQ<9>

=MEM_A_DQS_N<1>=MEM_A_DQS_P<1>

=MEM_A_DQ<26>

MEM_A_CKE<2>

MEM_A_BA<2>

MEM_A_A<9>

MEM_A_A<8>

=PP1V5_S3_MEM_A

=MEM_A_CLK_N<2>

MEM_A_A<10>MEM_A_BA<0>

MEM_DIMM2_SA<0>

=PP0V75_S0_MEM_VTT_AMEM_DIMM2_SA<1>=PPSPD_S0_MEM_A

=MEM_A_DM<7>




=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<42>

=MEM_A_DM<5>



=MEM_A_DQS_P<4>

=MEM_A_DQS_N<4>


MEM_A_CS_L<3>

MEM_A_A<13>

MEM_A_CAS_LMEM_A_WE_L

=MEM_A_CLK_P<2>

MEM_A_A<1>MEM_A_A<3>

MEM_A_A<5>

MEM_A_A<12>

=MEM_A_DQ<11>

=MEM_A_DQ<16>

=MEM_A_DQ<10>

=MEM_A_DQ<8>

=MEM_A_DM<0>

=MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A


=I2C_SODIMMA_SCL=I2C_SODIMMA_SDA


=MEM_A_DQ<63>


MEM_EVENT_L

=MEM_A_DQ<62>

=MEM_A_DQ<60>

=MEM_A_DQ<53>


=MEM_A_DQ<61>

=MEM_A_DQ<52>

=MEM_A_DQ<44>

=MEM_A_DQS_N<5>


=MEM_A_DQ<45>

PP0V75_S3_MEM_VREFCA_A

=PP1V5_S3_MEM_A

=MEM_A_DQ<37>

MEM_A_BA<1>

MEM_A_ODT<2>

=MEM_A_CLK_P<3>



MEM_A_A<7>

MEM_A_A<11>


MEM_A_CKE<3>

=MEM_A_DM<1>


=MEM_A_DQ<13>

MEM_RESET_L

=MEM_A_DQ<20>

=MEM_A_DQ<12>


=MEM_A_DQ<5>

=MEM_A_DQ<4>

=MEM_A_DQS_N<0>=MEM_A_DQS_P<0>

=MEM_A_DQ<21>

=MEM_A_DM<2>


=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQS_N<3>


=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQS_P<2>



=MEM_A_DM<3>

=MEM_A_DQ<27>

=MEM_A_CLK_N<3>

MEM_A_RAS_L

MEM_A_CS_L<2>

MEM_A_ODT<3>

MEM_A_CAS_LMEM_A_WE_L


=MEM_A_DQS_P<0>


=MEM_A_DQ<20>


MEM_RESET_L

=MEM_A_DQ<13>

=MEM_A_DM<1>

=MEM_A_DQ<21>


=MEM_A_DQ<28>

=MEM_A_DQS_N<3>

=MEM_A_DQ<29>

=MEM_A_DQS_P<3>


=MEM_A_CLK_P<1>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_RAS_L

=MEM_A_CLK_N<1>

MEM_A_BA<1>

MEM_A_CS_L<0>




=MEM_A_DM<4>

=MEM_A_DQ<47>

=MEM_A_DQ<44>

=MEM_A_DQ<46>


=MEM_A_DQ<45>

=MEM_A_DQ<52>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQ<53>

=MEM_A_DM<6>

MEM_EVENT_L


=MEM_A_DQ<8>

=MEM_A_DQS_N<1>


=MEM_A_DQ<24>

=MEM_A_DQ<26>

=MEM_A_DM<3>

=MEM_A_DQS_P<4>

=MEM_A_DQ<35>


=MEM_A_DM<5>

=MEM_A_DQ<42>

=MEM_A_DQ<48>

MEM_A_A<12>

MEM_A_BA<2>

=PP0V75_S0_MEM_VTT_AMEM_DIMM0_SA<1>

MEM_DIMM2_SA<0>

MEM_DIMM2_SA<1>

=PPSPD_S0_MEM_AMEM_DIMM0_SA<1>


PP0V75_S3_MEM_VREFDQ_A


=PPSPD_S0_MEM_A

MEM_DIMM0_SA<0>

=MEM_A_DQS_P<1>

=MEM_A_DQ<16>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

MEM_A_CKE<0>

=MEM_A_CLK_N<0>

MEM_A_BA<0>

=MEM_A_CLK_P<0>

PP0V75_S3_MEM_VREFDQ_A=MEM_A_DQ<4>


=MEM_A_DQS_P<2>

MEM_A_A<5>

=MEM_A_DQS_P<3>

MEM_A_A<14>


=MEM_A_DQ<5>

=MEM_A_DQ<12>

=MEM_A_DM<2>

=MEM_A_DQ<9>


=MEM_A_DM<0>

MEM_A_A<15>

=PP1V5_S3_MEM_AMEM_A_CKE<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<17>

=MEM_A_DQ<38>

=MEM_A_DQ<43>


=MEM_A_DQS_N<6>

=I2C_SODIMMA_SDA

=MEM_A_DQ<36>

=MEM_A_DM<6>

=MEM_A_DQ<39>

DDR3 SO-DIMMs 0 & 2SYNC_DATE=N/ASYNC_MASTER=MASTER

F-RT-TH

DDR3-SODIMM-DUALCRITICAL

F-RT-TH

DDR3-SODIMM-DUAL

CRITICAL

10K

402

5%1/16WMF-LF

10K5%

402

1/16WMF-LF

402-LF

6.3VCERM

20%2.2UF

5%10K

1/16W

402MF-LF MF-LF

5%

402

10K

1/16W

6.3V

2.2UF20%

402-LFCERM CERM

402-LF

6.3V

2.2UF20%

402-LF

20%

CERM6.3V

2.2UF10V20%0.1UF

402CERM

CERM

2.2UF20%6.3V

402-LF 402

10V

0.1UF20%

CERM

33

31

31

33

33 31

33 31

31

31 6

33 31

31 6

33 31

33 31

33 31

33 31

33 31

101 31 15

108 31 30 6

33 31

33 31

33 31

33 31

33 31

33 31

33 31

52 31

33 31

101 31 15

101 15

33 31

33 31

33 31

101 31 15

101 31 15

101 31 15

101 31 15 101 31 15

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

101 16

101 31 15

101 31 15

101 31 15

108 31 30 6

33

101 31 15

101 31 15

31

31 6

31

31 6

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

101 16

101 31 15

101 31 15

101 31 15

33

101 31 15

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

31 29

33 31

33 31

52 31

52 31

31 6

33 31

33 31

33 31

55 49 32 31 21

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

31

33 31

33 31

33 31

33 31

31 29

108 31 30 6

33 31

101 31 15

101 16

33

101 31 15

101 31 15

101 31 15

101 31 15

101 31 15

101 31 15

33 31

101 31 15

101 16

33 31

33 31

33 31

33 31

33 32 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33

101 31 15

101 16

101 16

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 32 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33

101 15

101 15

101 31 15

33

101 31 15

101 15

33 31

33 31

33 31

33 31

31 29

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

55 49 32 31 21

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

101 31 15

101 31 15

31 6

31

31

31

31 6 31

31 29

29

31 6

31 6

31

33 31

33 31

33 31

33 31

101 15

33

101 31 15

33

31 29

33 31

33 31

33 31

33 31

101 31 15

33 31

101 31 15

101 31 15

101 31 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

33 31

108 31 30 6

101 15

33 31

33 31

33 31

33 31

33 31

33 31

33 31

52 31

33

33 31

33 31

S1*A13VDD_14

CAS*

VDD_12BA0

A10_AP

WE*

A3

DQ54DQ55

VSS_44

VSS_0

VSS_2

VSS_5DQS0

DQS0*

DQ5DQ4

DQ6DQ7

VREFDQ

VSS_1

VSS_3

DQ0DQ1

DM0VSS_4

VSS_7DQ12

DQ20VSS_13

DQ15DQ14

VSS_11RESET*

VSS_9DQ13

DM1

DQ21VSS_15

DQ22VSS_16

VSS_18DQ23

DQ28

DQS3*VSS_20DQ29

DM2

VSS_23DQS3

DQ30DQ31

VSS_25

VDD_1

CKE1

A15A14

VDD_3

VDD_9

VDD_5

VDD_7

A7A11

A4A6

A2A0

CK1

NC_1ODT1

VDD_15

ODT0

VDD_13RAS*

VDD_11CK1*

BA1

S0*

DQ39DQ38

VSS_30

VSS_29DQ37DQ36

VSS_27

VREFCAVDD_17

DM4

VSS_32

DQ47

DQ44

DQ46VSS_37DQS5

DQS5*

VSS_39

VSS_34DQ45

DQ52

VSS_46DQ61DQ60

VSS_42

VSS_41DQ53

DM6

VTT_1

DQS7*

DQS7

EVENT*VSS_51

DQ63DQ62

VSS_49

SDASCL

DQ2DQ3

VSS_6DQ8DQ9VSS_8DQS1*

DQS1VSS_10

DQ16VSS_12

DQ11DQ10

DQ17

DQ18

DQS2VSS_17

DQS2*

VSS_14

VSS_21

DQ24DQ25

DQ19

VSS_19

VSS_24

DQ27DQ26

DM3VSS_22

CKE0

A5

VDD_4

CK0

VDD_8A1

VDD_6

VDD_10CK0*

DQ33

VSS_26

VDD_16TEST

DQ32

DQ34VSS_31DQS4DQS4*

VSS_28

DQ35

DQ41

VSS_33

VSS_35

DQ40

DM5

VSS_38

DQ43DQ42VSS_36

DQ48

VSS_43

DQS6*DQS6

VSS_40DQ49

DQ50


DM7

DQ58VSS_48

DQ59

SA0VSS_50

A8

A9A12/BC*

VDD_2BA2NC_0VDD_0

DQ51

VTT_0SA1VDDSPD

MTG PIN MTG PIN

KEY

(1 OF 2)

DQ3

VSS_10

VSS_19

DQ9VSS_8DQS1*

DQS1

VSS_21

DQ26

CKE0

BA2

A9

A8

VDD_6

VDD_8

CK0*

A10_AP

BA0

SA0

VTT_0SA1VDDSPD

VSS_50

VSS_47

DM7

DQ58DQ59

DQ57DQ56VSS_45

DQ51DQ50

DQS6VSS_43

DQS6*


DQ43DQ42VSS_36DM5

VSS_35DQ41DQ40

DQ35

DQ34VSS_31DQS4DQS4*

VSS_28

VSS_26DQ32DQ33

TESTVDD_16S1*A13

CAS*

VDD_14

WE*VDD_12

VDD_10

CK0

A1A3

A5

VDD_4

A12/BC*

VDD_2

VDD_0NC_0

DQ11

DQ16VSS_12

DQ10

DQ8

DM0VSS_4

VSS_6

DQ2

VREFDQ

DQ0

VSS_3DQ1

VSS_1

SCLSDA

VTT_1

VSS_51

VSS_49

DQ63

DQS7

DQS7*

EVENT*

DQ62

DM6

DQ60

VSS_46

VSS_41DQ53

DQ55VSS_44

DQ54VSS_42

DQ61

DQ52

DQ44

VSS_34DQS5*

VSS_37DQ46DQ47

VSS_39

DQ45

DQS5

VSS_32

DM4

VSS_27

VSS_29

DQ36

VREFCAVDD_17

DQ37

DQ38DQ39

VSS_30

BA1

NC_1

VDD_13

VDD_11

VDD_15

ODT0

CK1

A0A2

A6A4

A7A11

VDD_9

VDD_7

VDD_5

VDD_3

A15A14

CKE1

VDD_1

DM1

DQ15DQ14

DQ13

VSS_11

VSS_9

RESET*

VSS_13DQ20

DQ12

DQ7DQ6

DQ5DQ4

VSS_7

DQS0*VSS_2

VSS_0

DQS0VSS_5

DQ21VSS_15

DM2VSS_16DQ22

VSS_18DQ23

DQ28

VSS_20DQ29

DQS3VSS_23

DQS3*

DQ30DQ31

VSS_25

VSS_14DQ17

DQS2*

VSS_17DQS2

DQ18DQ19

DQ25DQ24

DM3VSS_22

DQ27

VSS_24

CK1*

RAS*

S0*

ODT1

VSS_33

VSS_48

KEY

(2 OF 2)




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

- =I2C_SODIMMB_SCL


TO FACILITATE BITSWAPS WITH ALIASES- ALL DQ, DQS, DM SIGNALS;

(NONE)


Page Notes

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMB_SDA


DIMM1 SPD ADDR=0XA2(WR)/0XA3(RD) DIMM3 SPD ADDR=0XA6(WR)/0XA7(RD)

DIMM 1

DIMM 3

32 OF 110

051-7845

A.0.0


113B

204B203B

26B25B

20B19B

14B

196B195B

13B

190B189B

185B

184B

179B178B

173B172B

168B167B

9B

162B161B

156B155B

151B150B

145B144B

139B138B

8B

134B133B

128B127B

72B71B

66B65B

61B

60B

3B

55B54B

49B48B

44B43B

38B37B

32B31B

2B1B

126B

199B

100B99B

94B93B

88B87B

82B81B

76B

124B123B

118B117B

112B111B

106B105B

75B

125B

200B

202B201B

197B

121B

114B

30B

110B

120B

116B

122B

77B

198B

186B188B

169B171B

152B154B

135B137B

62B64B

45B47B

27B29B

10B12B

23B21B

18B

16B

194B

192B

182B180B

6B

193B

191B

183B181B

176B

174B

166B164B

177B175B

4B

165B163B

160B

158B

148B146B

159B

157B

149B

147B

17B

142B

140B

132B130B

143B141B

131B129B

70B

68B

15B

58B56B

69B

67B

59B57B

52B

50B

42B40B

7B

53B51B

41B39B

36B

34B

24B22B

35B

33B

5B

187B

170B

153B

136B

63B

46B

28B

11B

74B73B

104B102B

103B101B

115B

79B

108B109B

85B

89B

86B

90B91B 92B

95B 96B97B

78B80B

119B

83B 84B

107B

98B

J3200

113A

204A203A

26A25A

20A19A

14A

196A195A

13A

190A189A

185A

184A

179A178A

173A172A

168A167A

9A

162A161A

156A155A

151A150A

145A144A

139A138A

8A

134A133A

128A127A

72A71A

66A65A

61A

60A

3A

55A54A

49A48A

44A43A

38A37A

32A31A

2A1A

126A

199A

100A99A

94A93A

88A87A

82A81A

76A

124A123A

118A117A

112A111A

106A105A

75A

125A

200A

202A201A

197A

121A

114A

30A

110A

120A

116A

122A

77A

410409

198A

186A188A

169A171A

152A154A

135A137A

62A64A

45A47A

27A29A

10A12A

23A21A

18A

16A

194A

192A

182A180A

6A

193A

191A

183A181A

176A

174A

166A164A

177A175A

4A

165A163A

160A

158A

148A146A

159A

157A

149A

147A

17A

142A

140A

132A130A

143A141A

131A129A

70A

68A

15A

58A56A

69A

67A

59A57A

52A

50A

42A40A

7A

53A51A

41A39A

36A

34A

24A22A

35A

33A

5A

187A

170A

153A

136A

63A

46A

28A

11A

74A73A

104A102A

103A101A

115A

79A

108A109A

85A

89A

86A

90A91A 92A

95A 96A97A

78A80A

119A

83A 84A

107A

98A

J3200

2

1R3241

2

1R3240

2

1 C3240

2

1R3242

2

1R3243

2

1 C3250

2

1 C3251

2

1 C3235

2

1 C3236

2

1 C3230

2

1 C3231

=MEM_B_DQ<58>=MEM_B_DQ<59>

MEM_DIMM1_SA<0>=PPSPD_S0_MEM_BMEM_DIMM1_SA<1>

=MEM_B_DQ<51>

=MEM_B_DM<7>

=PP0V75_S0_MEM_VTT_B

MEM_B_A<5>

MEM_B_A<15>MEM_B_A<14>

MEM_B_A<7>


MEM_B_A<8>

MEM_B_A<1>

=MEM_B_CLK_N<0>

=PP1V5_S3_MEM_B

MEM_B_A<10>MEM_B_BA<0>

=PP1V5_S3_MEM_B

=MEM_B_DQS_N<3>

=MEM_B_DQ<22>

=MEM_B_DQ<12>

=MEM_B_DQ<13>

=MEM_B_CLK_P<3>

=MEM_B_CLK_N<3>

MEM_B_BA<1>MEM_B_RAS_L

MEM_B_CS_L<2>MEM_B_ODT<2>

MEM_B_ODT<3>

=PP1V5_S3_MEM_B

MEM_B_A<0>

=MEM_B_DQ<3>

=MEM_B_DQ<9>

=MEM_B_DQS_N<1>=MEM_B_DQS_P<1>

=MEM_B_DQ<26>

MEM_B_CKE<2>

MEM_B_BA<2>

MEM_B_A<9>

MEM_B_A<8>

=PP1V5_S3_MEM_B

=MEM_B_CLK_N<2>

MEM_B_A<10>MEM_B_BA<0>

MEM_DIMM3_SA<0>

=PP0V75_S0_MEM_VTT_BMEM_DIMM3_SA<1>=PPSPD_S0_MEM_B

=MEM_B_DM<7>




=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>



=MEM_B_DM<5>



=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>


MEM_B_CS_L<3>

MEM_B_A<13>

MEM_B_CAS_LMEM_B_WE_L

=MEM_B_CLK_P<2>


MEM_B_A<5>

MEM_B_A<12>

=MEM_B_DQ<11>

=MEM_B_DQ<16>

=MEM_B_DQ<10>

=MEM_B_DQ<8>

=MEM_B_DM<0>

=MEM_B_DQ<2>

PP0V75_S3_MEM_VREFDQ_B


=I2C_SODIMMB_SCL=I2C_SODIMMB_SDA


=MEM_B_DQ<63>

=MEM_B_DQS_P<7>=MEM_B_DQS_N<7>

MEM_EVENT_L

=MEM_B_DQ<62>

=MEM_B_DM<6>

=MEM_B_DQ<60>

=MEM_B_DQ<53>


=MEM_B_DQ<61>

=MEM_B_DQ<52>

=MEM_B_DQ<44>

=MEM_B_DQS_N<5>


=MEM_B_DQ<45>

=MEM_B_DQS_P<5>

=MEM_B_DM<4>

=MEM_B_DQ<36>


=MEM_B_DQ<37>


MEM_B_A<2>


MEM_B_A<7>

MEM_B_A<11>


MEM_B_CKE<3>

=MEM_B_DM<1>


=MEM_B_DQ<13>

MEM_RESET_L

=MEM_B_DQ<20>

=MEM_B_DQ<12>


=MEM_B_DQ<5>

=MEM_B_DQ<4>


=MEM_B_DQ<21>

=MEM_B_DM<2>


=MEM_B_DQ<28>

=MEM_B_DQ<29>



=MEM_B_DQ<17>

=MEM_B_DQS_N<2>

=MEM_B_DQS_P<2>



=MEM_B_DM<3>

=MEM_B_DQ<27>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_CAS_L

MEM_B_A<3>



=MEM_B_DQ<5>

=MEM_B_DQ<4>




=MEM_B_DM<0>

=MEM_B_DQ<20>


MEM_RESET_L=MEM_B_DM<1>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DM<2>

=MEM_B_DQS_P<3>


MEM_B_CKE<1>

MEM_B_A<11>


=MEM_B_CLK_P<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_RAS_L

=MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_CS_L<0>




=MEM_B_DM<4>

=MEM_B_DQ<47>

=MEM_B_DQ<44>

=MEM_B_DQ<46>


=MEM_B_DQ<45>

=MEM_B_DQ<52>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<53>

=MEM_B_DM<6>



MEM_EVENT_L


=I2C_SODIMMB_SDA=I2C_SODIMMB_SCL


=MEM_B_DQ<8>

=MEM_B_DQ<9>


=MEM_B_DQ<16>


=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQS_P<2>

=MEM_B_DQS_N<2>

=MEM_B_DQ<24>

=MEM_B_DQ<19>

=MEM_B_DQ<26>

=MEM_B_DM<3>

=MEM_B_CLK_P<0>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<4>

=MEM_B_DQ<35>


=MEM_B_DM<5>


=MEM_B_DQ<48>

=MEM_B_DQS_N<6>

=MEM_B_DQS_P<6>

=MEM_B_DQ<49>

=MEM_B_DQ<50>


MEM_DIMM3_SA<0>

MEM_DIMM3_SA<1>

=PPSPD_S0_MEM_B

MEM_DIMM1_SA<0>

MEM_DIMM1_SA<1>

=PPSPD_S0_MEM_B




=PPSPD_S0_MEM_B

=MEM_B_DQ<25>

MEM_B_BA<2>

MEM_B_A<12>

MEM_B_A<9>

MEM_B_CKE<0>

=MEM_B_DQ<27>

=MEM_B_DQ<32>

MEM_B_WE_L

DDR3 SO-DIMM CONNECTOR BSYNC_MASTER=MASTER SYNC_DATE=N/A

F-RT-TH

CRITICAL

DDR3-SODIMM-DUAL

DDR3-SODIMM-DUAL

F-RT-TH

CRITICAL

MF-LF1/16W5%

402

10K

MF-LF1/16W

402

5%10K

CERM402-LF

6.3V

2.2UF20%

5%

402

1/16WMF-LF

10K

MF-LF1/16W5%

402

10K

CERM402-LF

20%2.2UF6.3V

2.2UF20%6.3V

402-LFCERM

2.2UF6.3VCERM

20%

402-LF

20%0.1UF

CERM402

10V

402-LF

6.3V20%2.2UF

CERM402CERM10V20%0.1UF

33 32

33 32

32

32 6

32

33 32

33 32

32 6

101 32 15

33 32

101 32 15

101 32 15

101 32 15

101 32 15

101 32 15

101 32 15

33

108 32 30 6

101 32 15

101 32 15

108 32 30 6

33 32

33 32

33 32

33 32

33

33

101 32 15

101 32 15

101 16

101 16

101 16

108 32 30 6

101 32 15

33 32

33 32

33 32

33 32

33 32

101 16

101 32 15

101 32 15

101 32 15

108 32 30 6

33

101 32 15

101 32 15

32

32 6

32

32 6

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

101 16

101 32 15

101 32 15

101 32 15

33

101 32 15

101 32 15

101 32 15

101 32 15

33 32

33 32

33 32

33 32

33 32

33 32

32 29

33 32

33 32

52 32

52 32

32 6

33 32

33 32

33 32

55 49 32 31 21

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

32 29

33 32

33 32

33 32

101 32 15

101 32 15

101 32 15

101 32 15

101 32 15

33 32

101 32 15

101 16

33 32

33 32

33 32

33 32

33 32 31

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

101 15

101 32 15

101 32 15

101 32 15

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

32 29

33 32

33 32

33 32

33 32

33 32

33 32

33 32 31

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

101 15

101 32 15

101 32 15

101 32 15

33

101 15

101 15

101 32 15

33

101 32 15

101 15

33 32

33 32

33 32

33 32

32 29

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

32 6

33 32

33 32

55 49 32 31 21

33 32

33 32

52 32

52 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

33 32

32

32

32 6

32

32

32 6

32 29

32 29

32 6

32 6

33 32

101 32 15

101 32 15

101 32 15

101 15

33 32

33 32

101 32 15

IN

G S

D

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MCP CHANNEL A DQS 7 -> DIMM A DQS 7


MCP CHANNEL B DQS 7 -> DIMM B DQS 7







3.3V input must be stable before

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

DDR3 RESET Support

before 1.5V starts to rise to

avoid glitch on MEM_RESET_L.



MCP CHANNEL A DQS 0 -> DIMM A DQS 0 MCP CHANNEL B DQS 0 -> DIMM B DQS 0




MCP MEMORY CLOCK ALIASES

MCP MEMORY TEST POINT ALIASES

33 OF 110

051-7845

A.0.0


2

1

3

Q3306

2

3

1 Q33052

1R3309

2

1R3300

2

1 C3300

2

1R3301

2

1R3305

2

1R3310

MEM_RESET_RC_L

MEM_B_CLK_P<1>MAKE_BASE=TRUE

MEM_A_DQ<4>MAKE_BASE=TRUE


=MEM_A_DQ<4>


MEM_A_DQ<2>MAKE_BASE=TRUEMEM_A_DQ<1>MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUEMEM_A_DQ<63>





=MEM_A_DQ<58>

MAKE_BASE=TRUEMEM_A_DQS_N<7> =MEM_A_DQS_N<7>


=MEM_A_DQ<15>

=MEM_A_DQ<13>

MEM_A_DM<1>MAKE_BASE=TRUE

MEM_A_DQS_P<1>MAKE_BASE=TRUE


MAKE_BASE=TRUEMEM_A_DQ<7> MAKE_BASE=TRUEMEM_A_DM<0>

MEM_A_DQS_N<0>MAKE_BASE=TRUE =MEM_A_DQS_P<0>

=MEM_A_DQ<7>

=MEM_A_DQ<1>

=MEM_A_DQS_P<1>=MEM_A_DM<1>

=MEM_A_DQS_N<1>


=MEM_A_DQ<6>

MEM_A_DQS_N<2>MAKE_BASE=TRUE

MEM_B_DQS_N<1>MAKE_BASE=TRUE

MEM_B_DQ<11>MAKE_BASE=TRUE

=MEM_B_DQS_P<6>


=MEM_A_DQS_P<5>

=MEM_A_DM<4>

=MEM_A_DQS_N<4>

=MEM_A_DQ<39>=MEM_A_DQ<38>=MEM_A_DQ<37>

MEM_B_DQS_P<6>MAKE_BASE=TRUEMEM_B_DM<6>MAKE_BASE=TRUE


MAKE_BASE=TRUEMEM_B_DQ<52>

=MEM_B_DQ<4>


=MEM_B_DQ<1>

=MEM_B_DQ<3>=MEM_B_DQ<2>=MEM_B_DQ<5>

=MEM_B_DQ<23>



=MEM_A_DQ<24>

=MEM_A_DQ<27>

=MEM_A_DQS_N<3>







MAKE_BASE=TRUEMEM_B_DQ<9> MAKE_BASE=TRUEMEM_B_DQ<10>

=MEM_B_DQS_N<1>

=PP3V3_S5_MEMRESET

=MEM_A_DQ<23>

=MEM_A_DQ<16>

=MEM_A_DQ<17>MEM_A_DQ<19>

MAKE_BASE=TRUE



=MEM_B_DM<3>

=MEM_B_DQ<30>

=MEM_B_DQ<29>

=MEM_B_DQ<27>

=MEM_B_DQ<25>

=MEM_A_DM<2>

=MEM_A_DQ<21>

=MEM_A_DQS_P<3>=MEM_A_DM<3>=MEM_A_DQ<31>


=MEM_A_DQS_P<4>

=MEM_B_DM<6>


=MEM_A_DQS_N<5>

=MEM_A_DQ<32>

=MEM_A_DQ<18>

=MEM_A_DQ<19>








MAKE_BASE=TRUEMEM_B_DQS_N<7>

=MEM_B_DQ<61>


MEM_B_DQS_N<0>MAKE_BASE=TRUE =MEM_B_DQS_P<0>





MEM_A_DQ<10>MAKE_BASE=TRUEMEM_A_DQ<9>MAKE_BASE=TRUE






MAKE_BASE=TRUEMEM_A_DQ<36>MEM_A_DQ<35>

MAKE_BASE=TRUE






=MEM_A_DQ<50>

=MEM_A_DM<7>=MEM_A_DQ<63>






=MEM_A_DQS_P<2>







MEM_B_DQS_P<2>MAKE_BASE=TRUE



=MEM_B_DM<0>


MAKE_BASE=TRUEMEM_B_DQS_P<3>MEM_B_DM<3>

MAKE_BASE=TRUE

MEM_B_DM<0>MAKE_BASE=TRUE





MAKE_BASE=TRUEMEM_B_DQS_P<4>




=MEM_A_DQS_N<6>

=MEM_B_DQ<57>=MEM_B_DQ<58>=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<62>=MEM_B_DQ<63>=MEM_B_DM<7>


=MEM_B_DQ<48>


=MEM_B_DQ<55>

=MEM_B_DQ<34>


=MEM_B_DQ<22>

=MEM_B_DQS_P<1>

=MEM_A_DQS_N<2>

=MEM_A_DQ<42>

=MEM_A_DQS_P<6>=MEM_A_DM<6>=MEM_A_DQ<55>


=MEM_A_DQ<62>=MEM_A_DQ<57>=MEM_A_DQ<56>

=MEM_A_DQ<59>



MEM_A_DQ<34>MAKE_BASE=TRUEMAKE_BASE=TRUE

MEM_A_DQ<33>

MEM_A_DQS_N<6>MAKE_BASE=TRUEMEM_A_DQS_P<6>MAKE_BASE=TRUE




MEM_A_DQ<58>MAKE_BASE=TRUEMEM_A_DQ<57>MAKE_BASE=TRUEMEM_A_DQ<56>MAKE_BASE=TRUE

=MEM_B_DQS_P<2>

=MEM_B_DM<2>


MAKE_BASE=TRUEMEM_A_DQ<12>MEM_A_DQ<13>

MAKE_BASE=TRUE


=MEM_A_DQ<10>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<2>

=MEM_B_DQ<0>



=MEM_B_DQ<21>


MAKE_BASE=TRUEMEM_B_DM<4>


MAKE_BASE=TRUEMEM_A_DQS_N<3>


MAKE_BASE=TRUEMEM_A_DQS_P<3>

=MEM_A_DQ<40>




=MEM_A_DQS_P<7>




MAKE_BASE=TRUEMEM_A_DQ<44> MAKE_BASE=TRUEMEM_A_DQ<45>MEM_A_DQ<46>

MAKE_BASE=TRUE





=MEM_B_DQ<8>


=MEM_B_DQ<26>

=MEM_B_DM<4>

=MEM_B_DQ<38>





=MEM_A_DQ<41>




MAKE_BASE=TRUEMEM_B_DM<1>


MEM_B_DQ<14>MAKE_BASE=TRUEMEM_B_DQ<13>MAKE_BASE=TRUE


=MEM_A_DQ<11> =MEM_B_DQ<11>

=MEM_B_DQ<9>

=MEM_B_DQ<12>

=MEM_B_DQ<10>


=MEM_B_DQ<15>=MEM_B_DM<1>


=MEM_A_DQ<20>

=MEM_A_DQ<22>

=MEM_B_DQ<20>



MEM_B_DM<2>MAKE_BASE=TRUE


=MEM_A_DQ<12>



=MEM_B_DQ<24>MAKE_BASE=TRUE

MEM_B_DQ<24> MAKE_BASE=TRUEMEM_B_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<25>

MAKE_BASE=TRUEMEM_B_DQ<32> MAKE_BASE=TRUEMEM_B_DQ<33>

=MEM_A_DM<5>=MEM_A_DQ<47>



=MEM_B_DQ<52>

=MEM_B_DQ<49>

=MEM_B_DM<5>

=MEM_A_DQ<46>


=MEM_B_DQ<51>MAKE_BASE=TRUE

MEM_B_DQ<51>=MEM_A_DQ<51>=MEM_A_DQ<52>

=MEM_B_DQ<50>



=MEM_A_DQ<45>




=MEM_A_DM<0>


=MEM_A_DQS_N<0>


=MEM_B_DQS_N<6>

=MEM_B_DQ<40>MAKE_BASE=TRUEMEM_B_DQ<41> MAKE_BASE=TRUEMEM_B_DQ<42>


=MEM_B_DQ<45>


=MEM_B_DQS_N<5>MEM_B_DQS_N<5>MAKE_BASE=TRUEMEM_B_DQS_P<5>MAKE_BASE=TRUEMEM_B_DM<5>MAKE_BASE=TRUEMEM_B_DQ<47>MAKE_BASE=TRUEMEM_B_DQ<46>MAKE_BASE=TRUE

MEM_B_DQ<44>MAKE_BASE=TRUEMAKE_BASE=TRUE

MEM_B_DQ<43>

MAKE_BASE=TRUEMEM_B_DQ<60>MEM_B_DQ<61>

MAKE_BASE=TRUE


MEM_B_DQ<63>MAKE_BASE=TRUEMAKE_BASE=TRUE

MEM_B_DM<7> MAKE_BASE=TRUEMEM_B_DQS_P<7>


=MEM_B_DQ<56>

=MEM_B_DQ<37>

=MEM_B_DQ<39>

=MEM_B_DQ<44>

=MEM_B_DQS_P<5>

=MEM_B_DQ<43>

=MEM_A_DQ<14>

=MEM_B_DQS_P<3>

=MEM_B_DQS_N<3>

=MEM_B_DQ<31>

=MEM_B_DQ<28>

=MEM_A_DQ<30>



MAKE_BASE=TRUEMEM_A_DM<4>

=MEM_A_CLK_P<0>=MEM_A_CLK_N<0>

MAKE_BASE=TRUEMEM_A_CLK_N<0>


MEM_A_CLK_N<3>MAKE_BASE=TRUEMEM_A_CLK_P<4>MAKE_BASE=TRUE =MEM_A_CLK_N<3>

=MEM_B_CLK_P<0>MEM_B_CLK_P<0>MAKE_BASE=TRUE =MEM_B_CLK_N<0>

=MEM_B_CLK_N<1>MEM_B_CLK_N<1>MAKE_BASE=TRUE =MEM_B_CLK_P<2>MEM_B_CLK_P<3>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_B_CLK_N<4>

MAKE_BASE=TRUEMEM_A_DM<3>


=MEM_A_CLK_P<2>MEM_A_CLK_N<1>

MAKE_BASE=TRUE

MEM_A_CLK_P<1>MAKE_BASE=TRUE

MAKE_BASE=TRUEMEM_A_CLK_P<0>

MEM_A_CLK_P<3>MAKE_BASE=TRUE

=MEM_B_CLK_N<3>

MEM_B_A<15>

MAKE_BASE=TRUEMEM_B_CLK_P<4>

MAKE_BASE=TRUETP_MEM_B_A<15> MAKE_BASE=TRUETP_MEM_A_A<15>

MEM_B_CLK_N<3>MAKE_BASE=TRUE

MEM_A_A<15>

=MEM_B_CLK_P<3>=MEM_B_CLK_N<2>

=MEM_B_CLK_P<1>

MAKE_BASE=TRUEMEM_A_CLK_N<4>

MEM_B_CLK_N<0>MAKE_BASE=TRUE

MCP_MEM_RESET_L

MEM_RESET

=PP1V5_S3_MEMRESET

MEM_RESET_L


DDR3 SUPPORT AND BITSWAPS

402MF-LF1/16W

MEMRESET_HW

20K5%

32 31

MF-LF

MEMRESET_HW

5%

402

20K

1/16W

SOT23-HF12N7002

MEMRESET_HW

SOT23MMBT3904G

MEMRESET_HW402

0

1/16W5%

MF-LF

MEMRESET_MCP

16

MF-LF402

1/16W5%

10K

MEMRESET_HW

10V

MEMRESET_HW

0.1UF20%

CERM402

5%1/16WMF-LF

1K

402

101 15

101 15

101 15 31

31

31

101 15

101 15 101 15

101 15

101 15

101 15

101 15

31

31

31

101 15 31

31

31

31

31

101 15

101 15

101 15

101 15

101 15

101 15

31

31

31

31

31

31

101 15

31

101 15

101 15

101 15

32

101 15

31

31

31

31

31

31

101 15

101 15

101 15

101 15

32

101 15

32

32

32

32

32

101 15

101 15

31

31

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

6

31

31

31

101 15

101 15

101 15

32

32

32

32

32

31

31

31

31

31

31

31

31

32

101 15

31

31

31

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

101 15

101 15

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

31

31

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

32

31

31

31

31

31

31

31

31

31

31

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

32

31

31

101 15

101 15

101 15

31

32

32

32

32

32

101 15

32

101 15

101 15

101 15

101 15

101 15

101 15

31

101 15

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

32

32

32

32

32

32

32

32

32

32

101 15

101 15

31

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

31 32

32

32

32

32

32

32

32

101 15

31

31

32

101 15

101 15

101 15

101 15

31

101 15

32

32

32 101 15

101 15

31

31

101 15

101 15

31

31

31

31

31

31

32

32

32

31

32

32

32 101 15 31

31

32

101 15

31

31

31

101 15

31

31

101 15

31

101 15

31

101 15

32

32

101 15

101 15

101 15 32

32

32

32 101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15

101 15 32

32

32

32

32

32

31

32

32

32

32

31

101 15

101 15

101 15

31

31 101 15

31

31

101 16

101 16

31

32 101 15

32

32 101 15

32 101 16

101 16

101 15

31

31

31

101 15

101 15

101 15

101 16

32

32

101 16

101 16

31

32

32

32

101 16

101 15

6

IN

OUT

OUT

IN

IN

OUT

OUT

SYM_VER-1

IN

IN

SYM_VER-2




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518S0731

34 OF 110

051-7845

A.0.0


4

3 2

1

L3440

9

8

7

6

5

4

3

2

18

17

16

15

14

13

12

11

10

1

J34004 3

21

L3430

21

L3400

21

C3430

21

C3431

2

1C3402

2

1C3401

2

1C3400

PCIE_CLK100M_MINI_CON_NPCIE_CLK100M_MINI_CON_P

PCIE_MINI_R2D_L_P

PCIE_MINI_R2D_L_N

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_PPCIE_MINI_R2D_N

PCIE_WAKE_LMINI_CLKREQ_L

PP3V3_MINIVOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

MINI_RESET_L

PCIE_CLK100M_MINI_N

PCIE_MINI_D2R_NPCIE_MINI_D2R_P

=PP3V3_S3_MINI

PCIE_CLK100M_MINI_P


PCI-E Wireless Connector

12-OHM-100MATCM1210-4SM

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

F-ST-SM20247-916E-01F

CRITICAL

102 17

102 17

PLACEMENT_NOTE=PLACE CLOSE TO J3400.

90-OHM-100MADLP11S

FERR-120-OHM-1.5A

0402-LF

102 17

102 17

102 17

102 17

17

17

9

0.1uF

402

10%

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

X5R16V

402X5R

10%16V

0.1uF

PLACEMENT_NOTE=PLACE CLOSE TO U1400.

10uF

X5R20%

6.3V

603

0.1uF10V

CERM20%

402

10V0.1uF

402

20%CERM

6




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8 7 5 4 2 1

35 OF 110

051-7845

A.0.0


BLANK PAGESYNC_MASTER=K51 SYNC_DATE=12/08/2008




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36 OF 110

051-7845

A.0.0



TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]MDI+[2]

MDI+[3]

MDI+[1]MDI-[1]

ENSWREG

TXD[1]TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN

IN

IN

IN

IN

IN

BI

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN




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8 7 5 4 2 1

Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

If internal switcher is used, must place inductor within 5mmof U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

If internal switcher is used, must place 1x 22uF &

Configuration Settings:

PHYAD = 01 (PHY Address 00001)

AN[1:0] = 11 (Full auto-negotiation)

TXDLY = 0 (No TXCLK Delay)RXDLY = 0 (RXCLK transitions with data)

WF: Marvell numbers, update for Realtek

(221mA typ - 1000base-T)

( 7mA typ - Energy Detect)

(19mA typ - Energy Detect)(43mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

If internal switcher is not used, VDDREG and REGOUT can float.

per RealTek request.

Reserved for EMI

WF: Verify that ENET_RESET_L does not assert when WOL is active.

If false, ENET_RESET_L should be removed.If true, RC and 0-ohm resistor should be removed.

37 OF 110

051-7845

A.0.0


21R3780

2

1C3790

2

1C3714

2

1C3710

2

1C3711

2

1

L3715

2

1C3716

2

1C3715

2

1R3751

2

1R3750

2

1R3757

2

1R3752

2

1R3756

2

1R3755

21R3795

21R379421R379321R379221R3791

21R3790

2

1 C3702

2

1 C3701

2

1 C3700

2

1 C3706

45

44

26

25

24

23

27

22

18

17

16

14

13

19

46

48

29

31

11

12

8

9

4

5

1

2

30

38

35

34

47

33

207

3

39

37

21

15

36

28

32

43

42

41

6 40

10

U3700

2

1 C3705

2

1

L3705

2

1R3720

2

1R3725

2

1R3730

2

1 C3725

21

R3724

=PP3V3_ENET_PHY_VDDREG

MIN_LINE_WIDTH=0.6 MMPP3V3_ENET_PHYAVDD


ENET_TXD<1>

ENET_MDIO

ENET_TX_CTRL

ENET_CLK125M_TXCLK ENET_CLK125M_TXCLK_R

=RTL8211_REGOUT

ENET_CLK125M_RXCLK_R

ENET_RXD_R<1>

ENET_RXD_R<3>

ENET_RXCTL_R

RTL8211_PHYAD1

ENET_TXD<2>

ENET_RX_CTRL

ENET_RXD<3>ENET_RXD<2>ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

=PP1V05_ENET_PHY

ENET_MDI_N<1>ENET_MDI_P<1>

ENET_MDI_P<3>ENET_MDI_N<3>

RTL8211_RXDLY

ENET_MDI_P<2>ENET_MDI_N<2>

=RTL8211_ENSWREG

ENET_MDC

ENET_RESET_L

RTL8211_CLK25M_CKXTAL1

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MMPP1V05_ENET_PHYAVDD

VOLTAGE=1.05V

RTL8211_PHYAD0

ENET_MDI_N<0>ENET_MDI_P<0>

ENET_RXD_R<2>

ENET_RXD_R<0>ENET_TXD<0>

TP_RTL8211_CLK125

TP_RTL8211_CKXTAL2

=PP3V3_ENET_PHY

RTL8211_RSET

RTL8211_PHYRST_L

ENET_TXD<3>

SYNC_MASTER=K51

Ethernet PHY (RTL8211CL)SYNC_DATE=12/08/2008

104 18 1/16W 402

22MF-LF5%

NO STUFF

10PF50VCERM

5%

402

0.1UF

X5R402

10%16V

10%

402X5R16V

0.1UF

402

10%

X5R16V

0.1UF CRITICAL

0402-LFFERR-120-OHM-1.5A

10%

402X5R

0.1UF16V

10%

402X5R16V

0.1UF

402

1/16W5%4.7K

MF-LF402

MF-LF

4.7K5%

1/16W

1/16W5%

MF-LF

4.7K

402

1/16W

4.7K5%

402MF-LF

38

1/16W5%

MF-LF

4.7K

402

1/16W5%

MF-LF

4.7K

402

104 18

104 18

104 18

104 18

104 18

104 18

5% 1/16W MF-LF22

402

5% 1/16W MF-LF22

402

5% 1/16W MF-LF22

402

225% 1/16W MF-LF 402

225% 1/16W MF-LF 402

40222

1/16W5% MF-LF

104 39

104 39

104 39

104 39

104 39

104 39

104 39

104 39

104 38

18

104 18

104 18

104 18

104 18

104 18

104 18

104 18

10%

402X5R16V

0.1UF10%

402X5R

0.1UF16V

10%

402X5R16V

0.1UF

402X5R

0.1UF10%16V

TQFP

RTL8211CLGR

OMITCRITICAL

402X5R16V

0.1UF10%

0402-LFFERR-120-OHM-1.5A

CRITICAL

402

1/16W5%

MF-LF

10K

MF-LF402

4.7K5%1/16W

NOSTUFF

402

1/16W1%

MF-LF

2.49K

402

0.1UF

CERM

20%10V

NOSTUFF

402MF-LF

5%1/16W

100

38

38

104

104

104

104

38

104

104

38

IN OUT

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

D SG

D S




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ENET ALIASES

NOTE: NOT USING THE BUILT-IN 1.05V REGULATOR OF THE PHY

RTL8211 25MHz ClockNOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

3.3V ENET FET

1.1V ENET FET

38 OF 110

051-7845

A.0.0


2

1

3

Q3850

2

1

3

Q3800

1

9

6

8

2

3

4

7

5

U3850

2

1 C3850

2

1 C3800

1

9

6

8

2

3

4

7

5

U3800

21

R3895

=RTL8211_ENSWREG

MCP_CLK25M_BUF0_R

=RTL8211_REGOUT

=PP3V3_ENET_PHY=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_PHY=PP1V05_ENET_MCP_PLL_MAC=PP1V05_ENET_MCP_RMGT

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUENC_RTL8211_REGOUT

NO_TEST=TRUE

NO_TEST=TRUE

NC_PP3V3_ENET_PHY_VDDREGMAKE_BASE=TRUE

MAKE_BASE=TRUEPP3V3_RMGT

MAKE_BASE=TRUEPP1V1_RMGT

RTL8211_CLK25M_CKXTAL1

ENET_EN

ENET_EN



MIN_LINE_WIDTH=0.5 mmVOLTAGE=1.05VPP1V1_RMGT

=PP12V_S5_PWRCTL

=PP1V1_S5_ENET_FET


VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mmMAX_NECK_LENGTH=3 MM


PP3V3_RMGT

=PP12V_S5_PWRCTL

=PP3V3_S5_ENET_FET

P1V1_ENET_EN

P3V3_ENET_EN

MAKE_BASE=TRUE

Ethernet SupportSYNC_MASTER=MASTER SYNC_DATE=N/A

CRITICAL

SOT23IRLML2502GPBF

IRLML2502GPBFSOT23

CRITICAL

70 38

TDFNSLG5AP001

CRITICAL

402

10%16VX5R

0.1UF

70 38

402

0.1UF10%

X5R16V

TDFNSLG5AP001

CRITICAL

104 37

1/16WMF-LF

5%


22

402

104 18

37

37

37

25 18

37

25

25 18

37

38

38

38

78 70 38 6

6

38

78 70 38 6

6

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

TD1+

TCT1

TCT2

TD1-

TD2+

TD2-

TD3+

TCT3

TD3-

TD4+

TCT4

TD4-

1CT:1CT

1CT:1CT

1CT:1CT

1CT:1CT

ENET_MDITRAN_P0TRAN_N0TRAN_P1

TRAN_P2TRAN_N2TRAN_N1TRAN_P3

TRAN_N3

PINSSHIELD




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NOTE: Check with PHY and Magnetics MFR to determine what to do with center taps.

NOTE: BOB SMITH TERMINATION FOR EMC.

PLACE ONE CAP PER TCT PIN

514-0654

39 OF 110

051-7845

A.0.0


7

4

3

1

8

5

6

2

9

10

J3900

11

12

8

9

5

6

2

3

10

7

4

1

14

13

17

16

20

19

23

22

15

18

21

24

T3900

2

1 C3904

2

1 C3903

2

1 C3902

2

1 C3901

2

1 C3900

2

1R3903

2

1R3902

2

1R3901

2

1R3900

CRITICAL

CRITICAL

LFE9287APF

ENET_MCT_BS

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MM

ENET_MCT3

ENET_MDI_T_P<3>

ENET_MDI_N<1>

ENET_MDI_P<3>

ENET_MDI_N<0>

ENET_MDI_T_P<0>ENET_MDI_P<0>

ENET_MDI_P<2>

ENET_MDI_N<3>

ENET_MCT2

ENET_MDI_T_N<3>

ENET_MDI_T_N<0>

ENET_TCT

ENET_MDI_N<2>

ENET_MDI_P<1>

ENET_MDI_T_N<2>

ENET_MCT0

ENET_MCT1

ENET_MDI_T_P<2>

ENET_MDI_T_N<1>

ENET_MDI_T_P<1> ENET_MDI_T_P<0>ENET_MDI_T_N<0>

ENET_MDI_T_P<3>

ENET_MDI_T_P<1>

ENET_MDI_T_N<2>ENET_MDI_T_N<1>

ENET_MDI_T_N<3>

ENET_MDI_T_P<2>

ETHERNET CONNECTORSYNC_MASTER=MASTER SYNC_DATE=N/A

RJ45-10/100TX-K22F-ANG-TH

SOI

CERM10V

0.1UF20%

402

10VCERM

0.1UF20%

402CERM10V

0.1UF20%

402CERM10V

0.1UF20%

402

1206

1000PF10%

NOSTUFF

2KVCERM

MF-LF402

1/16W5%7575

1/16WMF-LF402

5%

MF-LF

75

402

5%1/16W

755%

MF-LF402

1/16W

104 39

104 37

104 37

104 37

104 39 104 37

104 37

104 37 104 39

104 39

104 37

104 37

104 39

104 39

104 39

104 39 104 39

104 39

104 39

104 39

104 39

104 39

104 39

104 39




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40 OF 110

051-7845

A.0.0



OUT TRI-ST/NC

VCC

GND

NC

NCNC

NCNCNCNCNCNCNCNC

NCNCNCNCNCNCNCNCNC

NCNCNC

NCNCNCNCNCNCNCNC

OUT

IN

IN

OUT

IN

OUT

OUT

BI

BI

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

RSVD_19

LKON_DS2_P

XI

CNACPS

PD

R1R0

D6D5D4

D3D2D1D0

CTL0CTL1

LREQ_PLREQ_L

LPS_PLPS_L

PINT_P

PCLK_P

PINT_L

LCLK_PLCLK_L

LINKON_LDS1DS0

PC2

PC0

PC1

PHY_RESET*

TPB2_NTPB2_P

TPB1_NTPB1_PTPB0_NTPB0_P

TPA2_NTPA2_P

TPA1_NTPA1_PTPA0_NTPA0_P

TPBIAS2TPBIAS1

TPBIAS0

SE

TESTW_VREG_PD

SM

TESTM

BMODE

PLLGNDGND

DVDD_3_3

PLLVDD_3_3

VDDA_33 AVDD_3_3 VDD_15 VDDA_15 DVDD_CORE

VDD_15_COMB

VDD_33_COM_IO

VDD_33_COMB

VDD_33

PLLVDD_CORE

PCLK_L

VSSA_PCIEVSSAVSS

REF0_PCIE

REF1_PCIE

PERST*

RXNRXP

TXN

TXP

CLKREQ*

REFCLK_P

REFCLK_M

REFCLK_SEL

SCLSDA

GPIO0

GPIO2GPIO1

GPIO3

GPIO4GPIO5

GPIO7GPIO6

OHCI_PME*

GRST*

RSVD_1RSVD_0

RSVD_3

RSVD_2

RSVD_4

RSVD_6RSVD_5

RSVD_9

RSVD_7RSVD_8

RSVD_10

RSVD_11

RSVD_14

RSVD_12RSVD_13

RSVD_16RSVD_17RSVD_18

RSVD_15

D7

CYCLEOUT

PCI EXPRESS

1394B OHCI & PHY

IN

IN

IN




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Strap DSx high on unused ports.

page assumes no more than

Alias =FWPHY_PC0

(JTAG_TCK)

(JTAG_TDI)

(JTAG_TDO)

(JTAG_TMS)

(IPU)

(IPU)

Ground TPBx_P/TPBx_N

PC[0:2] = ’100’Multiple-ports:

Unused Ports:

TP/NC TPAx_P/TPAx_N

TP/NC TPBIASx

Single-port:

DS2 hard-strapped to 1,

2 FW800 connectors

PC[0:2] = ’000’

as appropriate

(VDD_33_AUX)

Power Aliases:

FWRS0_FWXIO nets are OHCI/PCIe power, andcan be S0.

5K pull-down device detect circuit.

For single-port systems, all FW power shouldbe tied together and powered by S0 or by the

FW_FWPHY nets are PHY power, and formulti-port systems must come from bus power.

(IPU)

(JTAG_TRST)

(Snoop Enable, for FireBug)

41 OF 110

051-7845

A.0.0


2

1R4189

2

1R4135

2

1C41904

13

2

Y4190

2

1R4190

2

1R4125

2

1C4120

2

1C4130

2

1C4125

2

1C4131

2

1C4132

2

1C4121

2

1C4122

2

1C4123

2

1C4126

2

1C4127

2

1C4128

2

1C4124

2

1R4171

21

R4191

2

1C4135

2

1 C4139

21

R4170

2

1R4175

2

1 C4138

2

1C4137

P4

C7

C6

C5

C4

B6

C10

F5

A7

A14

A10

C3

B5

B7

B9

B10

B11

C11

B12

M5

J10

H10

G10

E3

C12

B8

P7

M6

K10

H3

G3

A9

A8

E13

G13

K13

D14

E14

H14

J14

M14

N14

B14

C14

F14

G14

K14

L14

A6

B2

P14

P13

H12

J13

A4

A3

M12

M11

M8

L13

L12

K12

G12

F13

P3

D13

D12

P11

P10

N13

N12

N11

N10

M13

F12

E12

H13

A1

B1

A12

A13

M1

N1

M7

N7

N5

D3

D2

B4

B13

B3

F1

G1

A11

E8

E9

P8

E2

F2

C2

C1

D1

E1

H2

G2

C13

N6

P6

P5

N4

N3

P2

N2

P1

G8

G7

G6

G5

F9

F8

F7

K8

K7

K6

K5

F6

J8

J7

J6

J5

H9

H8

H7

H6

H5

G9

E7

E6

M9

F3

C9

K3

J3

C8

P9

N9

M3

M2

L3

L2

L1

K1

K2

J2

N8

J1

H1

P12

A2

J12

A5

M4

M10

K9

J9

F10

E10

U4100

2

1R41862

1R4185

2

1 C4189

2

1C4105

2

1C4104

2

1C4103

2

1C4108

2

1C4115

2

1C4107

2

1C4106

2

1C4114

2

1C4113

2

1C4102

2

1C4101

2

1C4100

2

1C4112

2

1C4111

2

1C4110

2

1R4110

2

1R4117

2

1R4119

2

1C4119

2

1C4118

2

1R4140

2

1C4117

2

1R4141

21C4140

21C4141

2

1R4152

2

1R4151

21C4145

21C4146

2

1R4150

2

1R4153

2

1R4160

2

1R4180

1

2R4182

2

1R4181

42

TP_FWPHY_CNA

1UF

402

10%

CERM

MF-LF

1K5%

402

1/16W

CERM6.3V

402

10%1UF

402

1UF

CERM6.3V10%

10%6.3V

402

1UF

CERM

402

1

MF-LF1/16W

5%

4.7

MF-LF

5%1/16W

402

98P3040MHZSM

10%6.3V

CERM-X5R402

0.22UF

15%

MF-LF1/16W

402

5%

402MF-LF

1K

1/16W

NO STUFF

MF-LF1/16W

402

5%47K

NO STUFF

1/16W

402

5%1K

MF-LF

42

1K5%

402

1/16WMF-LF

PLACEMENT_NOTE=Place C4146 next to C4145

16V10% 402X5R0.1uFPLACEMENT_NOTE=Place C4145 close to UA200

16V10% 402X5R0.1uF

402

5%

MF-LF1/16W

1K

1/16W5%

402MF-LF

220

1/16W5%

402MF-LF

220

PLACEMENT_NOTE=Place C4141 next to C4140

0.1uF 16V10% 402X5R

PLACEMENT_NOTE=Place C4140 close to U1400

16V10% 402X5R0.1uF

MF-LF402

1/16W1%232

1UF

402CERM6.3V10%

17 102

17 102

42

MF-LF1/16W

402

5%1K

9

14.3K1%

1/16WMF-LF402

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

MF-LF

15%

1/16W

402

15%

MF-LF1/16W

402

MF-LF

15%1/16W

402

1UF

402CERM

10%6.3V

1UF

CERM6.3V10%

402

17 102

6.3V

1UF

402CERM

10%

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

1UF

402

6.3V10%

1UF

402CERM6.3V

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

CERM6.3V10%1UF

1UF

402CERM6.3V10%

17 102

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

42

17 102

42

42

42

42

42

42

42

42

42 10%0.22UF6.3VCERM-X5R402

17 102

1%6.34K

402

1/16WMF-LF

5%

MF-LF1/16W

402

390K

CRITICALOMIT

BGA

XIO2213B

402

6.3VCERM

10%

CERM

1UF

402

10%6.3V

MF-LF

10K5%1/16W

402

42

402

5%

MF-LF1/16W

1K

42

42

1UF

402CERM6.3V10%

1UF

402CERM6.3V10%

1/16W

402

5%

MF-LF

22

470

402

5%1/16WMF-LF

1UF10%6.3VCERM402

402

10%6.3V

1UF

CERM

10%1UF6.3VCERM402

6.3VCERM

10%

402

1UF

CERM402

6.3V

1UF10%

6.3V

1UF

CERM402

10%6.3V10%1UF

402CERM

CERM

1UF

402

10%6.3V 6.3V

10%1UF

402CERM

FireWire LLC/PHY (XIO2213B)SYNC_MASTER=MASTER SYNC_DATE=N/A

FWOHCI_LREQ

CLK98M_FW_XI

TP_FWXIO_JTAG_TDOTP_FWXIO_JTAG_TMS

TP_FWXIO_GRST_L

FW_RESET_L

FWXIO_REFCLK_SEL

FWXIO_SDAFWXIO_SCL

FW_P1_TPBIASFW_P2_TPBIAS

FW_P2_TPA_NFW_P2_TPA_P

FW_P1_TPA_P

FW_P0_TPB_P

=PPVP_FW_PHY_CPS

FW_P0_TPA_P

FWXIO_REF1_PCIE

FWXIO_REF_PCIE

PCIE_FW_D2R_C_PPCIE_FW_D2R_C_N

TP_FWOHCI_XO

=FWPHY_DS1=FWPHY_DS0

FWXIO_REF0_PCIE

FW_P0_TPBIAS

FW_P0_TPA_N

FW_P1_TPA_N

=FW_CLKREQ_L

PCIE_CLK100M_FW_PPCIE_CLK100M_FW_N

=FW_PME_L

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_N

FWXIO_CYCLEOUT

CLK98M_FW_XI_R

FWPHY_LKON_DS2

=PP3V3_FW_FWPHY

=FWPHY_PC0

FWOHCI_LINKON_L

FWOHCI_LPS

FWPHY_PINT

FWOHCI_CLK98M_LCLK

FWPHY_CLK98M_PCLK

FWPHY_R1

FWPHY_R0

FWPHY_RESET_L

FWPHY_CPS

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PP3V3_FW_PLLVDDMIN_LINE_WIDTH=0.3 mm

=PP3V3_FWRS0_FWXIO

VOLTAGE=1.96V

PP1V96_FW_XTALMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

PCIE_FW_R2D_NPCIE_FW_R2D_P

VOLTAGE=3.3V

PP3V3_FW_AVDDMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

PP3V3_FW_VDDA


PP1V95_FW_FWPHY

FWXIO_VDD33COMIOFWXIO_VDD33COMBFWXIO_VDD15COMB

=PP3V3_FW_FWPHY

PP1V96_FW_PLLVDDMIN_LINE_WIDTH=0.3 mm

VOLTAGE=1.96VMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mmPP1V5_FW_VDDA


=PP1V5_FWRS0_FWXIO

FW_P0_TPB_N

FWXIO_SNOOP_EN

TP_FWXIO_JTAG_TDI

FWPHY_TESTM

FWPHY_BMODE

=PP3V3_FW_FWPHY

FWPHY_TESTW

42

102

102

6 41 42 43

6

102

102

42

6 41 42 43

6

6 41 42 43

OUTINNR

NC THRML

EN

GND PAD




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Apple Inc.

PAGE


A

B

C

345678

D

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8 7 5 4 2 1

Peak Current: 100mA

FireWire Aliases For Connectivity

1394 PHY STRAPPING OPTIONS

IT IS IN BILINGUL MODE PULL-UPS ASSERT/ENABLE DATA STROBE ONLY MODE.

2ND & 3RD TPA/TPB PAIR UNUSED

Place close to FireWire PHYTermination

iMacs are now one port only and have Power Code "000"

THERE ARE THREE FIREWIRE PORTS, BUT ONLY ONE IS USED.NO STUFF MEANS THAT

TI PHY requires 1UF, not 0.33uF spec value.

TI PHY "Peaking Inductors" To improve Data Eye.

1394 PHY 1.95V SUPPLY

42 OF 110

051-7845

A.0.0


21

L4251

21

L4250

21

L4253

21

L4252

2

1C4200

2

1C4201

2

1 C42027

1

2

5

6

3

4

U4200

2

1R4257

2

1R4258

2

1C4254

2

1R4254

2

1R4252

2

1R4253

2

1R4250

2

1R4251

2

1 C4250

2

1R4256

2

1R4255

402

0.01UF

=PP3V3_FW_FWPHY

MAKE_BASE=TRUE

CRITICAL

FW_P2_TPA_P

FW_P2_TPBIAS

MAKE_BASE=TRUEFW_CLKREQ_L

MAKE_BASE=TRUEFW_PORT0_TPB_PFW_P0_TPB_P

MAKE_BASE=TRUEFW_PORT0_TPB_N

MAKE_BASE=TRUEFW_PORT0_TPA_N

FW_P0_TPA_C

MAKE_BASE=TRUEFW_PHY_DS1

FW_PHY_DS0

P1V95_FW_NR

FW_P2_TPA_NMAKE_BASE=TRUENO_TEST=TRUE

NC_FW_PORT2_TPA_N

MAKE_BASE=TRUENO_TEST=TRUE

NC_FW_PORT2_TPA_P

NO_TEST=TRUE

NC_FW_PORT2_TPBIASMAKE_BASE=TRUE

FW_P1_TPA_N NC_FW_PORT1_TPA_NMAKE_BASE=TRUENO_TEST=TRUE

FW_P1_TPA_P NC_FW_PORT1_TPA_PMAKE_BASE=TRUENO_TEST=TRUE

FW_P1_TPBIAS NC_FW_PORT1_TPBIASMAKE_BASE=TRUENO_TEST=TRUE

=FW_CLKREQ_L

=FWPHY_PC0 FW_PHY_PC0MAKE_BASE=TRUE

=FWPHY_DS1

=FWPHY_DS0

=PP3V3_FW_FWPHY

=FW_PME_L FW_PME_LMAKE_BASE=TRUE

MAKE_BASE=TRUEPPVP_FW_PHY_CPS=PPVP_FW_PHY_CPS

MAKE_BASE=TRUEFW_PORT0_TPA_P

VOLTAGE=1.86VMIN_NECK_WIDTH=0.08MM

FW_P0_TPBIASMIN_LINE_WIDTH=0.1MM

FW_P0_TPA_PFW_P0_TPA_N

FW_P0_TPB_N

VOLTAGE=0VNO_TEST=TRUE

FW_P0_TPB_L_N

FW_P0_TPA_L_NVOLTAGE=1.86VNO_TEST=TRUE

FW_P0_TPB_L_PVOLTAGE=0VNO_TEST=TRUE

FW_P0_TPA_L_PVOLTAGE=1.86VNO_TEST=TRUE

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmNET_SPACING_TYPE=PWRMAX_NECK_LENGTH=3 MMVOLTAGE=1.95V

PP1V95_FW_FWPHY


FW: 1394B MISC

18NH-250MA

0402

18NH-250MA

0402

0402

18NH-250MA

0402

18NH-250MA

6.3VCERM

1UF10%

402

16VCERM

10%

402

4V20%2.2UF

X5R

SONTPS799195

1/16W5%

MF-LF402

10K

1/16W5%

MF-LF402

10K

25V5%

CERM

220PF

402402

4.99K1%1/16WMF-LF

1/16W

402MF-LF

1%56.2

MF-LF402

1/16W1%56.2

56.21/16W

402MF-LF

1%56.21/16W1%

402MF-LF

402

10%6.3V

1UF

CERM

402MF-LF1/16W5%10K

402MF-LF

NOSTUFF

5%1/16W

10K

41

41

17

105 43 41

105 43

105 43

41

41

41

41

41

43 42 41 6

41

41

41

43 42 41 6

41 19

43 41

105 43

41

41

41

41

105

105

105

105

41

GND

V+

SHIELDPINS

VGTPA-

TPA(R)

TPB- TPB(R)

TPB+ VP

TPA+

SC/NC




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D

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Apple Inc.

PAGE


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C

345678

D

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8 7 5 4 2 1

7 WATTS MAX PER PORT

POUR COPPER TO SINK HEAT

"Snapback" & "Late VG" Protection

IT IS HERE FOR SAFETY ONLYTHIS FUSE WILL NOT BLOW

FAST NON-RESETABLE FUSE

SHOULD BE DONE AS A POWER STRIP(SUBPLANE)

1394B

5.1VNC

PLACE CLOSE TO COMPARATOR

ESD Rail

IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP

CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V[ LATE VG NOTES ]

514-0656

PORT 0

12 VOLTS

5.1V

PLACE CLOSE TO COMPARITOR

INRUSH RESETABLE PTC

43 OF 110

051-7845

A.0.0


8

6

9

2

1

5

4

3

7

11

10

J4300

21XW4300

21

F4300

21

R43053 1

D4303

2

1C4305

2

1R4306

21

R4304

8

1

7

3

5

2

6

4

U4300

2

1 C4304

31

D4302

2

3

1Q4302

2

1R4301

2

1 C4302

2

1R4307

2

1R4302

2

1R4303

21

D4300

21

R4352

2 3

1 Q4301

21

R4300

4

3

65

21

Q4300

21

F4301

3

1

D43012

1 C4300

2

1R4335

2

1 C4335

2

1C4332

21

L4300

2

1C4311

2

1C4310

2

1C4313

2

1C4312

21

R4390

31

D4390

6

2

1

DP4311

6

2

1

DP4310

3

5

4

DP4311

3

5

4

DP4310

5%

0.33

MF1W

2512

MIN_LINE_WIDTH=1.7MMP12V_S5_FW_R=PP12V_S5_FW


P12V_S5_FW_DMIN_LINE_WIDTH=1.7MM

VOLTAGE=12V

FW_PORT0_VP

MIN_NECK_WIDTH=0.5MMVOLTAGE=12V

MIN_LINE_WIDTH=1.7MM

FW_PORT0_VP_F


VOLTAGE=12V

FW_CURRENT_LIMIT

=PP12V_S5_FW

FW_CURRENT_LIMIT

PP3V3_FW_ESD

FW_FET_LINEAR_LIMIT_OUTFW_FET_LINEAR_LIMIT_IN

FW_CURRENT_LIMIT_R

PP3V3_FW_ESD

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.38 mmVOLTAGE=3.3V

=PP3V3_FW_FWPHY

FW_FET_LINEAR_LIMIT_FB

FW_CURRENT_LIMIT_RD

FW_PORT0_TPA_N

FW_PORT0_TPA_PFW_PORT0_TPA_R

FW_PORT0_TPB_P

FW_PORT0_TPB_N

FW_FET_LINEAR_LIMIT_INFW_FET_LINEAR_LIMIT_OUT

FW_CURRENT_LIMIT_Q

FW_TURN_ON_V

P12V_S5_FW_CLMIN_LINE_WIDTH=1.7MMMIN_NECK_WIDTH=0.5MMVOLTAGE=12V

PPVP_FW_PHY_CPSVOLTAGE=12V



PP3V3_FW_ESD


FIREWIRE CONNECTOR

F-ANG-TH

CRITICAL

1394B-K22

SM

PLACEMENT_NOTE=PLACE CLOSE TO F4300

3AMP-32V

603

CRITICAL

100K

1/16W

402MF-LF

5%

SOT23

MMBZ5231BXG

16VX5R

10%2.2UF

603

200K1/16WMF-LF

5%

402

402MF-LF1/16W5%

100K

SOI-HFLM393

10%16V

402

0.1UF

X7R-CERM

BAS40XG

SOT23

SOT23MMBT2222A7F

5%1/16W

10K

MF-LF402

20%

CERM402

16V

0.01UF

402MF-LF1/16W5%20K

603

1/10W5%

MF-LF

15K

MF-LF1/16W

402

5%20K

SM

CRITICAL

CRS08-1.5A-30V

MF-LF

1%1/16W

51.1K

402

SOT2360V-600MAMMBT2907AXG

SSOT6

FDC610PZ

CRITICAL

0.3AMP-60V

CRITICAL

SMD030F-SM

MMBZ5231BXGSOT23

10%50VX7R

0.01UF

603-1

402

1%

MF-LF1/16W

1M

603-1

0.1UF10%50VX7R

10%

402

0.001UF

CERM50V

SM

CRITICAL

FERR-250-OHM

0.01UF50V

402

10%

X7R402

0.01UF50V10%

X7R

X7R

0.01UF50V

402

10%

X7R402

50V10%

0.01UF

1/16WMF-LF

1%

402

332

MMBZ5227BLT1HSOT23

CRITICAL

CRITICAL

BAV99DW-X-GSOT-363

BAV99DW-X-G

CRITICAL

SOT-363

BAV99DW-X-G

CRITICAL

SOT-363

CRITICAL

SOT-363BAV99DW-X-G

NOSTUFF

43 6

43

43 6

43

43

43 43

43 42 41 6

105 42

105 42

105 42

105 42

43

43

42

43




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C

A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

44 OF 110

051-7845

A.0.0



BLANK PAGE

OUTKEY

GNDGNDMD

+5V+5VDP

B-B+

GND

GNDA-A+GND

IN

IN

OUT

OUT

IN

IN

OUT




36

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DR


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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518-0361

SATA PORT A1 FOR SLIMLINE ODD

SATA PORT A0 FOR HDD

518S0251

SATA Activity LED

45 OF 110

051-7845

A.0.0


P3

P2

P4

15

14

S7

S4

S1

P6

P5

P1

S6

S5

S2

S3

J4520

7

6

5

4

3

2

1

J4510

2

1R45302

1C4531

2

1C4530

21C4519

21C4520

21C4517

21C4518

2

1

DS4599

2

1R4599

21C4516

21C4515

21C4511

21C4510

SATA_ODD_R2D_PSATA_ODD_R2D_N

SATA_ODD_D2R_C_N

=PP5V_S0_SATA

SMC_ODD_DETECT

SATA_ODD_D2R_C_P

SATA_HDD_R2D_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

MCP_SATALED_LMAKE_BASE=TRUE

TP_MCP_SATALED_L

SATA_HDD_D2R_N

SMC_EXCARD_OC_L

=PP3V3_S0_SATALED

MCP_SATALED_R_L

SATA_ODD_R2D_C_P

=PP3V3_S0_ODD

SATA_ODD_D2R_P

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_R2D_P

SATA_ODD_R2D_C_N


SATA Connectors

102 20

102 20

102 20


DEVELOPMENT

SILK_PART=SATA ACTIVE

DEVELOPMENT

1/10W5%

330

603MF-LF

102 20

102 20

102 20

102 20

0.01UF CERM 40210% 16V

40210% CERM16V0.01UF

CERM 4020.01UF 16V10%

CERM 40210% 16V0.01UF

M-ST-TH1735574

EP00-081-91M-ST-SM

CRITICAL

603MF-LF1/10W

5%33K

0.1UF

402

10%25VX5RX5R

402

25V10%0.1UF

10%0.01UF 402CERM16V

0.01UF 10% 402CERM16V

10%0.01UF 402CERM16V

10% 402CERM0.01UF 16V

102 20

110 102

110 102

110 102

6

110 49

110 102

110 102

20

50 49

6

6

110 102

110 102

110 102

EN1*

OC1*

IN OUT1

GND TPAD

OUT2

OC2*

EN2*

G S

D

EN1*

OC1*

IN OUT1

GND TPAD

OUT2

OC2*

EN2*

IO

IONC

GND

VBUS NC

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

VCC

GND

SELOE*

D+

D-

Y+

Y-

M+

M-

VBUSDATA-

GNDDATA+

VBUSDATA-

GND

DATA+

VBUS

DATA-

GNDDATA+

VBUSDATA-

GNDDATA+

IO

IONC

GND

VBUS NC

IO

IONC

GND

VBUS NC

IO

IONC

GND

VBUS NC

TABLE_5_ITEM






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A

D

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Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

514-0659

514-0659

514-0672

514-0672

(PUT CAP ON CONNECTOR SIDE)


SEL=0: CHOOSE SMC

PORT 3

D+

USB/SMC DEBUG MUX

D+GND

D-

VDD

PORT 2

D+D-VDD

VDDD-D+GND

GND

VDDD-

PORT 0

GND


SEL=1: CHOOSE USB


PORT 1

46 OF 110

051-7845

A.0.0


1

6

5

4

3

2

J4620

1

6

5

4

3

2

J4630

1

6

5

4

3

2

J4610

1

6

5

4

3

2

J4600

1

2

9

108

5

4

3

7

6

U4650 4 3

21

L4631

4 3

21

L4621

4 3

21

L4611

4 3

21

L4601

2

1 C4600

2

1 C4610

2

1 C4620

2

1 C4606

2

1 C4621

21

L4630

6

32 45

1

D4630

2

1 C4630

2

1 C46319

6

7

5

8

2

1

4

3

U4601

2

1 C4611

2

1 C4603

2

1 C4601

2

1 C4605

2

1R4600

2

1

3Q4600

2

1 C4602

9

6

7

5

8

2

1

4

3

U4600

21

R4652

21

R4651

2

1 C4650

6

32 45

1

D4600

6

32 45

1

D4610

6

32 45

1

D4620

21

L4600

21

L4610

21

L4620

K22CRITICALC4606150UF, TANY-POLY BULK CAP1128S0225

K23CRITICALC4602330UF, TANT-POLY BULK CAP1128S0238

OMIT

OMIT

6.3V

330UF

CRITICAL

20%

CASE-D3L-SM1POLY-TANT

0.1UF

USB_EXTD_OC_L

USB_EXTC_OC_L

=PP5V_S3_USB

USB_D_MUXED_P

USB_D_MUXED_N

MIN_LINE_WIDTH=0.6MMVOLTAGE=5VPP5V_USB2_PORT2



PP5V_USB2_PORT3


=PP3V3_S5_SMCUSBMUX

USB_EXTC_P

PP5V_USB2_PORT0

MIN_LINE_WIDTH=0.6MMVOLTAGE=5VMIN_NECK_WIDTH=0.2MM

USB_EXTC_N

USB_EXTB_N

USB_EXTB_P

USB_EXTA_N

USB_EXTA_P

PM_EN_USB_PWR

USB_EXTA_OC_L

USB_EXTB_OC_LPP5V_USB2_PORT1

MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=5V

USB_EXTD_P

USB_DEBUGPRT_EN_L

=PP5V_S3_USB

SMC_TX_LSMC_RX_L

USB_PWR_ENA_L

USB_EXTD_N

USB_PORT0_P

USB_PORT0_N

PP5V_USB2_PORT0_FVOLTAGE=5VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

USB_PORT1_P

USB_PORT1_N

PP5V_USB2_PORT1_F

MIN_LINE_WIDTH=0.6MMVOLTAGE=5V


USB_PORT3_P

USB_PORT3_N

PP5V_USB2_PORT3_F

MIN_LINE_WIDTH=0.6MMVOLTAGE=5VMIN_NECK_WIDTH=0.2MM

USB_PORT2_P

USB_PORT2_N

VOLTAGE=5VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

PP5V_USB2_PORT2_F

EXTERNAL USB CONNECTORSSYNC_DATE=N/ASYNC_MASTER=MASTER

SLP1210N6RCLAMP0502N

CRITICAL

SLP1210N6

CRITICAL

RCLAMP0502N

RCLAMP0502NSLP1210N6

CRITICAL

SM

CRITICAL

FERR-250-OHM

USB-K22

CRITICAL

F-ANG-TH

CRITICAL

USB-K22F-ANG-TH

USB-K22

CRITICAL

F-ANG-TH1

CRITICAL

USB-K22F-ANG-TH1

CRITICAL

PI3USB102ZLE

MOJOMUX

TQFN

CRITICAL

DLP0NS120-OHM-90MA

DLP0NS120-OHM-90MA

CRITICAL

CRITICAL

DLP0NS120-OHM-90MA

DLP0NS120-OHM-90MA

CRITICAL

0.01uF

CERM402

16V20%

402CERM16V20%

0.01uF

20%0.01uF

16VCERM402

6.3V

CRITICAL

CASE-D2-SMPOLY-TANT

20%150UF

0.1UF20%

402

10VCERM

SM

FERR-250-OHM

CRITICAL

SLP1210N6RCLAMP0502N

CRITICAL

402

16VCERM

20%0.01uF

0.1UF20%10V

402CERM

CRITICAL

TPS2060

MSOP

402CERM

20%10V

0.1UF

CERM

0.1UF20%

402

10V

10V

402

0.1UF

CERM

20%

5%

MF-LF1/16W

402

10K

SOT23-HF12N7002

MSOP

TPS2060

CRITICAL

PRODUCTION

0

MF-LF

5%

402

1/16W

PRODUCTION

1/16WMF-LF

5%

0

402

402CERM

20%0.1UF10V

CRITICAL

SM

FERR-250-OHM

FERR-250-OHM

SM

CRITICAL

CERM402

20%10V

9

20 9

46 6

103

103

6

103 20

103 20

103 20

103 20

103 20

103 20

70

20

20

103 20

50 49

46 6

51 50 49

51 50 49

103 20

103

103

103

103

103

103

103

103

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

D

SG

D

SG




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

IR RECEIVER CONNECTOR

518S0668

PLACE C4700, C4701 & L4700NEAR J4700 PINS 4 AND 5 IN THE

CAMERA CONNECTOR & FILTER

BOTH SIDES OF THE PIN.ORDER LISTED, AND NOT ON

LAYOUT NOTE:

518S0688

K37L (BLUETOOTH) CONNECTOR

SD Card Reader Board Connector

518S0690

47 OF 110

051-7845

A.0.0


6

5

4

3

2

1

8

7

J4750

5

4

3

2

1

7

6

J4720

45

3Q4700

12

6Q4700

4 3

21

L4720

21

L4721

2

1C475021

L4751

4 3

21

L4750

4

3

2

1

6

5

J4780

5

4

3

2

1

7

6

J4700

4 3

21

L4702

21

L4703

4 3

21

L4701

2

1 C4720

2

1 C4721

2

1 C4781

2

1 C4700

2

1C4701

21

L4700

USB_IR_P

USB_IR_L_N

USB_IR_L_P

USB_BT_N

=PP3V3_S3_BT

=PP5V_S3_IR


PP5V_S3_IR

USB_CAMERA_N

USB_CAMERA_P


PP5V_S3_CAMERA


USB_CAMERA_L_PUSB_CAMERA_L_N

=PP5V_S3_CAMERA

USB_SDCARD_N

=PP3V3_S3_SDCARDUSB_SDCARD_P

USB_IR_N

CARDREADER_RESET

CARDREADER_PLT_RST_L

CARDREADER_PLT_RST

USB_BT_L_NUSB_BT_L_P

PP3V3_S3_BTVOLTAGE=3.3VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM

USB_BT_P

PP3V3_S3_SDCARDVOLTAGE=3.3VMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MM

USB_SDCARD_L_PUSB_SDCARD_L_N

CARDREADER_RESET_L

SYNC_MASTER=MASTER SYNC_DATE=MASTER

Internal USB Connections

53261-8606M-RT-SM

CRITICAL

CRITICAL

M-RT-SM53261-8605

SSM6N15FEAPESOT563

SSM6N15FEAPESOT563

120-OHM-90MA

CRITICAL

DLP0NS

SM

CRITICAL

FERR-250-OHM

10%1UF6.3VCERM402

SM

FERR-250-OHM

CRITICAL

120-OHM-90MADLP0NS

CRITICAL 53261-8604M-RT-SM

CRITICAL

M-RT-SM53780-8605

CRITICAL

CRITICAL

DLP0NS120-OHM-90MA

SM

CRITICAL

FERR-250-OHM

DLP0NS120-OHM-90MA

CRITICAL

10UF

CERM6.3V

805-1

20%

402CERM10V20%0.1UF

10%6.3VCERM

1UF

402

805-1

20%6.3V

10UF

CERM0.1UF

20%10V

402CERM

FERR-250-OHM

CRITICAL

SM

103 20

110 103

110 103

103 20

6

6

103 20

103 20

110 103

110 103

6

103 20

6

103 20

103 20

17

9

110 103

110 103 103 20

110 103

110 103




36

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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

48 OF 110

051-7845

A.0.0



BLANK PAGE

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI

OUT

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

IN

IN

OUT

ININ

BI

BI

OUT

IN

OUT

OUT

NC

OUT

OUT

OUTNC

NCNCNC

NC

NC

NC

NCNC

NCNCNC

NC

NC

NC

NC

NC

NCNC

NCNC

NC

NCNC

IN

OUT

OUT

OUT

OUT

P13P14P15P16 P66

P10P11

P12

P17

P20P21P22P23P24

P25P26P27

P30P31P32

P33P34

P36

P37

P40

P41P42P43P44

P45P46P47

P50P51P52

P60P61

P62P63P64P65

P67

P70P71P72P73P74

P75P76P77

P80P81

P84P85P86

P90P91

P92P93P94P95

P96P97

P35

P83

P82

(1 OF 3)

PA5PA4

PA0PA1

PA2PA3

PA6PA7

PB0PB1PB2PB3

PB4PB5PB6PB7

PC0PC1

PC2PC3PC4PC5

PC6PC7

PD0PD1PD2PD3

PD4PD5PD6PD7

PE0PE1

PE2PE3PE4PF0

PF1PF2

PF3PF4PF5PF6

PF7

PG0

PG1PG2PG3PG4

PG5PG6PG7

PH0PH1PH2

PH3PH4PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2MD1

ETRST

AVSS

AVREFAVCC

EXTALXTAL

(3 OF 3)

BI

BI

BI

BI

IN

IN

IN

OUT

BI

IN

IN

IN

IN

BI

BI

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

(OC)

(OC)

(OC)

(OC)(OC)

(OC)(OC)

(OC)

(DEBUG_SW_1)(DEBUG_SW_2)

(OC)

(OC)

(OC)

(OC)

(OC)

(OC)

If SMS interrupt is not used, pull up to SMC rail.

(OC)(OC)

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NOTE: P94 and P95 are shorted, P95 could be spare.

pins designed as outputs can be left floating,

49 OF 110

051-7845

A.0.0


A3

C5

B11

F10

L3D2

E1

H10

M1B1

D3

E3

E5

H1

D1

A2

H3

L9

L11

M12

U4900

C4

B3A4J2F2E2

L6

M7N6K6K7K8

N7M8

M4L4N4M5

L5M6N5

K5K4J1

K2J3K1

L7K9

N8M9L8K10

N9M10

J13H11G12G10

H13F12G13G11

A11C11

B10C10A10B9C9

B8

L2K3L1N2M2

M3N1N3

U4900

F1

F4G4H4G1

H2G3J4

C6B5A6

D5C7B6A7

L12N13

M13N12N11L10

M11N10

H12J11J10K13

J12K11K12L13

E4F3G2

C3C1

B2C2A1B4

A5D4

D6D7D8A8

B7C8D9A9

E10F13

E12E13F11D12

E11D13

D10C12C13D11

B13A12A13B12

U4900

2

1R4998

2

1R4903

2

1R4902

2

1R4901

2

1R4909

2 1

XW4900

21

R4999

2

1C49202

1C4907

2

1 C4906

2

1 C4905

2

1 C4904

2

1 C4903

2

1C4902

GND_SMC_AVSS

PM_CLKRUN_LLPC_PWRDWN_L

SMC_LRESET_L

SMB_0_S0_DATAPM_CLK32K_SUSCLKPM_SLP_S5_L

PM_SLP_S4_SMC_L

SMC_RX_LSMC_TX_L

SMC_WAKE_SCI_L

SMC_GPU_VSENSE

SMC_CPU_VSENSESMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMB_0_S0_CLK

SMC_RX_LSMC_TX_L

SMC_SYS_KBDLEDSMC_GFX_THROTTLE_L

SMS_ONOFF_LSMB_MGMT_DATA

LPC_SERIRQLPC_CLK33M_SMC

LPC_FRAME_LLPC_AD<3>LPC_AD<2>LPC_AD<1>

LPC_AD<0>

SMC_P26

SMC_P24

ESTARLDO_EN

PM_PWRBTN_L

ALL_SYS_PWRGD_SMCSMC_RSTGATE_L

SMC_PROCHOT_3_3_LPM_RSMRST_L

RSMRST_PWRGD

ALS_GAINSMC_PH2

SMC_THRMTRIPSMC_PROCHOT

SMB_B_S0_CLKSMB_B_S0_DATASMB_A_S3_CLKSMB_A_S3_DATA

SMB_BSA_CLKSMB_BSA_DATA=SMC_SMS_INT

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_TMSSMC_TDOSMC_TDISMC_TCK

SMC_CASE_OPEN

SMC_NB_DDR_ISENSESMC_NB_CORE_ISENSESMC_ANALOG_ID

SMS_Y_AXISSMS_X_AXIS

SMC_FAN_3_TACHSMC_FAN_2_TACHSMC_FAN_1_TACH

SMC_FAN_0_TACHSMC_FAN_3_CTLSMC_FAN_2_CTLSMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_EXCARD_CPNC_SMC_PB3

SMC_ODD_DETECTSMC_RUNTIME_SCI_L

PM_BATLOW_LSYS_ONEWIRE

PM_SYSRST_LSMC_PA1

MEM_EVENT_L

SMC_PA5

USB_DEBUGPRT_EN_L

SMC_PM_G2_EN

PM_EN_PVCORE_CPU

VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC


PP3V3_S5_AVREF_SMC

SMC_TRST_L

SMC_KBC_MDE

SMC_VCL

SMC_NMISMC_EXTAL

SMC_PA0

SMC_P41

SMC_EXCARD_PWR_EN

SMC_ADAPTER_EN

SMC_RESET_L

SMC_XTAL

SMC_MD1

=PP3V3_S5_SMC

SMC_PBUS_VSENSE

SMC_NB_MISC_ISENSESMC_BATT_ISENSE

SMC_DCIN_ISENSE

SMC_GPU_ISENSE

SMC_BC_ACOK

SMB_MGMT_CLK

SMC_ONOFF_L

PM_SLPS3_BUF2_LSMC_BS_ALRT_L

ALS_RIGHT

ALS_LEFT

SMS_Z_AXIS


SMC

50

52

52

103 9

50

70 50

70 50 9 6

52

50

103 9

9

103 51 19

103 51 19

103 51 19

103 51 19

103 51 19

LGA-HF

OMIT

H8S2117

LGA-HF

OMIT

H8S2117

LGA-HFH8S2117

OMIT

50

50

50

50

50

50 21

50

50

51 19

21

51

28

55 32 31 21

51 19

50 50

51 50 49 46

51 50 49 46

50

50

50

50

52

52

52

52

52

52

50

51 50

51 50

51 50

50

51 50

50

50

50

50

50

50

50

56

56

57

50

50

57

56

56

50 45

21

55

110 45

21

50

50 46

10K

MF-LF

5%1/16W

402

NO STUFF

0

MF-LF

5%1/16W

402

1/16W5%

MF-LF

10K

402

MF-LF

10K5%1/16W

402

51

51

10K

MF-LF

5%1/16W

402

52

50

51 50 49 46

51 50 49 46

50

50

50

50

50

50

108 53

108 53

108 53

108 53

20%

CERM

0.1UF

402

10V

50

70

70

21

20%

CERM

0.1UF

402

10V

71

21

SM

20%

CERM

0.1UF

402

10V

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

4.7

1/16W5%

MF-LF402

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

402

20%

CERM

0.1UF10V

20%

CERM10V

402

0.1UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

6.3V

0.47UF

CERM-X5R402

10%

50

51 50

51 19

22UF20%6.3V

CERM-X5R805-3

54 53 50

50

50

50

50

50

50

50

50

50

50

50 6

G

D

S

IN OUT

GND

OUT

IN

BI

OUT

G

D

S

OUT

IN

IN G

D

S

G

D

S

CD

GNDNC

OUTIN

OUT




36

BRANCH

REVISION

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

UNUSED TP/NC ALIASES

PULL-UP ON PAGE 14

ANALOG SENSORS

MISC. SIGNAL ALIASES

518S0665

SMC Crystal Circuit

SMC AVREF Supply

FROM MXM

NC

FROM SMC

TO SMC

TO CPU

FROM SMC

SMC & MXM THERMTRIP LEVEL SHIFTING

UNUSED TP/NC ALIASES - PORT D - INTERNAL PULLUPS

FOR <RDAR://PROBLEM/5925345>

SMC Reset Button / Brownout Detect

POWER BUTTON

SMC PROCHOT 3.3V LEVEL SHIFTING

50 OF 110

051-7845

A.0.0


43

21

S5010

43

21

S5000

2

1

4

3

J5010

2

1R5050

1

4 2

3

5

U5000

2

1R5068

21

R5020

21

R5019

2

1R5069

4

5

3

Q5096

1

2

6

Q5096

21R5099

21

R5018

1

2

6

Q5095

21R509821R504921R504721R509721R5095

21R5093

21R5092

21R5089

21R5096

21R5091

21R5090

2

1R5078

2

1R5070

4

3

5Q5077

21

R5071

1

6

2Q5077

21R5043

21

R5010

2

1 C501021R5094

2

1Y5020

21R5046

21R504221R504121R504021R503921R503821R503721R503621R503521R503421R503321R5032

21

3

VR5065

2

1C5066

2

1 C5067

2

1 C5065

4

5

3

Q5095

21

C5021

21

C5020

2

1C5001

2

1R5000

2

1C5000

POWER_BUTTON_L

SMC_MANUAL_RST_L SMC_SYS_LED TP_SMC_SYS_LEDMAKE_BASE=TRUE

TP_SMC_P41MAKE_BASE=TRUE

PM_THRMTRIP_L

SMC_ONOFF_L

SMC_ANALOG_IDNO_TEST=TRUE

NC_SMC_ANALOG_IDMAKE_BASE=TRUE

ESTARLDO_ENMAKE_BASE=TRUETP_ESTARLDO_EN

SMC_P41

SMC_P26 TP_SMC_P26MAKE_BASE=TRUE

SMC_P24 TP_SMC_P24MAKE_BASE=TRUE

SMS_ONOFF_LMAKE_BASE=TRUETP_SMS_ONOFF_L

SMC_RSTGATE_LMAKE_BASE=TRUETP_SMC_RSTGATE_L

SMC_EXCARD_PWR_EN

SMC_PM_G2_EN TP_SMC_PM_G2_ENMAKE_BASE=TRUE

SMC_SYS_KBDLED TP_SMC_SYS_KBDLEDMAKE_BASE=TRUE

ALS_GAINMAKE_BASE=TRUENC_ALS_GAIN

NO_TEST=TRUE

SMC_NB_MISC_ISENSE

SMC_NB_CORE_ISENSE SMC_MCP_CORE_ISENSEMAKE_BASE=TRUE

SMC_BATT_ISENSE

SMS_X_AXISMAKE_BASE=TRUESMC_1V5_S0_VSENSE

SMS_Y_AXIS SMC_MCP_CORE_VSENSEMAKE_BASE=TRUE

SMC_NB_DDR_ISENSEMAKE_BASE=TRUESMC_1V5_S0_ISENSE

SMC_PBUS_VSENSEMAKE_BASE=TRUESMC_CPU_INPUT_VSENSE

SMC_DCIN_ISENSEMAKE_BASE=TRUESMC_CPU_INPUT_ISENSE

MAKE_BASE=TRUESMC_UNUSED_ADC_PORT7

MXM_PWR_LEVELMAKE_BASE=TRUE

CPU_PROCHOT_BUF

SMC_BC_ACOKSMC_FAN_3_TACH

SMC_ADAPTER_EN

MAKE_BASE=TRUESMC_SMS_INT

MXM_OVERT_L

=PP3V3_S0_SMC_LS

SMC_MCP_SAFE_MODE

=PP5V_S5_AVREF

SMC_XTAL

PP3V3_S5_AVREF_SMC



SMC_EXTAL

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSS

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

SMC_ONOFF_LSMC_LIDSMC_PH2

SMC_TX_LSMC_RX_LSYS_ONEWIRESMC_BS_ALRT_L

SMC_TDOSMC_TDISMC_TCKSMC_EXCARD_OC_L

SMC_PA0SMC_PA1SMC_BIL_BUTTON_LSMC_FAN_3_CTL

=PP3V3_S0_SMC

SMC_GFX_OVERTEMP_L

MXM_THRMTRIP_L

SMC_THRMTRIPMXM_THRMTRIP

=PPVTT_S0_CPU

SMC_PROCHOT_3_3_L

CPU_PROCHOT_L_R

SMC_PROCHOT

=PP3V3_S5_SMC

SMC_TMS

NO_TEST=TRUEMAKE_BASE=TRUENC_SMS_Z_AXIS

NO_TEST=TRUENC_ALS_RIGHT

MAKE_BASE=TRUE

NO_TEST=TRUENC_ALS_LEFT

MAKE_BASE=TRUEALS_LEFT

SMC_GFX_OVERTEMP_L

SMC_PA5

SMS_Z_AXIS

ALS_RIGHT

MAKE_BASE=TRUESMC_IG_THROTTLE_L

SMC_GFX_THROTTLE_L

CPU_PROCHOT_L

MCP_SPKR

MXM_ALERT_LMAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_RESET_L

TP_SMC_EXCARD_PWR_ENMAKE_BASE=TRUE

USB_DEBUGPRT_EN_L

=SMC_SMS_INT

=PP3V3_S0_SMC_LS

PM_SLP_S5_L

PM_SLPS3_BUF2_LSMC_CASE_OPEN

PM_SLP_S4_SMC_L MAKE_BASE=TRUE

SMC SupportSYNC_DATE=N/ASYNC_MASTER=MASTER

Intersil ISL60002-33353S1278 ALL353S1381

10%

CERM

0.01UF16V

402

22PF

CERM50V

402

5%

CERM50V

22PF

5%

402

50 49

SILK_PART=SYS POWER

NTC020-CC1J-B260T

DEVELOPMENT

SM

NTC020-CC1J-B260T

SILK_PART=SMC RESET

DEVELOPMENT

SM

CRITICAL

SILK_PART=PWR BTN

M-RT-SM53261-8602

5%10K

1/16WMF-LF402

CRITICAL

SOT23-5-HFNCP303LSN

MF-LF1/16W5%10K

402

MXM

IG

51

MF-LF

5%1/16W

402

MF-LF

0

1/16W

402

5%

1/16WMF-LF402

5%3.3K

MXM

2N7002DW-X-GSOT-363

MXM

2N7002DW-X-GSOT-363

MXM

5% 40210K

1/16W MF-LF

MF-LF

5%

0

1/16W

402

MXM

85

49

100 14 11

SOT-3632N7002DW-X-G

4025%10K

1/16W MF-LF

5% MF-LF10K

4021/16W

MF-LF 4021/16W5%10K MF-LF1/16W 4025%100K100K

4025% MF-LF1/16W

5% 40210K

1/16W MF-LF

MF-LF 4025% 1/16W10K

5% 1/16W 402MF-LF100K

PLACEMENT_NOTE=PLACE CLOSE TO U4900(SMC)

10K4025% 1/16W MF-LF

1/16WMF-LF402

1K5%

402MF-LF1/16W5%10K

10K1/16W5% MF-LF 402

49

100 14 11

MF-LF1/16W

402

5%470

1/16WMF-LF402

5%3.3K

MMDT3904-X-GSOT-363-LF

MF-LF1/16W5%

402

3.3K

SOT-363-LFMMDT3904-X-G

402NO STUFF 10K

5% 1/16W MF-LF

1K

402

1/16WMF-LF

5%

402CERM

20%10V

0.1UF

49

51 49

1/16W MF-LF 402100K

5%

20.000M

CRITICAL

SM-4

MF-LF 40210K

1/16W5%

5%10K

MF-LF 4021/16W

5% MF-LF 4021/16W10K 1/16W5% MF-LF 40210K MF-LF1/16W10K

4025%

402MF-LF1/16W5%100K

2.0KMF-LF1/16W5% 402

100K402MF-LF5% 1/16W

MF-LF5% 40210K

1/16W

MF-LF10K

5% 1/16W 402

402MF-LF1/16W5%100K 1/16W10K

402MF-LF5%

SOT23-3REF3133

CRITICAL

6.3V

603

10uF20%

X5R

0.01UF10%

CERM402

16V

10%6.3VCERM-X5R402

0.47UF

2N7002DW-X-GSOT-363

CERM

0.1uF20%10V

402

49

49

49

49

49

49

49

49

49

49

49

49

49

49 108 54

49

49 108 54

49 108 54

49 108 54

49 53

49 53

85

49

49

49 21

55 50 6

49

6

49

49

49

54 53 49

50 49

49

49

51 49 46

51 49 46

49

49

51 49

51 49

51 49

49 45

49

49

49

49

54 53 6

50 49

71 55 10 6

50 49 6

51 49

49

50 49

49

49

49

21

49

21

85

50 49 6

49 46

49

55 50 6

49

70 49 9 6

49

70 49

IN

BI

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

BI

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

INOUT

INOUT

OUTIN

OUT

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL




36

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C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

516S0573

FRANK CONNECTOR

LPC+SPI Connector

SPI Bus Series Resistance Option

Alternate SPI ROM Support

Pull-up on debug card

51 OF 110

051-7845

A.0.0


9

87

65

4

3433

3231

30

3

29

2827

2625

2423

2221

20

2

19

1817

1615

1413

1211

10

1

J5100

21

R5145

2

1 C5144

21

R5146

2

1R5144

5

6

2

1

3 4

U51002

1R5140

21

R5158

21

R5157

21

R5156

=SPI_CS1_R_L_USE_MLB

SPI_CS0_R_L

SPI_MLB_CS_L

=PP3V3_S5_ROM

SPI_CS0_LSPI_ALT_CS_L

MAKE_BASE=TRUESPIROM_USE_MLB

PM_CLKRUN_LLPC_FRAME_L

LPC_AD<1>LPC_AD<2>LPC_AD<3>

SPI_ALT_CLKSPI_ALT_CS_LLPC_SERIRQLPC_PWRDWN_LSMC_TDISMC_TCK

LPCPLUS_GPIO

SPI_ALT_CLK

SMC_TX_LSMC_MD1SMC_TRST_LSMC_TDODEBUG_RESET_LSMC_TMS

SPI_ALT_MISOSPI_ALT_MOSI

LPC_AD<0>

SMC_RX_LSMC_NMISMC_RESET_L

SPIROM_USE_MLB

LPC_CLK33M_LPCPLUS=PP5V_S0_LPCPLUS=PP3V3_S5_LPCPLUS

SPI_MISO

SPI_MOSI_R

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_CLK_R

=PP3V3_S5_LPCPLUS


LPC+SPI Debug Connector

PRODUCTION

5%MF-LF

0

4021/16W PLACEMENT_NOTE=PLACE NEXT TO U5100

402MF-LF1/16W

5%20K

NC7SB3157P6XGSC70

CRITICAL

PATH=I96

LPCPLUS

61

51

MF-LF402

5%1/16W

100K

51

PLACEMENT_NOTE=Place next to R6105

402

1/16W5%

MF-LF

0

LPCPLUS

103 61 21

51

PLACEMENT_NOTE=Place next to R6152

402

0

MF-LF

5%1/16W

LPCPLUS

103 61 21

51

LPCPLUS

402

PLACEMENT_NOTE=Place next to R6150 5%

MF-LF

0

1/16W

103 61 21

103 9

103 49 19

103 49 19

51

51

51

49 19

49 19

50 49

50 49

50 49

49

50 49 46

18

55909-0374

CRITICALLPCPLUS

M-ST-SM

103 49 19

51

103 49 19

103 49 19

51

49 19

50 49

9

49

50 49

49

50 49 46

21

103 21

PLACEMENT_NOTE=Place near U1400

LPCPLUS

402

5%1/16WMF-LF

0

0.1UF

CERM10V20%

402

61 6

103

51

6

51 6

51 6

51 6




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

Also reserve 0x56 and 0x32 per spec

CPU - PECI DTS

DIODE2: CPU

UNUSED SMC "BATTERY A" SMBUS CONNECTIONS

(WRITE: 0X54 READ: 0X55)

321

4

65

DIODEEMC1047-2 HEX DIODE SENSOR

(MASTER)

MCP HEATSINK

CPU HEATSINKAMBIENT TEMP

ODD TEMPLCD TEMP

MXM HEATSINK

FUNCTION

SMCU4900

INA219: ACDC THRU J600(WRITE: 0X80, READ: 0X81))

OUTPUT VOLTAGE, CURRENT, POWER

AC/DC PS POWER

3 SENSE POINTS - PRIMARY, SECONDARY, AMB

(WRITE: 0X98 OR 0X9A, READ: 0X99 OR 0X9B)

EMC1403-[1,2]: ACDC THRU J600AC/DC PS TEMPS

REMOTE TEMPSEMC1047-2, U5500, SEE TABLE(WRITE: 0X90 READ: 0X91)


MCP79 SMBUS "1" CONNECTIONS

(WRITE: 0X9A READ: 0X9B)

MAX6618 - U5570

SMC "0" SMBus Connections

SMBUS 0 ALSO GOES TO THE XDP CONNECTOR

SMC

GPU ON CARD - J8400

EMC1403-2: U5535

DIODE1: MCP

DIE TEMPSSO-DIMM "B"

MXM CARD (WRITE: 0X98 READ: 0X99)

SMC "MANAGEMENT" SMBUS CONNECTIONS

U4900

NOTE: SMC RMT BUS REMAINS POWERED AND MAY BE ACTIVE IN S3 STATE

MARGINGING CONTROL

(MASTER)U4900

(MASTER)

U2900

U2901

(Write: 0x98 Read: 0x99)

VREF DAC


MCP79 SMBUS "0" CONNECTIONS

J9800MIKEYMCP79

U1400(MASTER)

(WRITE: 0XA2 READ: 0XA3)J3200

SO-DIMM "A"J3100

MCP79U1400

(MASTER) (MASTER)

SMCU4900

SMC "A" SMBus Connections

U4900

(Write: 0xA0 Read: 0xA1) (MASTER)

MXM TEMP

NV INSIDE (WRITE: 0X9E READ: 0X9F)

SMC

SMC

SMC "B" SMBus Connections

52 OF 110

051-7845

A.0.0


2

1R5202

2

1R5203

2

1R5250

2

1R5251

2

1R5270

2

1R5271

2

1R5260

2

1R5261

2

1R5290

2

1R5291

2

1R5281

2

1R5280

2

1R5201

2

1R5200

MAKE_BASE=TRUESMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL

=SMB_MXM_THRM_SDA

SMB_B_S0_DATA

SMB_B_S0_CLK

=SMB_ACDC_SDA

=SMB_ACDC_SCL

=SMB_REMOTE_TEMP_SDA

=SMB_REMOTE_TEMP_SCL

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS

=SMB_CPU_PECI_SCL

=SMB_CPU_PECI_SDA

=SMB_MXM_THRM_SCL

=PP3V3_S0_SMBUS_SMC_MGMT

SMB_0_S0_CLK

=I2C_AUDIO_SDA

=I2C_AUDIO_SCLSMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMB_BSA_CLK

MAKE_BASE=TRUESMBUS_MCP_1_DATAMAKE_BASE=TRUESMBUS_MCP_1_CLK

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

SMB_MGMT_DATA

SMB_MGMT_CLK

=I2C_VREFDACS_SDA

=I2C_VREFDACS_SCL

SMB_BSA_DATAMAKE_BASE=TRUESMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCLMAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDAMAKE_BASE=TRUE

=PP3V3_S5_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUESMBUS_MCP_0_DATAMAKE_BASE=TRUESMBUS_MCP_0_CLK

=I2C_SODIMMB_SDA

=I2C_SODIMMB_SCL

=PP3V3_S0_SMBUS

=SMB_MCP_CPU_THRM_SDA

=PP3V3_S3_SMBUS_SMC_A_S3

MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

SMB_A_S3_CLK

SMB_A_S3_DATASMB_0_S0_DATA

=SMB_MCP_CPU_THRM_SCL

SMBUS_SMC_0_S0_SCLMAKE_BASE=TRUE

MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA


SMBUS CONNECTIONS

1/16WMF-LF

5%2.2K

402

1/16WMF-LF

5%2.2K

402

402

5%4.7K

MF-LF1/16W

402

5%

MF-LF1/16W

4.7K

402

5%

MF-LF1/16W

100K

MF-LF

5%1/16W

100K

402

MF-LF1/16W

5%

402

2.2K

1/16W5%

MF-LF402

2.2K

4.7K

MF-LF1/16W

402

5%4.7K5%1/16W

402MF-LF

402

5%1/16WMF-LF

100K

MF-LF

5%

402

1/16W

100K

5%4.7K

1/16W

402MF-LF

402

1/16W5%

4.7K

MF-LF

106

106

85

49

49

6

6

55

55

6

52 6

55

55

85

6

49

68

68 106

49

21

21

29

29

49

49

29

29

49 106

106

106

6

6

106 21 13

106 21 13

32

32

52 6

55

6

106

106

31

31

49

49 49

55

106

106

RS_P

RS_M

OUTGND

VCC

IN

OUT

IN

V+

REFIN+

IN- OUT

GND

OUT






36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM



TABLE_5_ITEM

CPU CURRENT SENSE AMP & FILTER

CPU Voltage Sense / Filter

CPU CORE INPUT SIDE CURRENT & VOLTAGE SENSE

PCB: PLACE R5364, C5362 WITHIN 1" OF SMC (U4900)

AMPLIFIED AND FILTERED ISNS TO SMC

Place RC close to SMC MXM PWRSRC (GPU CORE & MEM) CURRENT SENSE

GAIN = 20353S2291

K51 SET FOR APPROX 1.98V AT 5.5A ON PWRSRC

COUNT.0087518 A/COUNT2.778 A/V2 A/V

4 V/V

MXM PWRSRC VOLTAGE SENSE

.0129 V/COUNTCOUNT

0 TO 3.3V

(SCALING 12V INPUT VOLTAGE TO SMC)

PCB: PLACE C5359 WITHIN 1" OF SMC (U4900)

0 TO 3.3V

0 TO 3.3VADC IS 10BIT 0 TO 1023

SCALE

K50 SET FOR APPROX 2V AT 4A ON PWRSRC

COUNT.0064453 A/COUNT

SCALE

ADC IS 10BIT 0 TO 1023

SCALE

ADC IS 10BIT 0 TO 1023

PLACE RC CLOSE TO SMC

53 OF 110

051-7845

A.0.0


2

1R5361

5

2

4

1

3

U5360

2

1R5331

2

1 C5330

2

1R5330

3

1

6

4

5

2

U5320

2

1 C5321

2

1C5320

21

R5321

21

R5360

21

R5363

21

C5360

21

R5364

2

1 C5362

3

4

5

1

2

U5380

2

1 C5381

4321

R5380

2

1 C5380

2

1R5354

2

1R5353

2

1 C5359

2

1 C5309

21

R5309

OMIT

0.22UF

X5R

20%6.3V

402

402

0.22UF6.3V20%

X5R

MXM

1/16WMF-LF402

18.2K1%

MXM

1/16W

6.04K

MF-LF402

1%

0.22UF

X5R6.3V

402

20%

MXM

1%

2512-1

1W

0.025

MF

OMIT

16V10%

CERM-X7R402

MXM

MAX4073TAXK+G65SC70

12 108

49 108

CERM-X5R10%0.22UF6.3V402

5.1K

402

5%1/16WMF-LF

16V20%

0.01UF

CERM402

21K

402

1%1/16WMF-LF

1%

10K

1/16W402

MF-LF

71 108

MF-LF

4.53K

402

402

10V

0.1UF

DEVELOPMENT

CERM

20%

INA210

DEVELOPMENT

CRITICALSC70

402

18.2K1/16W1%

MF-LF

0.22UF6.3VX5R402

20%1/16W1%

402

6.04K

MF-LF

OPA348SC70-5

402MF-LF1/16W1%10K

49 108 4.53K

402MF-LF

1%1/16W

0.22UF

X5R

20%6.3V

402

CPU/MXM CURRENT AND VOLTAGE SENSESYNC_MASTER=MASTER SYNC_DATE=N/A

107S0111 1 18 MILLIOHM R5380 CRITICAL K23_MXM

C5381 MXMCAP,0.082UF,4021

1 C5381 IGRES,10KOHM,5%,402

VR_ISNS_CPU_P

VR_ISNS_CPU_N

SNS_PS_CPU_ISNS

CPU_INPUT_ISENSE_N

CPU_INPUT_ISENSE_P

SMC_CPU_INPUT_VSENSE

=PP3V3_S0_SMC

SMC_CPU_INPUT_ISENSE

PP12V_S0_CPU_FLTRD

GND_SMC_AVSS

GND_SMC_AVSS

VR_CPU_IOUT

SMC_CPU_ISENSE

=PP5V_S0_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

PPV_S0_MXM_PWRSRC

SMC_GPU_VSENSE

GND_SMC_AVSS

CPU_VCC_SENSE

=PPV_S0_MXM_PWR


PPV_S0_MXM_PWRSRC

VOLTAGE=12V



MAKE_BASE=TRUE

MXM_PWRSRC_SENSOR_N

GND_SMC_AVSS

=PP3V3_S0_SMC

SMC_CPU_VSENSE

CRITICAL

CRITICAL

=PPV_S0_MXM_PWRSRC

132S0242

116S0090

SMC_GPU_ISENSE

0.082UF

MXM_PWRSRC_SENSOR_P

OMIT

107S0063 1 R538025 MILLIOHM CRITICAL K22_MXM

SMC_CPU_INPUT_IOUT

1%1/16W

1132S0080 C5321 DEVELOPMENT

C53211116S0004 PRODUCTION

CAP, 0.22UF, 0402

RES, 0-Ohm, 0402

DEVELOPMENT

108

71

71

50

6 50 53 54

50

71 72

49 50 53 54

49 50 53

6

49 50 53 54

49 108

49 50 53 54

53

49 108

49 50 53 54

6

108

53

108

49 50 53 54

84

6 50 53 54

54

V+

REFIN+

IN- OUT

GND

OUTIN



TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM






36

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DR


SHEET

PAGE TITLE

C

A

D

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Apple Inc.

PAGE


A

B

C

345678

D

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8 7 5 4 2 1

Place RC close to SMC

MCP CORE CURRENT SENSE

GAIN = 200V/V

MCP CORE VOLTAGE SENSE

SCALE IS 0.116 V/A

TRANSFER RATIO = 0.4V/A

1.5V S0 VOLTAGE SENSE

1.5V S0 CURRENT SENSE

353S2073

54 OF 110

051-7845

A.0.0


2

1R5405

2

1 C5404

21

R5404

21

R5403

2

1 C5403

2

1 C5402

21

R5402

2

1 C5400

2

1 C5401

4321

R5400

21

R5401

3

1

6

4

5

2

U5400

402X5R6.3V20%0.22UF

1%1/16W

402MF-LF

4.53K

6.3VX5R402

0.22UF20%

1%

4.53K

402

1/16WMF-LF

RES, 0 OHM, 0402

CAP, 0.22UF, 0402

1/16W

6.3V

402

OMIT

C5401

C5401

116S0004

132S0080

20%0.22UF

X5R

MCP_PWR_SENSE

1 PRODUCTION

RES,0 OHM,1206,20MILLIOHM MAX101S0414 PRODUCTIONR54001 CRITICAL

RES,2 MILLIOHM,1206104S0018 MCP_PWR_SENSER5400 CRITICAL1

1/4W

0.002

=PP3V3_S0_SMC

SMC_1V5_S0_ISENSE_R SMC_1V5_S0_ISENSE

PP1V5_S0

MCPCORES0_IMON

SENSE_1V5_S0_N

SENSE_1V5_S0_P

PP1V5_S0

PPMCPCORE_S0_REG SMC_MCP_CORE_VSENSE

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

GND_SMC_AVSS

SMC_1V5_S0_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

PP1V5_S0_FET


MCP CURRENT AND VOLTAGE SENSE

6.3VX5R402

20%0.22UF

1%

4.53K

402

1/16WMF-LF

MCP_PWR_SENSE

402X5R6.3V20%0.22UF

1206

1%

MF-LF

OMIT

1%

4.53K

402MF-LF

MCP_PWR_SENSE

1/16W

402

NOSTUFF

4.53K

MF-LF

1%

108 74 108 50

MCP_PWR_SENSE

SC70INA210

1

53 50 6

108 108 50

54 6

108

108

54 6

74 6 108 50

54 53 50 49

54 53 50 49

108 50

54 53 50 49

54 53 50 49

78

BI

BIDN2/DP3

DP1

DN1

DP2/DN3

SMCLKGND

THERM*

SMDATA

VDD

ALERT*

BI

BI

DP2/DN3

DN2/DP3

DP1/DN6

DN1/DP6

GND

SMDATA

SMCLK

DN4/DP5

DP4/DN5

VDD

BI

BI

AGND

VREF

PECISDA

SCL

AD0

AD2

AD1

GND

VCC

OUT

OUT

GND

V+




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

518S0677

SENSOR CH2 SENSOR CH3

is on csa 70 with power sequencingpower/gnd and ref for this dual part

Must pull high to 2.5V for compatibility with all drives

Cannot pull low because some drives use this bit todetermine 1.5 Gbps vs. 3.0 Gbps SATA

Drive disconnected = pulled highDrive asleep = HDD drives HDD_OOB_TEMP lowDrive active = valid signal protocol

FROM DRIVE:LOW: -0.3V TO 0.5VHIGH: 2.0V TO 3.6V

TO SMC

HDD OUT OF BAND TEMPERATURE SENSING LEVEL SHIFTING

CPU PECI DTS OPTIONS

PLACEMENT NOTE: PLACE U5535 NEAR MCP, TOP SIDE UNDER HEATSINK

PLACE HSK SENSOR CONN. TOP SIDE NEAR MXM OR CPU

518S0678

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

SENSOR CH4

353S2224

SENSOR CH1 SENSOR CH6

MCP & CPU T-Diode Thermal Sensor

SENSOR CH5

REMOTE THERMAL SENSORS

Consider 3rd option - direct to SMC

518S0678

HEATSINKS, AMBIENT, PANEL AND ODD

REMOTE THERMAL SENSORS (HEATSINKS AND ODD)

518S0698

518S0698

518S0698

518S0678

55 OF 110

051-7845

A.0.0


8

1

3

2

4

U7030

2

1

4

3

J5535

2

1

4

3

J5550

2

1R5553

21

R5550

2

1R5554

2

1R5551

21

L5536

21

L5535

2

1C5580

21

R5571

2

1 C5571

2

1C5570

10

6

4

5

1

72

8

9

3

U5570

21

R5570

1

9

10

6

8

4

2

7

5

3

U5500

3

2

1

5

4

J5521

2

1 C5535

21

R5535

2

1

4

3

J5511

21

L5511

21

L5510

21

L5521

21

L5520

2

1

4

3

J5510

21

L5513

21

L5512

21

L5523

21

L5522

2

1

4

3

J5520

21

L5554

21

L5553

2

1

4

3

J5551

21

L5552

2

1C5536

1

7

9

10

6

4

2

5

3 8

U55352

1R5537

2

1R5536

21

R5538

2

1C5501

21

R5500

2

1C5502

2

1C5503

2

1C5504

CRITICAL 0402

10%0.0022UF

CERM50V

402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

0.0022UF10%

402CERM50V

SIGNAL_MODEL=EMPTY

0.0022UF10%50VCERM402

5%

MF-LF1/16W

22

402

10VX5R

402-1

10%1UF

5%

402MF-LF

0

1/16W

MF-LF1/16W

5%100K

402

MCP_CPU_TDIODE

402

1/16W5%

MF-LF

10K

MCP_CPU_TDIODE

52

52

MCP_CPU_TDIODE

EMC1403-2-AIZL

CRITICAL

TSSOP

CERM402

10%50V

0.0022UF

SIGNAL_MODEL=EMPTYMCP_CPU_TDIODE

21 108

21 108

0402

FERR-220-OHM

FERR-220-OHM

0402

FERR-220-OHM

0402

0402

FERR-220-OHM

FERR-220-OHM

0402

FERR-220-OHM

0402

MXM

MXM

FERR-220-OHM

SILK_PART=CPU HSK

53398-8602M-ST-SM

0402

FERR-220-OHM

FERR-220-OHM

0402

FERR-220-OHM

0402

FERR-220-OHM

0402

M-ST-SM

CRITICAL

53398-8602

MXM

SILK_PART=MXM HSK

MCP_CPU_TDIODE

402MF-LF

5%

22

1/16W

10%10VX5R402-1

1UF

MCP_CPU_TDIODE

CRITICAL

53780-8603M-RT-SM

CRITICAL

EMC10472AIZL

TSSOP

11 108 20

MF-LF5%

1/16W402

PECI_MCP

14 108

MAX6618USOP-HF

PECI_SMB

10V20%

0.1UF

402CERM

PECI_SMB PECI_SMB

10V20%0.1UF

402CERM

402MF-LF1/16W5%

20

PECI_SMB

SIGNAL_MODEL=EMPTY

402CERM50V10%

0.0022UF

MCP_CPU_TDIODE

11 108

11 108

0402

FERR-220-OHM

FERR-220-OHM

MF-LF1/16W5%1K

402MF-LF

5%1/16W

62K

402

MF-LF402

5%1/16W

3.3K

MF-LF

5%1/16W

200K

402

CRITICAL

53398-8602

LM393SOI-HF

CRITICAL

Thermal SensorsSYNC_DATE=N/ASYNC_MASTER=MASTER

SNS_AMB_NSNS_AMB_PSNS_LCD_P

SNS_LCD_N

SMC_EXCARD_CPSMC_HDD_OOB_TEMPMAKE_BASE=TRUE

=PP3V3_S0_SMC_LS

HDD_OOB_TEMP_R

12VS5_1V60_REF

HDD_OOB_TEMP

=PP3V3_S0_TSENS

CPU_PECI_MCP

=SMB_CPU_PECI_SDA

HDD_OOB_TEMP_FILT

SNS_ODD_N

SNS_T_DP4_DN5

=SMB_MCP_CPU_THRM_SCL

SNS_MCP_P

=SMB_CPU_PECI_SCL

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0_MCPTHMSNS_RMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mmVOLTAGE=3.3V

SNS_T_DN4_DP5

=SMB_REMOTE_TEMP_SDA


PP3V3_S0_TSENS_R


VOLTAGE=3.3V

SNS_MXM_NSNS_MXM_P

=SMB_REMOTE_TEMP_SCL

=PP3V3_S0_TSENS

DIFFERENTIAL_PAIR=SNS_T1SNS_T_DN1_DP6

SNS_T_DN1_DP6

SNS_T_DP4_DN5

=PPVTT_S0_CPU

MEM_EVENT_L

SNS_T_DN4_DP5DIFFERENTIAL_PAIR=SNS_T3

SNS_T_DP2_DN3

MCPTHMSNS_ALERT_L

SNS_T_DN2_DP3

DIFFERENTIAL_PAIR=SNS_T2SNS_T_DP2_DN3

MCP_THMDIODE_P

=SMB_MCP_CPU_THRM_SDA

MCPTHMSNS_THERM_L

SNS_T_DN1_DP6

SNS_T_DP1_DN6

SNS_T_DP2_DN3

SNS_T_DN2_DP3

SNS_CPU_H_N

SNS_T_DN4_DP5

SNS_CPU_H_P

SNS_ODD_P

SNS_T_DP4_DN5DIFFERENTIAL_PAIR=SNS_T3

SNS_T_DN2_DP3DIFFERENTIAL_PAIR=SNS_T2

DIFFERENTIAL_PAIR=SNS_T1SNS_T_DP1_DN6

=PP3V3_S0_MCPTHMSNS

MCP_THMDIODE_N

SMB_PECI_L

CPU_PECI_L

M-ST-SM

SILK_PART=MCP HSK

SILK_PART=AMBIENT TEMP

SNS_MCP_N

0402

SNS_T_DP1_DN6

SILK_PART=ODD TEMP

M-RT-SM

CRITICAL

53780-8602

CRITICAL

M-RT-SM

SILK_PART=LCD TEMP

53780-8602

SILK_PART=HDD TEMP

53780-8602M-RT-SM

CRITICAL

108 110

108 110 108 110

108 110

49 108

6 50

108

70

6 55

52

108

108 110

55 108

108

108

52

55 108

52

108

108

52

6 55

55 108

55 108

55

55 108

6 10 50 71

21 31 32 49

55 108

55 108

55 108

55 108

55 108

55 108

55 108

55 108

108

55 108

108

108 110

55 108

55 108

55 108

6

108

108

G S

D

G S

D




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PAGE


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C

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D

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8 7 5 4 2 1

FAN 0

518S0592

GNDTACHMOTOR CONTROL

518S0592

GND

TACHMOTOR CONTROL

FAN 1

ODD FAN

NOTE: ADDED TO PROTECT SMC

HD FAN

12V DC

12V DC

56 OF 110

051-7845

A.0.0


2

1 C5605

2

1 C5628

2

1R5630

2

1R5620

21

L5640

21

L5630

21

L5620

21

L5610

21

L5601

21

L5600

2

1 C56082

1 C5609

2

1 C56062

1 C5607

4

3

2

1

6

5

J5600

4

3

2

1

6

5

J5601

2

1 C5602

2

1

3

Q5605

2

1

3

Q5602

21

R5698

21

R5699

2

1R5611

2

1R5610

3

1

D5601

21

R5609

2

1 C5603

2

1R5607

5

4

876321

Q5603

2

1R5606

21

R5605

2

1 C5601

3

1

D5600

2

1R5603

5

4

876321

Q5600

2

1R5602

2

1R5601

2

1R5600




1.5K

F1_VOLTAGE8R5MIN_LINE_WIDTH=0.5MM

402MF-LF1/16W

10K5%

MF-LF5%10K1/16W402

1206MF-LF1/4W

1.5K5%

NTHS5443T1H

CRITICAL

1206A-03-HF

SOT23

5%

402

10K1/16WMF-LF

NTHS5443T1H

CRITICAL

1206A-03-HF

MMBD914XGSOT23

1/4W1206

5%MF-LF

1.5K10K

MF-LF402

5%1/16W

MF-LF

5%

47K

1/16W

402

47K

5%1/16WMF-LF402

2N7002SOT23-HF1

2N7002SOT23-HF1

20%16VELEC6.3X5.5-SM1-HF

100UF

CRITICAL

53780-8604M-RT-SM

M-RT-SM53780-8604

CRITICAL

402

20%CERM16V0.01UF

20%CERM1206-116V4.7UF

16V20%0.01UF

402CERMX5R

603

10%16V2.2UF

0402

CRITICAL

FERR-220-OHM

0402

FERR-220-OHM

CRITICAL

220-OHM-1.4A

CRITICAL

0603

220-OHM-1.4A

0603

CRITICAL

CRITICAL

220-OHM-1.4A

0603

220-OHM-1.4A

0603

CRITICAL

MF-LF1/10W5%0

603

PLACEMENT_NOTE=PLACE R5620 CLOSE TO J5600 Pin3

0

603MF-LF1/10W5%


16V10%2.2UF

603X5R

CRITICAL

20%16VELEC6.3X5.5-SM1-HF

100UF

HD AND OD FANSYNC_MASTER=MASTER SYNC_DATE=N/A

FAN_1_GNDMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM

FAN_0_GND


SMC_FAN_1_CTL

FAN_TACH0

FAN_0_PWR


=PP3V3_S0_FAN

SMC_FAN_1_TACH

SMC_FAN_0_TACH

=PP3V3_S0_FAN

=PP3V3_S0_FAN

=PP3V3_S0_FAN

FAN_TACH1

=PP12V_S0_FAN

SMC_FAN_0_CTL

FAN_TACH0_L


FAN_0_PWR_L

VOLTAGE=12V

MIN_LINE_WIDTH=0.5MMPP12V_S0_FAN0_L


FAN_1_PWR


FAN_TACH1_LFAN_1_PWR_L

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM


MIN_LINE_WIDTH=0.5MMPP12V_S0_FAN1_L

=PP12V_S0_FAN

CRITICAL

MMBD914XG


805

5%1/8W

MF-LF

1.5K

F0_GATESLOWDN

0.47UFX7R10%16V805

8051/8W5%

MF-LF

3.9KF0_VOLTAGE8R5MIN_LINE_WIDTH=0.5MM

805MF-LF

5%1/8W

F1_GATESLOWDN

0.47UF10%

805X7R16V

805

5%1/8WMF-LF

3.9K

110

110

49

6 56 57

49

49

6 56 57

6 56 57

6 56 57

6 56 57

49

110

110

110

110

110

110

6 56 57

G S

D




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A

D

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PAGE


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B

C

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D

B

8 7 5 4 2 1

518S0592

MOTOR CONTROL

FAN 2

CPU FAN

12V DCGNDTACH

57 OF 110

051-7845

A.0.0


4

3

2

1

6

5

J5700

2

1R5720

21

L5720

21

L5710

21

L5701

2

1 C57092

1 C5708

2

1 C57022

1

3

Q5702

21

R5797

2

1R5705

2

1R5704

21

R5703

2

1 C5701

2

1R5701

3

1

D5700

5

4

876321

Q5700

2

1R5700





F2_VOLTAGE8R5

805MF-LF

3.9K

5%1/8W

0.47UF10%16VX7R805

F2_GATESLOWDN

1/8W

805

5%1.5K

MF-LFCRITICAL

FAN_2_PWR

=PP3V3_S0_FAN

SMC_FAN_2_TACH

=PP3V3_S0_FAN

SMC_FAN_2_CTL

FAN_TACH2

=PP12V_S0_FAN

FAN_2_GND


VOLTAGE=12V


PP12V_S0_FAN2_L


FAN_2_PWR_L


FAN_TACH2_L


CPU FAN

47K

5%1/16WMF-LF402

MF-LF

10K

402

5%1/16W 5%

1/4W

1.5K

1206MF-LF

SOT23MMBD914XG

NTHS5443T1H1206A-03-HF

1/16WMF-LF402

5%10K

M-RT-SM53780-8604

CRITICAL

6031/10W5%0

MF-LF


0603

CRITICAL

220-OHM-1.4A

0603

220-OHM-1.4A

CRITICAL

0402

FERR-220-OHM

CRITICAL

402CERM

0.01UF16V20%

4.7UF

1206-1CERM16V20%

100UF20%16VELEC6.3X5.5-SM1-HF

CRITICAL

SOT23-HF12N7002

57 56 6

49

57 56 6

49

56 6

110

110

110

110




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DR


SHEET

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A

D

2 1


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PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

58 OF 110

051-7845

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DR


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PAGE TITLE

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A

D

2 1


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PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

59 OF 110

051-7845

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BLANK PAGE




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A

D

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PAGE


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D

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8 7 5 4 2 1

60 OF 110

051-7845

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SO

VDD

CE*

SCK

VSSHOLD*

SI

WP* OUTIN

IN IN




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8 7 5 4 2 1

0

SPI_CLK

0

1

1

SST25VF016B max speed for READ command is 25MHz.

MCP79 SPI Frequency Select

SPI_MOSI

NOTE: MCP79 only issues ’READ’ (0x03) commands

frequency and part selection. not ’READ_FAST’ (0x0B). Limits SPI bus

0

Frequency

31 MHz

1

1

25 MHz

1 MHz

42 MHz 0

61 OF 110

051-7845

A.0.0


2

1R6191

2

1R6190

21

R615021

R6152

21

R6105

3

4

8

2

56

7

1

U61002

1R6100

2

1R6101

2

1C6100

=PP3V3_S5_ROM

SPI_WP_LSPI_HOLD_L

SPI_CLK SPI_MOSI

SPI_MLB_CS_L

SPI_CLK_R SPI_MOSI_R

SPI_MISO_R SPI_MISO

SYNC_DATE=12/08/2008

SPI ROMSYNC_MASTER=K51

MF-LF

5%1/16W

10K

402

402MF-LF

5%1/16W

10K

402

0

1/16W5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%1/16W

0

402

PLACEMENT_NOTE=PLACE CLOSE TO U6100

MF-LF

5%1/16W

0

402

103 51 21 103 51 21

51 103 51 21

CRITICAL

SST25VF016B

OMIT

SOI

16MBIT

1/16W5%

MF-LF

3.3K

402

1/16W5%3.3K

MF-LF402

10V

0.1UF

CERM

20%

402

51 6

103 103

103

IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

OUT

NR/FB

NC

IN

EN

GND

IN

OUT

IN

IN

OUT

IN

VL_HD

SENSE_A

GPIO1/DMIC_SDA2GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REFVD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYCFLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDISDO

VL_IF

BITCLK

MICIN_R-MICIN_R+

VREF+_ADC

LINEOUT_L2+LINEOUT_L2-LINEOUT_R2+

/SPDIF_OUT2IN




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8 7 5 4 2 1

APPLE P/N 353S24564.5V POWER SUPPLY FOR CODEC

NC

DAC2/3 FSOUTPUTSE= 1.34VRMS

HP OUT ZOBEL NETWORK

DIFF FSINPUT= 2.45VRMSSE FSINPUT= 1.22VRMSDAC1 FSOUTPUT= 1.34VRMSDAC2/3 FSOUTPUTDIFF= 2.67VRMS

NCNC

NC

NC

NC

NC

NC

K22 = NC

APPLE P/N 353S2592

K23 LOW = S/PDIF IN, HIGH = DP SPDIF

AUDIO CODEC

62 OF 110

051-7845

A.0.0


2

1 C6207

2

1 C6202

2

1 C6205

27

1

3

44

41

9

28

29

24

46

25

49

10

4847

13

58

1119

20

1817

16

3233

3637

3130

3534

23

21

22

39

4038

151412

2

45

42

43

4

7

6

26

U6201

2

1C6204

2

1R6295

2

1C6297

2

1C6298

2

1R6297

2

1R6296

21

R6257

2

1R6298

2

1R6299

2

1C6266

1

3

5

6

2

4

VR6201

2

1C6259

2

1C6260

2

1 C6262

2

1 C6263

2

1C6261

21

R6254

2

1R6267

2

1R6263

2

1R6255

2

1C62652

1 C6258

2

1C6264

2

1 C6201

21

R620121

L6201

2

1 C62132

1C6203

2

1C6211

2

1 C6208

2

1C6206

21

XW6201

CRITICAL

CRITICAL

X5R

MIN_LINE_WIDTH=0.30MMCS4206_FP

CS4206_FLYC

2.2UF

AUD_LO1_P_LTP_AUD_LO1_N_L

AUD_LO1_P_R

AUD_LI_COMMAKE_BASE=TRUE

AUD_LI_P_L

CS4206_VCOM

CS4206_FN

TP_AUD_LO1_N_R

AUD_LO2_P_RTP_AUD_LO2_N_R

AUD_CODEC_MICBIAS

TP_AUD_LO2_N_LCS4206_FLYP

AUD_MUX_CNTRL

AUD_SENSE_A

AUD_GPIO_1AUD_GPIO_2AUD_GPIO_3

GND_AUDIO_HP_AMP_LPP4V5_AUDIO_ANALOG

HDA_SDOUTHDA_RST_L

AUD_LO2_P_L

VBIAS_DAC

CS4206_FLYN

AUD_LI_P_R

AUD_MIC_INP_LAUD_MIC_INN_L

HDA_SYNC

TP_AUD_DMIC_CLK

AUD_SDI_R

HDA_BIT_CLK

AUD_MIC_INN_RAUD_MIC_INP_R

CS4206_VREF_ADC

AUD_SPDIF_OUT

VOLTAGE=0VGND_AUDIO_HP_AMP_L

GND_AUDIO_HP_AMP_L

GND_AUDIO_HP_AMP_L


AUD_Z_L

AUD_LI_N_L

=PP3V3_S0_AUDIO

=PP5V_S0_AUDIO

AUD_HP_PORT_RMIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM

HDA_SDIN0AUD_LI_N_R

4V5_NR

AUD_Z_R


AUD_HP_PORT_L


AUD_GPIO_1

=PP1V5_S0_AUD_DIG

MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_L

=PP5V_S0_AUDIO

VOLTAGE=4.5VMIN_NECK_WIDTH=0.10MMMIN_LINE_WIDTH=0.20MM

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

AUD_HP_PORT_REFMIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM AUD_HP_PORT_R

=PP3V3_S0_AUDIO


4V5_REG_IN

VOLTAGE=5V

4V5_REG_EN

=PP3V3_S0_AUDIO

AUD_SPDIF_IN_CODECAUD_SPDIF_CHIP

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0V

GND_AUDIO_CODEC

VOLTAGE=4.5VMIN_LINE_WIDTH=0.20MMMIN_NECK_WIDTH=0.10MM

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

SYNC_DATE=06/01/2009SYNC_MASTER=SKIPAUDIO

AUDIO: CODEC/REGULATOR

402-1

1UF

X5R

10%10V

402-1

1UF

X5R

10%10V

10UF

X5R6.3V20%

603

62

QFNCS4206ACNZC

X5R6.3V20%

10UF

603

1/16W

402

100K1%

MF-LF

9

103 66

63 62

63 62

X7R-CERM

0.1UF16V

402

10%0.1UF

X7R-CERM

10%16V

402

402MF-LF1/16W

5%39

MF-LF

5%39

402

1/16W

402

22

1/16W5%

MF-LF

62

68 67 66 65 64 62 6

EDUCATION

1/16WMF-LF

5%10K

402

MF-LF402

5%100K

BETTER

1/16W

16VX7R-CERM

402

10%0.1UF

SONTPS71745

1UF

402-1

10%10VX5R

68 62 6

68 67 66 65 64 62 6

62

66

62

62

68 67 66 65 64 62 6

68 62 6

16V

10UF20%

CASE-B2-SMPOLY-TANT

CASE-B2-SM

16V20%

POLY-TANT

10UF

CRITICAL

10UF

CASE-B2-SMPOLY-TANT

20%16V

10%10V

402

0.47UF

402

5%

MF-LF

22

1/16W

NOSTUFF

100K5%

402MF-LF1/16W

1/16W

NOSTUFF

MF-LF

05%

402

402MF-LF

2.67K1/16W1%

X5R402

0.47UF10%10V

402

10VX5R

10%0.47UF

0.47UF10%10VX5R402

402-1

1UF

X5R

10%10V

1/16WMF-LF402

1%

2.21K

FERR-220-OHM

0402

63

63

20%

CRITICAL

10UF6.3V

603X5R

67

67

68

68

63

63

67

65

65

64

64

63 62

63 62

68 64

68 65 64

67

103 21

103 21

103 21

103 21

103 21

4.7UF4VX5R402

20%

CRITICAL

10%1UF

TANTCASE-R-HF

20V

402-LF

20%6.3VCERM

6.3V

2.2UF

402-LF

20%

CERM

SM

103

9

66 63 62

103

66 63 62

66 63 62

66 63 62

6

68 67 65 64 63 62

68 67 65 64 63 62

68 67 65 64 63 62

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

1ST ORDER DAC FILTER PLACEHOLDER

NET RIN = 18K OHMSVIN = 2VRMS, CODEC VIN = 1.14 VRMSFC = 5 HZ MaxCODEC Nom SE RIN = 20K OHMS

63 OF 110

051-7845

A.0.0


2

1R6305

2

1 C6304

21

R6306

2

1R6303

2

1 C6301

2

1R6301

21

R6300

21

C6305

21

C6303

21

C6302

21

C6300

21

R6325

2

1C6321

2

1C6320

21

R6324

AUD_HP_R


GND_AUDIO_HP_AMP_L

AUD_HP_PORT_R

AUD_HP_PORT_L AUD_HP_L


GND_AUDIO_CODEC

AUD_LI_L


AUD_LI_N_L

MIN_LINE_WIDTH=.3MMMIN_NECK_WIDTH=.2MM

MIN_NECK_WIDTH=.2MMMIN_LINE_WIDTH=.3MM

AUD_LI_P_LAUD_LI_LF


AUD_LI_GND



AUD_LI_R


AUD_LI_GND



AUD_LI_RF AUD_LI_P_R



AUD_LI_N_R

AUDIO: FILTER/BUFFERSYNC_DATE=06/01/2009SYNC_MASTER=SKIPAUDIO

21.5K1%

1/16WMF-LF

402

10%820PF

402CERM50V

NOSTUFF

MF-LF1/16W

402

7.87K

1%

MF-LF1/16W1%10

402

10%820PF

CERM50V

402

NOSTUFF

21.5K1%

1/16WMF-LF

402

MF-LF1/16W

7.87K

1%

402

10%16VX5R

2.2UF

603

CRITICAL

10%16VX5R603

2.2UF

CRITICAL

10%16VX5R

2.2UF

CRITICAL

603

10%16VX5R603

CRITICAL

2.2UF

66 63

66

68 67 65 64 62

66 63

66

62

62

62

62

66 62

1/10W5%

0

MF-LF603

66

66

62

62

NOSTUFF

5%50V

C0G-CERM

2200PF

CRITICAL

603

NOSTUFFCRITICAL

603

50V5%

C0G-CERM

2200PF

603

5%1/10WMF-LF

0

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

REG

VS

C1P

BOOT

C1N

OUTL1-OUTL1+

OUTL2-

OUTL2+

OUTR1-

OUTR1+

OUTR2-

OUTR2+

NC1NC2NC3

FBL

COM

INL

INRFBR

MONO

SHDN*

MOD

REGENMUTE*

THMPGNDAGND

PVDD

PAD




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

RIN = 17.4 OHMS

TURN ON TIME: 110MSTURN ON DELAY: 150MS

FC = 19.5 HZAMP VOUT = 7.355VRMS

GAIN = -4.8(20K/17.4K)

POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

TWEETER SPEAKER AMPLIFIERMAX9736B APN:353S2042

CODEC OUT = 1.335VRMS

64 OF 110

051-7845

A.0.0


21

R6407

21

R6405

2

1C6499

2

1C6498

2

1R6406

21

C6495

21

C6496

21

R6404

21

R6402

2

1 C6404

21

R6403

21

C6413

2

1 C6405

21

R640121

R6400

21

C64122

1C6403

2

1C6402

16

10

11

15

3027

2928

2624

2523

32

2

31

1

1787

9

4

20

18

6

19

5

33

12

22

21

3

1413

U6400

2

1 C6410

21

L6403

2

1 C6407

2

1C6406

2

1C6401

2

1 C6411

21

L6401

21

L6402

2

1C6408

2

1 C6409

21

L6400

AUD_SPKR_OUTLO1R_NOUT

AUD_SPKR_OUTLO1R_POUT

AUD_SPKR_OUTLO1L_NOUT

AUD_SPKR_OUTLO1L_POUT


PP12V_AUD_SPKRAMP_PLANE


GND_AUDIO_SPKRAMP_PLANE

AUD_L_P1



AUD_LO1_P_R



AUDSAMPCPP1

AUDSAMPCPN1MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.15MM

AUD_L_N10.5MM0.2MM

AUD_R_N1


MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMMAX9736_INT_1REG

AUD_R_P1 0.2MM0.5MM

AUD_MAX9736_1VREG


AUD_MAX9736_1FBLAUD_MAX9736_1INL

AUD_MAX9736_1COM

AUD_MAX9736_1INRAUD_MAX9736_1FBR

AUD_BOOT1


AUD_LO1_P_L


L01_P_L


=PP3V3_S0_AUDIO

=PP3V3_S0_AUDIO AUD_SPKRAMP_1SHDN_L

GND_AUDIO_SPKRAMP_PLANEMIN_LINE_WIDTH=0.6MMVOLTAGE=0VMIN_NECK_WIDTH=0.2MM

AUD_GPIO_3

GND_AUDIO_CODEC

AUD_GPIO_2

AUD_SPKRAMP_1MUTE_L

L01_P_R




AUDIO: SPEAKER AMP

MF-LF

1%

402

1/16W

17.4K

1%

402MF-LF1/16W

20.0K

402

0.001UF

X7R50V10%

NOSTUFF

402-1X5R

10%1UF10V

402-1X5R

1UF10V10%

MAX9736BETJ+

CRITICALTQFN

X7R25V

1UF10%

805

180-OHM-1.5A

0603-LF

CRITICAL

5%1000PF

402NP0-C0G25V

25V

402NP0-C0G

5%1000PF

0.1UF

CERM603

16V20%

X7R50V10%

603-1

0.1UF

0603-LF

CRITICAL180-OHM-1.5A

CRITICAL

0603-LF

180-OHM-1.5A

1000PF5%

NP0-C0G402

25V

402

25V

1000PF5%

NP0-C0G

180-OHM-1.5A

0603-LF

CRITICAL

66

66

66

66

0

1/16W5%

402MF-LF

NOSTUFFMF-LF402

5%1/16W

0

68 62

20%100UF

TANT16V

D-HF

20%100UF

TANT16V

D-HF

MF-LF1/16W5%100K

402

67 65 64

68 65 62

68 67 66 65 64 62 6

68 67 66 65 64 62 6

62

0.47UF

X5R10V10%

402

62

67 65 64

10%

X5R

0.47UF

402

10V

67 65 64

67 65

MF-LF1/16W5%

0

402

MF-LF1/16W1%

17.4K

402

100PF5%

CERM50V

402

1%

MF-LF402

1/16W

20.0K

NOSTUFF

0.001UF

402X7R50V10%

402-1

10%

X5R

1UF10V

68 67 65 63 62

REG

VS

C1P

BOOT

C1N

OUTL1-OUTL1+

OUTL2-OUTL2+

OUTR1-OUTR1+

OUTR2-OUTR2+

NC1

NC2NC3

FBL

COM

INL

INRFBR

MONOSHDN*

MOD

REGENMUTE*

THMPGNDAGND

PVDD

PAD

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AMP VOUT = 7.355VRMS

GAIN = -4.8(20K/17.4K)

MAX9736B APN:353S2042TURN ON TIME: 110MSTURN ON DELAY: 150MS

FC = 19.5 HZCODEC OUT = 1.335VRMS

POUT = 6.76 W INTO 8 OHMS @ 1% THD+N

WOOFER SPEAKER AMPLIFIER

RIN = 17.4 OHMS

65 OF 110

051-7845

A.0.0


2

1C6599

2

1C6598

2

1R6506

2

1 C6505

2

1C6503

21

C6595

21

C6596

21

C6513

21

C6512

21

R650321

R6502

21

R650021

R6501

2

1 C6507

2

1C6508

21

L650221

L6501

2

1 C650921

R6504

2

1 C6511

21

L6503

21

L6500

2

1C6502

2

1C6501

21

R6505

2

1 C6504

16

10

11

15

3027

29

28

26

24

25

23

322

311

178

7

9

420

18

6

19

5

33

12

2221

3

14

13

U6500

2

1 C65102

1C6506

AUD_MAX9736_INLAUD_MAX9736_FBL


AUD_R_NOUT

0.2MM0.5MM

AUD_R_POUT

0.2MM0.5MMAUD_L_NOUT


AUD_L_POUT


AUD_MAX9736_COM

=PP3V3_S0_AUDIO

AUD_MAX9736_FBR

AUD_BOOT


AUD_SPKRAMP_MUTE_L


MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MMVOLTAGE=0V

AUD_SPKRAMP_SHDN_L



MAX9736_INT_REG


L02_P_L


AUD_MAX9736_VREG



AUD_LO2_P_R

MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM

L02_P_R

AUDSAMPCPPMIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.2MM


AUD_LO2_P_L

MIN_LINE_WIDTH=0.2MMAUDSAMPCPN


=PP3V3_S0_AUDIO

AUD_GPIO_3

GND_AUDIO_CODEC

AUD_MAX9736_INR

VOLTAGE=12VMIN_LINE_WIDTH=0.6MM







AUDIO: SPEAKER AMPSYNC_MASTER=SKIPAUDIO SYNC_DATE=06/01/2009

20%100UF

TANT16V

D-HF

20%100UF

TANT16V

D-HF

100K5%1/16WMF-LF402

10V

1UF

X5R

10%

402-1

10V

1UF10%

X5R402-1

0.47UF

10%

402

10VX5R

402

0.47UF

X5R

10%10V

67 65 64

67 65 64

67 65 64

68 64 62

68 67 66 65 64 62 6

68 67 66 65 64 62 6

62

62

67 64

10%50VX7R402

0.001UF

NOSTUFF

0.001UF

50V10%

X7R402

NOSTUFF

20.0K

1/16W

402MF-LF

1%1%

402

17.4K

1/16WMF-LF

402

1%

20.0K

1/16WMF-LF

1/16WMF-LF402

1%

17.4K

402

25V

1000PF5%

NP0-C0G

25V

402NP0-C0G

5%1000PF

180-OHM-1.5A

0603-LF

CRITICAL

CRITICAL180-OHM-1.5A

0603-LF

66

66

66

66

402

25V

1000PF5%

NP0-C0GMF-LF1/16W5%

0

402

0.1UF

603-1

10%50VX7R

CRITICAL

0603-LF

180-OHM-1.5A

180-OHM-1.5A

CRITICAL

0603-LF

10V

1UF

X5R

10%

402-1

CERM

20%16V

0.1UF

603

0

MF-LF402

5%1/16W

100PF5%

CERM50V

402

CRITICAL

MAX9736BETJ+TQFN

X7R25V

1UF10%

805

5%

NP0-C0G402

25V

1000PF

68 67 64 63 62

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

INOUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AUD_HP_GND_JACK

AUD_LI_GND_JACK

PP3V3_AUDIO_SPDIF_JACK

APPLE P/N 518S0723

NC TWEETER (SECONDARY)

PROPERTIES FOR ALL SPKR NETS

WOOFER (PRIMARY)WOOFER (PRIMARY)

TWEETER (SECONDARY)

REMOTE I/O CONNECTOR

SPEAKER CABLE CONNECTORSAPPLE P/N 518S0656APPLE P/N 518S0748INTERNAL MIC CON

APPLE P/N 518S0677

PROPERTIES FOR ALL SPKR NETS

66 OF 110

051-7845

A.0.0


4

3

2

1

J6602

5

4

3

2

1

J6603

21

L661821

L6616

21

R6610

21

R661721

XW6617

21

L661321

L6612

21

L6606

21

R6601

21

L6605

9876

543

24

23

22

21

20

2

19

1817161514

13121110

1

J6600

3

2

1

5

4

J6601

21

L6615

2

1C6600

2

1

DZ66032

1

DZ6615

2

1

DZ66062

1

DZ6608 2

1

DZ6610 2

1

DZ6612 2

1

DZ6614

21

L660921

L6608

21

L6607

2

1 C6601

2

1R6600

2

1

DZ6607

2

1

DZ6604

21

L6614

2

1

DZ66092

1

DZ66052

1

DZ6611 2

1

DZ6613

2

1

DZ66012

1

DZ6600

21

L6604

21

L6601

21

L6603

21

L6600

21

L6602

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_HP_GND_JACKMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM AUD_HP_L_JACK

MIN_LINE_WIDTH=0.2MM VOLTAGE=3.3VMIN_NECK_WIDTH=0.1MM PP3V3_AUDIO_SPDIF_JACK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_TIPDET_JACK

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM HS_MIC_HI_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM HS_MIC_LO_JACK



AUD_SPDIF_OUT_JACK

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM AUD_LI_DET_JACK

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM AUD_LI_L_JACK





AUD_SPKR_OUTLO2L_NOUTNC_J6702_3NO_TEST

MIN_NECK_WIDTH=0.1MMVOLTAGE=0VMIN_LINE_WIDTH=0.2MM

GND_AUDIO_MIC1_CONN

AUD_SPDIFIN_JACK

MIN_NECK_WIDTH=0.2MM AUD_LI_GND_JACKMIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM AUD_LI_R_JACK


AUD_MIC_IN1_P_CONN

GND_AUDIO_HP_AMP_LMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM


AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM AUD_HP_TYPEDET_JACK

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMVOLTAGE=0VAUD_HP_R


AUD_HP_L


AUD_HP_TIP_DET


AUD_LI_R

AUD_LI_TIP_DET

MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MMAUD_LI_GND

MIN_LINE_WIDTH=0.2MMMIN_NECK_WIDTH=0.1MMAUD_IP_PERPH_DET

HS_MIC_LOVOLTAGE=0VMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM

AUD_SPDIF_OUT


AUD_HP_TYPE

AUD_LI_L



HS_MIC_HI

AUD_SPDIF_IN

AUD_MIC_IN1_N_EMI


AUD_MIC_IN1_P_EMI


AUD_MIC1_IN_N

=PP3V3_S0_AUDIO

AUD_MIC1_IN_P


AUD_MIC_IN1_N_CONN

AUD_HP_R_JACKMIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.2MM AUD_IP_PERPH_JACK


AUD_SPKR_OUTLO2R_NOUTAUD_SPKR_OUTLO2R_POUT


Audio: MLB to I/O Conn.

M-RT-SM78048-0473

CRITICALCRITICAL

M-RT-SM78048-0573

220-OHM-0.7A-0.28-OHM

0402

220-OHM-0.7A-0.28-OHM

0402

603

5%

0

1/10WMF-LF

MF-LF603

5%

0

1/10W

SM

63

63

63

67

62

0402

FERR-1000-OHM0402

FERR-1000-OHM

FERR-1000-OHM

0402

67

103 9

5%1/16W

402

22

MF-LF

0402

FERR-1000-OHM

20143-020E-20F

CRITICAL

F-RT-SM

53780-8603

CRITICAL

M-RT-SM

FERR-1000-OHM

0402

10VX5R

402-1

1UF10%

6.8V-100PF402

CRITICALCRITICAL

4026.8V-100PF

6.8V-100PF402

CRITICAL

6.8V-100PF402

CRITICAL

6.8V-100PF402

CRITICAL CRITICAL

4026.8V-100PF

402

CRITICAL

6.8V-100PF

67

63 62

68

68

FERR-1000-OHM

0402

63

FERR-1000-OHM

0402

63

FERR-1000-OHM

0402

10VX5R

10%0.47UF

402

1/16W

0

402MF-LF

5%

67

67 65

65

64

64

64

65

65

64

68 67 65 64 62 6

67

103 62 CRITICAL

4026.8V-100PF

402

CRITICAL

6.8V-100PF

FERR-1000-OHM

0402

6.8V-100PF

CRITICAL

402

CRITICAL

4026.8V-100PF

6.8V-100PF402

CRITICAL CRITICAL

4026.8V-100PF

6.8V-100PF402

CRITICALCRITICAL

6.8V-100PF402

FERR-1000-OHM

0402

FERR-1000-OHM

0402

0402

FERR-1000-OHM

0402

FERR-1000-OHM

FERR-1000-OHM

0402

110

110

G

S

D

G

S

D

G

S

D

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN OUT

OUT

OUT

IN

OUT

OUT

G

S

D

IN

IN

G

S

D

G

S

D

IN

G S

D




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

IPHS HS DETECT DEBOUNCE CKT

NC

DIGITAL OUT HEADPHONE OUT

NC

NC

PLACE ACROSS GROUND SPLIT

AUDIO GROUND RETURNSLI INSERT DETECT

MICROPHONE IMPEDANCE MATCHING CIRCUIT

67 OF 110

051-7845

A.0.0


21

R6749

21

R6748

2

1R6768

2

1

3

Q6703

2

1R6762

4

5

3

Q6700

1

2

6

Q6700

2

1R6730

2

1R6731

21

R6732

2

1 C6740

21

R6700

2

1R6797

4

5

3

Q6701

2

1R6792

2

1R6793

21

R6747

2

1C6751

2

1R6798

2

1R6791

21

C6796

2

1R6701

21

R6796

2

1 C6797

21

R6799

2

1R6794

2

1R6744

2

1C6750

2

1R6795

2

1R6790

1

2

6

Q6701

1

2

6

Q6702

4

5

3

Q6702

21

L6739

21

L6738

21

XW670421

XW6703

21

R6743

21

XW6705

21

XW6702

21

C6795

GND_AUDIO_CODEC

AUD_IP_PERPH_DET_R

AUD_IP_PERIPHERAL_DETAUD_IP_PERPH_DET_DB

AUD_IP_PERPH_DET_INV

AUD_IP_PER_DEB

AUD_IP_PERPH_DET

AUD_SENSE_A

AUD_SENSE_A

=PP3V3_S0_AUDIO

AUD_SENSE_A

AUD_Q6702_D3

AUD_HP_TYPE_INV

AUD_Q6701_D6=PP3V3_S0_AUDIO

AUD_LI_TIP_D

AUD_LI_TIP_DET_INV

GND_AUDIO_CODEC

=PP12V_S0_AUDIO_SPKRAMP




MIN_NECK_WIDTH=0.2MMVOLTAGE=12VMIN_LINE_WIDTH=0.6MM

GND_AUDIO_CODECMIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.2MM

AUD_MIC1_IN_P

AUD_MIC1_IN_G


AUD_MIC1_IN_N



AUD_CODEC_MICBIAS

MIN_NECK_WIDTH=0.2MMMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM

AUD_INTMICBIAS


GND_AUDIO_CODEC


AUD_MIC_INN_R

AUD_LI_TIP_DET

AUD_HP_TYPE

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

AUD_HP_TIP_DET

AUD_HP_TIP_DET_INV

GND_AUDIO_CODEC


AUD_MIC_INP_R

=PP3V3_S0_AUDIO

AUDIO: Detects/GroundingSYNC_DATE=06/01/2009SYNC_MASTER=SKIPAUDIO

402

5%

0

MF-LF

NOSTUFF

1/16W

402

5%

0

MF-LF

NOSTUFF

1/16W

1/16W5%

MF-LF402

100K

SOT23-HF12N7002

68 67 66 65 64 62 6

MF-LF1/16W5%100K

402

NTZD3154NT1HSOT-563-HF

SOT-563-HFNTZD3154NT1H

68 67 66 65 64 62 6

5%

MF-LF402

1/16W

100K

402MF-LF1/16W5%0

1/16WMF-LF

0

5%

402

NOSTUFF

66

10%16VX5R402

0.1UF

17.4K

402

1%1/16WMF-LF

1/16W

402

100K5%

MF-LF

SOT-563-HFNTZD3154NT1H3.40K

1%

402

1/16WMF-LF

3.40K

MF-LF1/16W1%

402

62

62

402

5%

0

MF-LF

NOSTUFF

1/16W

603-HF

6.3V20%

TANT

CRITICAL

4.7UF

62

1/16W5%

MF-LF

100K

402

68 67 65 64 63 62

65 64

65 64 6

67 62

66

67 62

68 67 66 65 64 62 6

66

66

68 67 66 65 64 62 6

67 62

66

66

MF-LF402

1/16W5%100K

10%

X5R402

16V

0.1UF

MF-LF

10K1%

402

1/16W

5%

402MF-LF1/16W

0

X5R

NOSTUFF

10%16V

0.1UF

402

MF-LF1/16W5%

0

402

17

0.1%

402

1/16W

20K

CRITICAL

MF

1%

MF-LF402

39.2K1/16W

402

10%25V

0.0082UF

X7R

100K1/16W

402MF-LF

5%

402

100K5%1/16WMF-LF



SOT-563-HFNTZD3154NT1H

FERR-250-OHM

SM-1

FERR-250-OHM

SM-1

OMITSM

OMITSM

2.2K

5%

402MF-LF1/16W

SM OMIT

SM

0.1UF

402

16VX5R

10%

68 67 65 64 63 62

68 67 65 64 63 62

68 67 65 64 63 62

68 67 65 64 63 62

68 67 65 64 63 62

68 67 66 65 64 62 6

IN

BI

OUT

IN

IN

IN

OUT

OUT

IN

INOUT

OUTIN

IN

GND THMENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASSINT*

SCL




36

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DR


SHEET

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C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

APN 353S2256

MIKEY RECEIVER CKTWRITE: 0X72 READ: 0X73

0X0C

GPIO 3CNTRL

FHP = 80 HZ

MIKEY

FLP = 8.82 KHZ

MICBIAS 80%

N/A

0X04

N/A

PIN0X0A

0X100X0F

FUNCTIONPRIMARYSECONDARY

0X0B

0X09

LINE INPUTBUILT-IN MICROPHONEHEADSET MICROPHONE

0X0D(13,B,RIGHT)

TYPE DETECT/INTERRUPTN/A

N/ALINE IN

N/A

N/AMCP GPIO_5

0X09 (A)GPIO 3

ENABLE/VOLUME

0X05

N/AN/A

0X06

0X03

N/A

0X06

0X02

N/A

0X080X060X06

0X020X030X04

N/A0X07

0X05

CONVERTER

0X0D (13,V22,B,LEFT)SPDIF OUTSPDIF IN

HEADPHONES

MIKEY

MIKEYN/AN/AMCP GPIO_38

0X0C (B)

68 OF 110

051-7845

A.0.0


11

5

6 1

7

4 9

8

2

10

3

U6806

21

C6802

21

C6801

2

1D6800

2

1 C6853

21

R6810

2

1R6808

2

1 C6852

2

1 C6854

21

R6805

21

R6804

21

R6803

21

R6802

2

1R6806

2

1R6807

21

L6840

2

1 C6899

2

1R6852

2

1R6809

2

1 C6857

HS_MIC_BIASMIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.15MM

VOLTAGE=3.3VPP3V3_S0_HS_F



HS_SW_DET


HS_RX_BP


HS_MIC_LO

=PP3V3_S0_AUDIO


AUD_MIC_INN_L

AUD_MIC_INF



AUD_MIC_INP_L

AUD_GPIO_3

HS_MIC_HI


AUD_GPIO_2

=PP5V_S0_AUDIO

=I2C_AUDIO_SCL

HS_SCL

HS_SDA

=I2C_AUDIO_SDA

HS_INT_LAUD_I2C_INT_L HS_RST

AUD_IPHS_SWITCH_EN

GND_AUDIO_CODEC

GND_AUDIO_CODEC

SYNC_MASTER=SKIPAUDIO SYNC_DATE=06/01/2009

AUDIO: Mikey

25VX7R402

10%0.01UF

1/16W5%

402

1K

MF-LF MF-LF

2.2K1/16W

402

5%

402-1

10VX5R

1UF10%

CRITICAL

DRCCD3275

X5R

10%16V

402

0.1UF

10%

X5R16V

402

0.1UF

1N4148WS-X-GSOD-323-HF

NOSTUFF

65 64 62

64 62 64 62

65 64 62

402

25VX7R

10%0.0082UF

2.2K

402

5%

MF-LF1/16W

100K1/16WMF-LF402

5%

X5R

CRITICAL

20%

603

6.3V

10UF

67 66 65 64 62 6

62 6

62

62

66

66

4.7UF

603-HF

6.3V20%

TANT

CRITICAL

19

21

52

52

5%

0

MF-LF402

1/16W

0

5%1/16W

402MF-LF

MF-LF402

1/16W

0

5%

402MF-LF

5%

0

1/16W

47K1/16WMF-LF

5%

402

NOSTUFF

1/16W

402MF-LF

5%100K

FERR-1000-OHM

0402

68 67 65 64 63 62

68 67 65 64 63 62




36

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DR


SHEET

PAGE TITLE

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A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

12V_S0 SUPPLIED BY AC/DC, GATED BY PM_SLP_S3_L

5V_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT

3V3_S0 FET GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG; RC SOFT TURN-ON CIRCUIT; SLOWER THAN 5V_S0

1V8_S0 LDO SOURCED FROM 5V_S0, ENABLED BY 5V_S0 WITH RC DELAY

1V5_S0 FET SOURCED FROM 1V5_S3, GATED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

MCP_VCORE REGULATOR INTERNAL LOGIC POWERED FROM 5V_S3, SOURCED FROM 12V_S5,

1V05_S0 REGULATOR SHARES INTERNAL LOGIC POWER WITH 3V3_S5 REG, SOURCED FROM 12V_S0ENABLED BY PM_SLP_S3_L*12VS0_PG*1V5_S3_PG WITH RC DELAY

CPU_VCORE

VTT_S0_DDR_LDO

1V05_S0

MCP_VCORE

1V5_S0

1V8_S0

MCP: PM_SLP_RMGT_L

1V05_RMGT FET SOURCED FROM 1V05_S5, ENABLED BY PM_SLP_RMGT_L

PM_SLP_RMGT_L FOLLOWS PM_SLP_S4_L TIMING CLOSELY

3V3_RMGT FET SOURCED FROM 3V3_S5, ENABLED BY PM_SLP_RMGT_L

12V_S5

3V3_RMGT

1V05_RMGT

RMGT POWER RAIL SEQUENCING

3V3_S5

1V05_S5

S5 POWER RAIL SEQUENCING

3V3_S5 SWITCHER LOGIC POWERED BY INTERAL LDO, SOURCED FROM 12V_S5

12V_S5 SUPPLIED BY AC/DC MAX RAMP TIME < 50MS MAX RAMP RATE 10V/MS

1V05_S5 SWITCHER SOURCED FROM 3V3_S5 AND ENABLED FROM 3V3_S5_PGOOD

OUTPUT SOURCED FROM 12V_S5 AND ENABLED BY PM_SLP_S4_L + LDO OUTPUT GOOD5V_S3 SWITCHER LOGIC POWERED BY INTERNAL LDO (EN BY SLP_S4_L)

5V3_S3

3V3_S33V3_S3 FET GATED BY PM_SLP_S4_L

1V5_S3 SWITCHER LOGIC POWERED BY 5V_S3 SO ENABLED BY PGOOD_5V_S3

MCP: PM_SLP_S4_L


SB: PM_SLP_S3_L

COUNT


SOURCED BY 12V_S5; MUST RAMP IN < 2MS

NOTE: NO SEQUENCING REQUIREMENTS FOR THESE 3 RAILS

Soft-Off (S5/M-Off)

Sleep (S3/M-Off)

Soft-Off (S5/M1)

Sleep (S3/M1)

Run (S0/M0)

State

Battery Off (G3Hot)

On

N/A

On

Off

Off

N/A

Manageability

1

1

1

1

0

1

SMC_PM_G2_ENABLE

1

0

1

0

0

1

PM_S4_STATE_L

0

0

0

1

PM_SLP_S3_L

0

0

0

0

1

PM_SLP_S4_L

1

1

1

PM_SLP_M_L

0

0

1

1

1

0

SB: PM_SLP_S4_L

12V_S0

5V_S0

STARTUP (BOOT OR WAKE) TIMINGBOOT UP

SMC: IMVP_VR_ON

SMC STARTS

SHUT DOWN (SHUTDOWN OR SLEEP) TIMING

POWER RAILS SHUT DOWNCPU VTT_PWRGD LOW

POWER RAILS ON DURING THIS TIME

SLEEP OR SHUTDOWNSUSPEND SOONSB SAYS

SB: PM_SLP_S3_L

SB: PM_SUS_STAT#

VREGS: ALL_SYS_PWR_GD

OS COMMANDSVREG IN RESPONSE TOSMC SAYS SHUTDOWN CPU

SB PWROK DISABLE

CLK GEN DISABLEDCPU_PWRGD DISABLED

CPU VCORE OFF

IMVP6: VR_PWRGOOD_DELAY

SMC: IMVP_VR_ON

SB: PM_SLP_S3_L

3V3_S0

SB: PM_SLP_S4_L

VREGS: ALL_SYS_PWRGD

IMVP6 ON

99 MS

IMVP: VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOODALL_SYS_PWRGD * VR_PWRGOOD_DELAY

AND GATE: MCP_PS_PGOOD

MCP: CPUPWRGD

1V5_S3

69 OF 110

051-7845

A.0.0


SYNC_DATE=12/08/2008

POWER SEQUENCING BLOCK DIAGRAMSYNC_MASTER=K51

IN

OUT

OUT

OUT

OUT

Y

B

A

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

Y

B

A

IN

OUT

IN

OUT

OUT

OUT

GND

V+

OUT

IN

IN

IN

OUTIN

GND

V+

IN OUT

IN

OUT

OUT

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

USING COMPARTOR INSTEAD OF REGULATOR

NO INTERNAL POWER TO PULL PGOOD

(PM_SLP_S3_L_BUF)

12V_S0 NEED TO BE ON BEFORE MCP REG AND 1.05_S0 REG EN

Enable FET

DELAY OF ~15MS FROM PM_SLP_S3_L



(PM_S4_STATE_L)

FROM COMPARATOR

FROM COMPARATOR

Enable regulator

PGOOD Comparators

(9.91V/9.58V; 330MV HYSTERESIS)

IRF7410IRF7413

3.7A

PLACE RESISTORS CLOSE TO U7020

18mOHM35mOHM

5.8A

9.6A

I

1V05V_S0 DERIVES FROM 3.3V_S5

PM_MXM_PGOOD IS PULLED UP TO IT

WHICH GOES INTO PGOOD_SB OF MCPFROM THIS SMC GENERATES PM_RSMRST_L

DELAY IS ABOUT 200MS

To SMC (2)

Rds(on)

7mOHM

25V20V

PM_SLP_S4_L

1

1

PM_SLP_S3_L

0

1

0

0 0

0

8V

8V

Vgs +/-

12V

20V

70mOHM

115mOHM65mOHM

1.6A

13A

8.8AIRF7406

IRF6402SI2302

FDS4435

Battery Off (G3Hot)

Sleep (S3)

Soft-Off (S5)

State

Run (S0)

1

1

1

0

SMC_PM_G2_ENABLE (PORTABLES)

From SMC (6)

1.5V_S3 NEED TO BE ON BEFORE S0 FET ON

Enable regulator

AND GATE BY THE FACT THATALL_SYS_PWRGD IS ALSO AN INPUT TO THIS

S0 RAILS PGOOD

Enable FET

PLACE SHORTS CLOSE TO PLANE CUTS

NOT COME UP, PPDDR REGULATOR HASLOW

HYSTERESIS NUMBERS CALCULATED BASED ON OUPTPUT PULL UP OF 3.3V

PGOOD OUTPUT BECAUSE IF 5V_S3 DOES



(PULLUPS ARE NEAR LOADS)

PM_MXM_PGOOD IS OPEN DRAIN SIGNAL, IT’S PULLED UP TO ALL_SYS_PWRGD

MXM CARD INPUT POWER ARE 12V_S0, 3V3_S0, 5V_S0

MXM POWER SEQUENCE

ALL_SYS_PWRGD ENABLES MXM REGULATORS

Enable regulator

USB Port Switch

Power Control Signals3.3V,5V S3 enable

Enable FET

To SMC

FROM MCP (6)

(PM_SLP_S3_L)

ENABLE REGULATOR

Enable FET

70 OF 110

051-7845

A.0.0


2

1 C70832

1

R7083

21

R7085

21

R7054

21

R7053

21

R7052

21

R7051

21

R7050

8

7

5

6

4

U70302

1R70222

1 C7025

2

1R7020

2

1R7006

8

1

7

3

5

2

6

4

U7010

21

R7099

21

R7098

2

1R7007

21

XW700121

R7001

21

XW7000

2 1

XW7002

2

1R7040

2

1R7033

2

1 C7031

2

1R7031

21

R7002

21

R7000

2

1R7014

2

1R7019

2

1R7021

2

1R7013

2

1R70182

1 C7010

2

1R7008

4

5

3

1

2

U7059

2 1

C7058

2

1 C7080

2

1 C7081

2

1 C7082

2

1

R7080 2

1

R7081 2

1

R7082

2

1R7030 4

5

3

1

2

U7020

2

1 C7020

2

1R7072

5

4

1

2

3

U7056

21

C7056=PP12V_S0_VRD

PM_SLP_S3_L_AND_S0_RDY

P3V3S0_ENMAKE_BASE=TRUE

=PVTT_S0_ENCPUVTTS0_ENMAKE_BASE=TRUE

MAKE_BASE=TRUEMCPCORES0_EN

=PP3V3_S5_PWRCTL

MCPDDR_ENMAKE_BASE=TRUE

PM_SLP_S4_L

P3V3S3_EN

PM_SLP_S4_SMC_L

PM_SLP_RMGT_L ENET_EN

PGOOD_1V5_S3

12VS5_9V00_REF

=PP12V_S5_PWRCTL

PGOOD_12V_S0

PGOOD_MCPCORE_S0

MAKE_BASE=TRUE

S0_PWR_CMP_PGOOD

12VS5_1V27_REF

=MCPCORES0_EN

ALL_SYS_PWRGD_R

PGOOD_1V05_S0

RSMRST_PWRGDPGOOD_1V1_S5

=PP3V3_S5_PWRCTL

MCP_PS_PWRGD

=MCPDDR_EN

PGOOD_1V5_S3

ALL_SYS_PWRGD

ALL_SYS_PWRGD_SMC

PM_PGOOD_PVCORE_CPU

PM_MXM_PGOOD

=PPDDR_S3_PGCMP MAKE_BASE=TRUE

S0_PWR_REG_PGOOD

=PP3V3_S5_PWRCTL

PGOOD_1V5_S0

PGOOD_1V8_S0

=PP3V3_S5_PWRCTL

PP12V_S0

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PGOOD_5V_S0

12VS0_COMP_REF

1V5S3_PG_CMP 1V5S3_COMP_REF

1V8S0_PG_CMP

12VS0_PG_CMP

12VS5_1V60_REF

PGOOD_1V8_S0

1V8S0_COMP_REF=PP1V8_S0_PGCMP

ALL_SYS_PWRGD_RMAKE_BASE=TRUE

PM_MXM_EN

=PM_MXM_PGOOD_PULLUP

=PP5V_S3_PWRCTL

MAKE_BASE=TRUEPGOOD_5V_S3 =DDRREG_EN

PM_EN_USB_PWRPGOOD_5V_S3

5VREG_EN

S0_RDYMAKE_BASE=TRUE

PGOOD_12V_S0

PM_SLPS3_BUF2_L

=P3V3S0_EN

P5VS0_ENMAKE_BASE=TRUE

=P5VS0_EN


PGOOD and Power Sequencing

CERM-X5R

10%6.3V

0.47UF

402

402

5%

MF-LF1/16W

2.2K

33


50 49 33


73

78

33PLACEMENT_NOTE=Place close to U1400

33


102 21

38


33

NOSTUFF

21 0

SOI-HF

CRITICAL

LM393

MXM

402

1/16WMF-LF

5%100K

70 46

70

78

78

0.1UF20%16VCERM603

402

64.9K1%1/16WMF-LF

49.9K1%1/16WMF-LF402

70

SOI-HF

CRITICAL

LM393

70 6

5%

33

402

1/16WMF-LF

402

1/16WMF-LF

33

5%

70

1/16W

49.9K

402MF-LF

1%

SMOMIT

1.21K

1/16W

402MF-LF

1%

85

85

SMOMIT

OMITSM

10K

402

1/16WMF-LF

5%

MF-LF

1%1/16W

10K

402

0.1UF

402X5R16V10%

1/16W

1K

402MF-LF

5%

402

1%

IG

1/16W

2.0K

MF-LF

MF-LF

1%

402

1/16W

4.99K

100K1%

1/16W

402MF-LF MF-LF

1/16W

402

1%10K

10K1%1/16WMF-LF402

MF-LF402

1/16W

33.2K1%

1/16W1%

84.5K

MF-LF402

603CERM16V20%0.1UF

1%1/16W

402MF-LF

49.9K

70

85

TC7SZ08AFEAPESOT665

50 49 9 6

CERM10V

0.1UF

20%

402

10%6.3VCERM-X5R

402

0.47UF 0.47UF

6.3VCERM-X5R

402

10%

0.47UF

402

6.3V10%

CERM-X5R

39K

MF-LF

5%1/16W

402

5%1/16W

43K

MF-LF402

10K 5%

402

1/16WMF-LF

74

76

78

78

78

76

74

402

5%

10K

MF-LF1/16W

TC7SZ08AFEAPESOT665

20%0.1UF

10V

402CERM

49

MF-LF

100K5%

402

1/16W

75

49

21

71 11

MC74VHC1G08SOT23-5-HF

0.1uF

20%

CERM10V

402

71 6

70 6

78 38 6

79

70 6

70

6

70 6

70 6

6

70 6

6

55

6

70 6

6

70

70

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

IN

IN

IN

ISEN4-EN_VTT

THRM_PAD

VR_HOT

VR_FAN

ISEN4+

ISEN3-ISEN3+

ISEN2-ISEN2+

ISEN1+

PWM2

FB

PWM1

TCOMP

PSI*

IMON

OFS

VCC

VID0

VR_RDY

VID7

VID5VID4VID3

VID2

VID6

VID1

SS

FSPWM3

PWM4TM

REF

DAC

EN_PWR

RGND

VSENVDIFF

ISEN1-

COMP SYM_VER_2

IN

IN




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

CPU CORE

K22/K23 65W

VR_HOT goes HIGH when VTM/VCC < 28%

75A PEAK70A AVE

LAYOUT: PLACE RT7101 NEAR HOT SPOT.

and LOW when VTM/VCC > 33%.

1.25 mOhm loadline

INPUT SENSE & FILTER

71 OF 110

051-7845

A.0.0


2

1

RT7101

5678

4321

RP71915678

4321

RP7190

21

XW7130

21

XW7120

4321

R7169

21

L7160

2

1 C7160

2

1 C7161

21

R7133

21

R7129

21

R7128

21

R7127

21

R7135

21

R7134

2

1R7146

21

R7145

2 1

R7143

2 1

R7139

2 1

R7167

2 1

R7166

2 1

R71652

1 C7152

2

1 C7151

2

1 C7150

2

1R7162

2

1R7161

2

1R7160

2

1R7116

2

1 C7130

2

1R7164

2

1R7130

21

R7103

17

36

38

37

40123

4567

15

19

39

41

18

35

16

12

25

31

20

26

8

9

2324

29

30

2221

2827

10

34

14

33

32

11

13

U7100

2

1R7104

21

R7140

2

1 C7116

2

1 C7117

2 1

R7121

2

1 C71182 1

R7122

2

1 C7119

2

1 C7120

2 1

R7123

2

1 C71212 1

R7124

2

1 C7113

2

1 C7114

2 1

R7119

2

1 C71152 1

R7120

2

1R7106

2

1R7100

2

1R7105

2

1R7107

2

1R7108

2

1R710921

C7109

21

R7110

2

1 C7101

2

1 C7102

2

1 C7103

21

R7111

2

1 C7110

2

1R7112

2

1R7114

2

1R7115

2

1R7117

2

1 C7112

21

R7131

2

1C713121

XW7101

2

1R7132

21

R710121

C7105

2

1 C7107

21

C7104

21

R7163

21

C7106

21

R7102

2 1

R7118

CPU_INPUT_ISENSE_N

100

0.001UF

VR_CPU_EN_PWR

75K

402

50V

CPU_VCC_PKG_SENSE_N

4.75K

1/16W1%

402MF-LF

4.75K

402MF-LF1%

1/16W

4.75K

MF-LF1/16W1%

402

20.0K1/16W1%

402MF-LF

22.1K

402MF-LF1%1/16W

845

1%1/16W

402MF-LF

10.7K

MF-LF402

1%1/16W

402CERM50V5%

47PF

10%1UF

X5R10V402AGND_CPU

50V

CRITICAL

CRITICAL

1UH-20A-4.5MOHM

VR_CPU_ISNS3_R_P

VR_CPU_OFS

VR_CPU_SS

VR_CPU_PWM4

VR_CPU_VSNS_R_P

0.1UF

402

PM_PGOOD_PVCORE_CPU

PPVCORE_S0_CPU

VR_CPU_ISNS2_R_N

CPU_INPUT_ISENSE_P

PP12V_S0_CPU_FLTRDNET_PHYSICAL_TYPE=POWERVOLTAGE=12V

CPU_PSI_L

=PPVTT_S0_CPU

CPU_VCC_PKG_SENSE_P

VR_CPU_VSNS_R_N

VR_CPU_FS

VR_CPU_TCOMP

VR_CPU_PWM3_R

VR_CPU_ISNS3_RR_P

VR_CPU_REF

NET_PHYSICAL_TYPE=POWER

VR_CPU_VSNS_GNDVOLTAGE=0V

PP5V_S0_CPU_VCORE_VCC


VR_CPU_VSNS_VCCVOLTAGE=1.1V

MAX_NECK_LENGTH=3MMMIN_NECK_WIDTH=0.3MM

VOLTAGE=5VMIN_LINE_WIDTH=0.6MM


VR_CPU_COMP_R

VR_CPU_VDIFF_R1

VR_CPU_VDIFF_R2

VR_CPU_EN_VTT

VR_CPU_IOUT_PD

VR_CPU_ISNS1_RR_P

VR_CPU_ISNS2_P

VR_CPU_ISNS1_N

PP12V_S0_CPU_FLTRD

=PP5V_S0_VRD

=PP3V3_S0_VRD

=PP12V_S0_VRD

VR_CPU_VRDHOT

VR_CPU_FAN

VR_CPU_ISNS2_N

VR_CPU_COMP

VR_CPU_DAC

VR_CPU_ISNS1_R_NVR_CPU_ISNS1_R_P

VR_CPU_VSNS_MI

VR_CPU_ISNS3_P

VR_CPU_IMON

VR_CPU_FB

VR_CPU_VDIFF

VR_CPU_PWM2_R

VR_CPU_ISNS2_R_P

VR_CPU_PWM3

VR_CPU_ISNS3_R_N

PM_EN_PVCORE_CPU

VR_CPU_TM

VR_CPU_COMP_RC

VR_CPU_PWM2

VR_CPU_ISNS3_N

VR_CPU_FB_R


VR_CPU_VSNS_PL

NET_PHYSICAL_TYPE=POWERVOLTAGE=12V

PP12V_S0_CPU_FLTRD_R

VR_CPU_ISNS2_RR_P

VR_CPU_ISNS1_P

VR_CPU_PWM1

MAX_NECK_LENGTH=3MM


CPU_VID<7..0>

SYNC_MASTER=MASTER

VREG: PPVCORE_S0_CPUSYNC_DATE=N/A

10%50V

560PF

402CERM

MF-LF

0

5%1/16W402

50V10%

470PF

402CERM

1/8W5%

2.2

MF-LF805

6.8K0603

SM-LF

6801/16W5%

SM-LF

6805%1/16W

SM

SM

1%0.0021/4WMF1206

CRITICAL

TH-VERT-HF

CRITICAL

270UF

8X12-TH-HFELEC16V20%

CRITICAL

ELEC8X12-TH-HF

16V20%270UF

12

MF-LF1/16W

1K

402

5%

0

1/16W402

5%MF-LF

5%

0

4021/16WMF-LF

5%MF-LF

1K

4021/16W

10

5%MF-LF1/16W402

MF-LF5%

4021/16W

10100 12

NOSTUFF

1M1/16WMF-LF402

5%

1/16WMF-LF1%

402

47.5

MF-LF402

1/16W5%

0

5%

402

0

MF-LF1/16W

MF-LF5%

0

1/16W402

1/16W402

0

5%MF-LF

1/16WMF-LF

0

5%

402

C0G50V

NOSTUFF

1%

402

15PF

50V

NOSTUFF

1%15PF

402C0G

1%

NOSTUFF

15PF

C0G50V402

01/16W

5%

402MF-LF

5%MF-LF

402

0

NOSTUFF

1/16W

01/16W

402MF-LF

5%

NOSTUFF

05%MF-LF402

1/16W

10VCERM20%

402

NOSTUFF

5%MF-LF1/16W

0

402

05%

1/16WMF-LF

NOSTUFF

402

1%

301

1/16WMF-LF

ISL6334

QFN

100 12

402

5%0

MF-LF1/16W

0

402MF-LF1/16W5%

11

50V5%68PF

402-1CERM

AGND_CPU

10%16V0.1UF

X5R402

402

383

1/16W1%

MF-LF

CERM402

10V0.1UF20%

SIGNAL_MODEL=EMPTY

108 72

72

108 72

402-1

68PF

CERM50V5%

AGND_CPU

X5R16V10%

402

0.1UF

1%402MF-LF

383

1/16W

20%

402CERM10V0.1UF

SIGNAL_MODEL=EMPTY

108 72

72

108 72

AGND_CPU

50V68PF5%

402-1CERM X5R

0.1UF16V402

10%

383

MF-LF1/16W1%

402

402CERM10V20%

SIGNAL_MODEL=EMPTY

0.1UF

108 72

108 72

72

AGND_CPU

1/16WMF-LF

100K1%

1%1.02K1/16W

402MF-LF MF-LF

1%

4021/16W

20.0K

MF-LF402

1/16W5% 100K

1/16WMF-LF

1%

402

0.0022UF

402

10%

CERM MF-LF402

1K

1/16W1%

SIGNAL_MODEL=EMPTY

CERM10%

40250V

NOSTUFF

0.0022UF

AGND_CPU

CERM10%

402

0.0022UF 0.0022UF50V402CERM10%

VR_CPU_IOUT108 53

70 11

49 10K

1/16W

402MF-LF5%

402CERM16V10%0.01UF

2.0K1/16W

5%MF-LF

402

AGND_CPU

1/16W

49.9K

MF-LF402

1%

4021/16W1%MF-LF

49.9K

402

10%25VCERM

33NF

0

1

2

3

4

5

6

7

4021/16W5%

10K

MF-LF

10%50V

402CERM

SM

402

5%1/16W

1K

MF-LF

72 6

108

108

53

53

72 71 53

55 50 10 6

71

71

72 71 53

6

6

70 6

108

108

108

108

71

OUT

OUT

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND THRML

PHASE

LVCCUVCC

PAD

IN

OUT

OUT

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND THRML

PHASE

LVCCUVCC

PAD

IN

IN

GDSEL

LGATE

VCC

PWM

BOOT

UGATE

GND THRML

PHASE

LVCCUVCC

PAD

OUT




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM



PHASE 2

PHASE 3

PHASE 1

THESE TWO CAPS ARE FOR EMC



OUTPUT CAPS

72 OF 110

051-7845

A.0.0


321

4

5

Q7243

321

4

5

Q7223

321

4

5

Q7203

321

4

5

Q7241

321

4

5

Q7221

321

4

5

Q7201

2

1 C7292

2

1 C7293

2

1 C7294

2

1 C7296

2

1 C7295

2

1 C7297

2

1 C7298

2

1 C7299

2

1 C7280

2

1 C7281

2

1 C7282

2

1 C7283

2

1 C7284

2

1 C7285

2

1 C7286

2

1 C7287

2

1 C7291

2

1 C7290

2

1 C7289

2

1 C7288

2

1 C7249

2

1 C7229

2

1 C7205

2

1 C7215

2

1 C7211

2

1 C7210

2

1 C7207

2

1C7260

2

1C7261

2

1C7262

2

1C7263

2

1C7264

2

1C7265

2

1R7247

9 8

1

11

4

10

7

6

5

3 2

U7241

2

1C7242

2

1 C7240

2

1R7242

2

1R7245

2

1R7241

2

1 C7241

2

1R7244

2

1 C7243

2

1 C7248

2

1R7246

2

1 C7245

5

4321

D7240

2

1 C7246

2

1 C7247

2

1

XW7241

2

1 C7250

21

L7241

2

1 C7251

2

1

XW7242

2

1R7227

9 8

1

11

4

10

7

6

5

3 2

U7221

2

1C7222

2

1 C7220

2

1R7222

2

1R7225

2

1R7221

2

1 C7221

2

1R7224

2

1 C7223

2

1 C7228

2

1R7226

2

1 C7225

5

4321

D7220

2

1 C7226

2

1 C7227

2

1

XW7221

2

1 C7230

21

L7221

2

1 C7231

2

1

XW7222

5

4321

D7200

2

1 C7200

2

1R7205

2

1R7207

2

1R7202

2

1R7201

2

1 C7201

2

1C7202

9 8

1

11

4

10

7

6

5

3 2

U72012

1R7204

2

1 C7203

2

1 C7208

2

1R72062

1

XW7201

21

L7201

2

1 C7206

2

1

XW7202

DIDT=TRUE

0.001UF

402CERM10%50V

0.001UF

CERM10%50V

402

0.001UF

402

10%CERM50V

2.2

MF-LF5%1/8W805

2.21/8WMF-LF805

5%

2.21/8WMF-LF805

5%

VR_CPU_PH1_SNUBNET_PHYSICAL_TYPE=VR_CTL_PHY

CRITICAL

RJK0348DPAWPAK

WPAKRJK0348DPA

CRITICAL

WPAKRJK0348DPA

CRITICAL

CRITICAL

WPAKRJK0353DPA

RJK0353DPAWPAK

CRITICAL

RJK0353DPAWPAK

CRITICAL

VR_CPU_BOOT1_RC

PP12V_S0_CPU_FLTRD

CTLSH3-30M833

TLM833 SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY

VR_CPU_ISNS1_P

MF-LF

10%

OMIT

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

NOSTUFF

1/10W

VR_CPU_DRV2_LGATE

VR_CPU_SW2

DIDT=TRUE

VR_CPU_DRV2_PVCC

1UF10%16V

VR_CPU_BOOT2_RCNET_PHYSICAL_TYPE=POWER

VR_CPU_BOOT3_RC

71 108

SM

71 108

71 108

SIGNAL_MODEL=EMPTY

SM

16V0.01UF

CERM402

20%CERM40216V0.01UF20%

SIGNAL_MODEL=EMPTY

SM

16VX5R

1UF10%

60316VX5R-CERM

10UF

CRITICAL

10%

0805

TLM833

CTLSH3-30M833

20%270UF

8X12-TH-HFELEC16V

CRITICAL

10UF16VX5R-CERM

CRITICAL

10%

0805

10%16V0.22UF

X7R603

MF-LF5%0

1/10W603

X5R603

1/10W5%10

MF-LF603

5%1/10W

0

MF-LF

5%MF-LF

603

603X5R

1UF16V10%

10%16V1UF

X5R603

0

603MF-LF

5%1/10W

71

71 108

SM

71 108

SM

SIGNAL_MODEL=EMPTY

20%

402CERM

0.01UF16V

20%

402CERM

0.01UF16V

SIGNAL_MODEL=EMPTY

SM

603

10%1UF16VX5RX5R-CERM

0805

CRITICAL

10%10UF16V

CTLSH3-30M833

TLM833

CRITICAL

20%270UF

8X12-TH-HFELEC16V

0.22UF

603X7R10%16V

603MF-LF1/10W

5%0

10%1UF16VX5R603

105%

MF-LF1/10W603

5%1/10W

0

MF-LF603

603

105%

MF-LF1/10W

603X5R

1UF16V10%

16VX5R603

1UF

CRITICAL

DFNISL6622

0

NOSTUFF

603MF-LF1/10W5%

71

10%

603

1UF16VX5R

20%

402CERM16V0.01UF

20%

402

0.01UF16V

CRITICAL

X5R-CERM16V10UF10%

0805

20%

8X12-TH-HFELEC16V

CRITICAL

CRITICAL

0805

10%10UF16VX5R-CERM

X5R-CERM16V10UF10%

0805

CRITICAL

6.3VCERM-X5R20%22UF

critical

805-3CERM-X5R6.3V20%22UF

critical

805-3

20%22UF

CERM-X5R6.3V805-3

critical

CERM-X5R6.3V20%22UF

critical

805-36.3VCERM-X5R20%22UF

critical

805-36.3VCERM-X5R20%22UF

critical

805-36.3VCERM-X5R20%22UF

critical

805-36.3VCERM-X5R20%22UF

critical

805-3CERM-X5R6.3V20%22UF

critical

805-3CERM-X5R6.3V20%22UF

critical

805-3CERM-X5R6.3V20%22UF

critical

805-3CERM-X5R6.3V20%22UF

critical

805-3

6.3VCERM-X5R

22UF20%

critical

805-36.3VCERM-X5R

22UF20%

critical

805-3

22UF6.3VCERM-X5R20%

critical

805-3CERM-X5R6.3V20%

805-3CERM-X5R6.3V22UF20%

critical

805-3

CERM-X5R6.3V20%22UF

critical

805-36.3VCERM-X5R20%

critical

805-3

22UF6.3VCERM-X5R

22UF20%

805-3

critical

10%0.22UF16VX7R603603

0

MF-LF5%

1/10W

71

10%X5R603

1UF16V

71 108

603

10%1UF

X5R16V

NOSTUFF

603MF-LF

105%1/10W

105%

1/10W

0

NOSTUFF

603MF-LF1/10W5%

0

603

5%

603X5R16V10%


VREG: PPVCORE_S0_CPU

DIDT=TRUE

VR_CPU_DRV1_BOOTNET_PHYSICAL_TYPE=POWER

DIDT=TRUE

VR_CPU_DRV3_UGATENET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PPVCORE_S0_CPU

VR_CPU_SW3NET_PHYSICAL_TYPE=POWER

DIDT=TRUE

DIDT=TRUE

PP12V_S0_CPU_FLTRDDIDT=TRUE

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV1_UVCC

VR_CPU_DRV1_PVCCNET_PHYSICAL_TYPE=POWER


DIDT=TRUE

PPVCORE_S0_CPU

PPVCORE_S0_CPU

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_UVCC

NET_PHYSICAL_TYPE=VR_CTL_PHYVR_CPU_PH2_SNUB

VR_CPU_ISNS2_N

NET_PHYSICAL_TYPE=VR_CTL_PHYDIDT=TRUE

VR_CPU_PH3_SNUB


DIDT=TRUE

DIDT=TRUE

VR_CPU_ISNS2_P

VR_CPU_DRV3_GDSEL

VR_CPU_DRV2_GDSEL


VR_CPU_ISNS3_N

VR_CPU_ISNS1_N

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_VCC

VR_CPU_PWM3

PP12V_S0_CPU_FLTRD

PPVCORE_S0_CPU

PP12V_S0_CPU_FLTRD

VR_CPU_ISNS3_P


VR_CPU_DRV1_GDSEL

VR_CPU_PWM1


VR_CPU_DRV2_UGATE DIDT=TRUE

VR_CPU_DRV2_UVCC

VR_CPU_DRV2_VCC

PP12V_S0_CPU_FLTRD

DIDT=TRUE

VR_CPU_DRV3_LGATENET_PHYSICAL_TYPE=POWER

DIDT=TRUE

PP12V_S0_CPU_FLTRD

NET_PHYSICAL_TYPE=POWERVR_CPU_DRV3_PVCC

NET_PHYSICAL_TYPE=POWERDIDT=TRUE

critical

POLY-TANT

330UF20%

2.5VPOLY-TANT

critical

330UF20%

2.5VPOLY-TANT

330UF

critical

20%2.5V

POLY-TANT

330UF20%

2.5V

critical critical

POLY-TANT

330UF20%

2.5V

330UF20%

POLY-TANT2.5V

critical

CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM


VR_CPU_PWM2


DFNISL6622

603

10

CRITICAL


OMIT




353S1733 2 U7221,U7241 CRITICALIC,ISL6612,SYNC,FETDRV,DFN10,LF

VR_CPU_DRV1_VCC603

MF-LF


NET_PHYSICAL_TYPE=POWERVR_CPU_SW1

CRITICAL

ISL6622DFN

VR_CPU_DRV1_LGATE

VR_CPU_DRV1_UGATE

1/10W

1UF

22UF

critical

CERM

CRITICAL

0.36UH

CRITICAL

0.36UH

CRITICAL

0.36UH

270UF

MMD10EE-SM

MMD10EE-SM

MMD10EE-SM

108

108

53 71 72

6 71 72

108

53 71 72

6 71 72

6 71 72

53 71 72

6 71 72

53 71 72

53 71 72

53 71 72

G

D

S

G

D

S

IN

INTVCC

MODE/PLLIN

TG

VIN

SWBOOST

FB

ITH

TK/SS

RUN

FREQ/PLLFLTRILIM

GND

SENSE-SENSE+

BG

THRMPAD

D

SG




36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

AVE=3.19A

PEAK=3.31A

K22/K23

EMC: C7304,C7356

OSCILLATED AT APPR. 330KHZ

SOFT START TIME 8MS

BURST MODE

POWER BUDGET

PLACE AT L7320.1

PLACE XW CLOSETO L7320

(5VS3_VOUT)

PM_SLP3_BUF1_L

RB

RA

5V_S3

LTCMODESTATE

1

0

0

1

1

0

CONT MODE

S3

S0

(5VS3_FB)

Mode

TO L7320PLACE XW CLOSE

5VREG_PS_L

PLACE AT Q7330EMC: C7353,C7354

5V S3 REGULATOR

73 OF 110

051-7845

A.0.0


2

1

3

Q7303

2

1C7331

2

1 C7307

2

1R7302

2

1 C7306

2

1C7303

2

1C7316

2

1C7334

2

1 C7325

2

1C7317

2 1

R7304

2

1R7307

2

1R7336

2

1 C7363

2

1R73622

1 C73222

1C7315

21

D7301

2

1C7345

11

2

17

1314

65

1

15

3

10

7

8

16

4

12

9

U7300

2

1

XW7300

2

1R7312

2 1

R7310

2

3

1 Q7360

2

1R7301

2

1R7311

2 1

R73242 1

C7326

321

4

5

Q7335 5

4

3

2

1

D7300

321

4

5

Q7330

2 1

L7320

2

1C7309

2

1R7306

2

1R7305

2

1 C7305

2

1

XW7301

2

1 C7301

2

1C7356

2

1 C7342

2

1C7354

2

1C7300

2

1C7335

2

1C7353

2

1C7332

2

1C7302

2

1C7304

100K

CSD58856Q5A

5%1/10W

402


5V_SNUBBER

1/10WMIN_NECK_WIDTH=0.2 MM

LTC3851EUD

603

603

5V_BOOT1_R

DIDT=TRUE

MF-LF

1

5%1000PF

C0G-CERM50V

1

MF-LF

5%

603

2.2UF

PP5V_S3_REG


5V_BOOT1MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMDIDT=TRUE

=PPVIN_S5_P5VS3

DIDT=TRUEMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

5VS3_BG

5VS3_SENSEP

=PPVIN_S5_P5VS3DIDT=TRUE

5VS3_SENSEN_R

5VS3_FB

DIDT=TRUE

5VS3_TGMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

5VS3_SENSEN

5VS3_TK_SS

5VS3_ITH


PM_SLPS3_BUF1_L PM_SLPS3_BUF1_R_L

5VS3_ITH_R

LTCMODE

5VS3_SENSE

5VREG_PS_L

LTCMODE

LTCINTVCC

LTCINTVCC

5VREG_EN5VS3_FREQ

SWITCHNODE

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM5VS3_SW

DIDT=TRUE

5V_S3 REGULATORSYNC_MASTER=MASTER SYNC_DATE=N/A

SI2301BDS

CRITICALSM-HF

402

0.1UF10%16VX5R

100PF50VCERM402

5%

24.9K

MF-LF402

1/16W1%

10%50V

402CERM

0.001UF

0.1UF10%

402

25VX5R

402

16V10%

CERM

0.01UF

402

10%50VCERM

0.001UF

35V

4.7UF10%

X5R-CERM0805

5%

CERM

20PF

402

50V

402CERM10V10%

0.22UF

0

402

5%1/16WMF-LF

1%1/16W

1.24K

MF-LF402

1/16W1%

MF-LF

1.5K

805-1

10UF

CERM20%6.3V

50V5%

100PF

CERM402

SOD-123-HFB0530WXG

0805X5R-CERM

16V

10UF10%

10%

603

16VX5R

CRITICAL

QFN

OMIT

SM

100K1/16W5%

MF-LF402

1/16W

402MF-LF

10K

5%MMBT3904GSOT23

X5R-CERM

10%10UF

16V

0805

X5R

10%0.1UF

25V

402

1/16WMF-LF

402

5%

73

X5R-CERM16V10%

0805

10UF

100K1/16W5%

MF-LF402

CASE-D3L-SM

CRITICAL

20%

POLY-TANT6.3V

330UF

X5R402

10%25V

0.1UF

MLP5X6-LFPAK-Q5A

CRITICAL

CRITICAL

CTLSH3-30M833TLM833

MLP5X6-LFPAK-Q5ACSD58856Q5A

CRITICAL

SM

2.2UH-10A-11.6M-OHM

CRITICAL

50VCERM402

100PF5%

402MF-LF1/16W

1%8.06K

1/16W

402MF-LF

1%43.2K

20%

CRITICAL

330UF

CASE-D3L-SMPOLY-TANT6.3V

OMITSM

6.3V20%CERM805-1

10UF

402

10%25V

0.1UF

X5R

270UF

ELEC

20%

8X12-TH-HF

16V

CRITICAL

402

10%X5R25V

0.1UF

110 6

73 6

73 6

94 9

73

73

73

108

G

D

S

G

D

S

OUT

IN

IN

IN

IN

SOFT

RBIAS VIN

UGATE

VW

VSS

VSEN

VR_ON

VO

VID1

VID0

THRM_PAD

RTN

PVCC

PHASEPGOOD

PGND

FDE

FB

BOOT

VDD

VID2VID3

IMON

AF_EN

VDIFF

COMP

LGATE

ICOMP

ISN

OCSET

ISP

NC




36

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PAGE


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8 7 5 4 2 1

TABLE_5_ITEM

TABLE_5_ITEM



(MCPCORES0_PHASE)

PLACE AT Q7460

(MCPCORES0_UGATE)

(MCPCORES0_VW)

(MCPCORES0_VSEN)

(MCPCORES0_ISP)

(MCPCORES0_RTN)

(MCPCORES0_VDIFF)

(MCPCORES0_FB)

(MCPCORES0_COMP)

PLACE XW NEAR THE MCP,MCPCORE AND GND BALLOF MCP

(MCPCORES0_LGATE)

(MCPCORES0_ISN)

EMC:

Vout = See below

MAX CURRENT: 20A

MCP CORE

(=PPMCPCORE_S0_REG)

(MCPCORES0_VO)

F = 200-300 KHZ

CONNECT SENSE LINES TO CLOSEST

(MCPCORES0_ICOMP)

000 +1.100V

VID<2:0> Voltage

1.1V DEFAULT, OTHER VALUES TBD

EMC: C7467,C7457

PLACE AT L7460

74 OF 110

051-7845

A.0.0


2

1R7485

2

1R7484

4

15

8

29

12

14

272625

24

7

16

18

33

2

9

1

22

1931

20

3

23

21

13

11

28

10

32

6

5

17

30

U7401

2

1R74832

1C7483

2

1C7484

2

1 C7467

21

XW7462

21

XW7463

21

R7479

21

R7477

21

R7478

21

C7480

21

C7481

21

C7482

2

1C7479

2

1R7471

2

1R7476

2

1R7472

2

1C7476

21

R7468

21

R7466

2

1 C7470

21

R7492

2

1R7463

21

R7490

21

R7491

2

1R7461

2

1C7461

21

XW7461

2

1R7475

2

1R7473

21

R7474

2

1 C7462

2

1R7469

321

4

5

Q7465

2

1 C7455

2

1 C7472

21

C7464

21

R7460

2

1 C7477

2

1 C7473

321

4

5

Q7460

2

1 C7478

2

1R7470

2

1R7464

21

R7465

2

1 C7463

2

1R7462

2

1

XW7460

2

1R7467

21

L7460

2

1C7471

2

1 C7460

2

1 C7474

2

1 C7475

2

1 C7457

2

1

XW7402

2

1 C74652

1 C7469

2

1C7466

2

1 C7468

10%

0.4991/10W

603MF

1%

10%

402CERM50V

0.0022UF

X7R

402X5R

=PPVIN_S0_MCPCORE

MCP_ISL6263D


DIDT=TRUEMIN_NECK_WIDTH=0.4MM

MCPCORES0_SNUBBER

MCPCORES0_UGATE

DIDT=TRUE


GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 MM

PGOOD_MCPCORE_S0

MCP_VID3

MCP_ISL6263D_OFFSET0

MCP_VID<2>

MCP_VID2_R

MCPCORES0_SOFT

MCPCORES0_VSEN

MCPCORES0_FDE=MCPCORES0_EN

MCPCORES0_RTN

MCPCORES0_COMP

MCPCORES0_FB

MCP_VID1_RMCP_VID0_R

MCPCORES0_IMON MCPCORES0_BOOT

DIDT=TRUE0.25 MM0.2 MM

0.2 MM0.6 mmVOLTAGE=5V

5V_S3_MCPREG_VIN

0.25 MM0.2 MM

MCPCORES0_ISP_R

MCPCORES0_ISN_R

MCPCORES0_VDIF_C

MCPCORES0_COMP_C

PPMCPCORE_S0_REG

MCPCORES0_RSEN_L

MCPCORES0_RSEN_H

PPMCPCORE_S0_REG

MCPCORES0_ISN

MCP_VID<0>

MCP_VID<1>

MCPCORES0_VDIFF

MCPCORES0_VO

MCPCORES0_ISP

MCPCORES0_LGATEDIDT=TRUE

MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MMGATE_NODE=TRUE

MCPCORES0_VW

MCPCORES0_ICOMP

MCPCORES0_RBIAS

DIDT=TRUE

=PP3V3_S3_MCPREG

GND_MCPCORES0_AGND


VOLTAGE=0VMIN_LINE_WIDTH=0.6 mm

MCPCORES0_OCSET

PPMCPCORE_S0_REG

=PP5V_S3_MCPREG

MCPCORES0_PHASE

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MCP CORE REGULATORSYNC_MASTER=MASTER SYNC_DATE=N/A

U7401 MCP_ISL9563ACRITICALINTERSIL ISL9563A1353S2497

MCP_ISL6263DINTERSIL ISL6263D353S2303 U74011 CRITICAL

10UF25VX5R

10%

805

MCP_ISL6263D

402

1/16WMF-LF

1%20.0K

1%20.0K

MF-LF1/16W

402

QFN

OMIT

CRITICAL

ISL9563A

20.0K

MF-LF1/16W

402

1%

603X5R4V

20%10UF

20%4V

X5R603

10UF

0.1UF

X5R

10%25V

402

SM

OMIT

SM

OMIT

402X5R25V

21

21

21

402MF-LF

2.21K

1/16W1%

1%1/16WMF-LF402

133K

1%1/16WMF-LF402

100

68PF

50VCERM

5%

402-1

CERM402

50V

560PF

10%

402CERM50V10%

560PF

10%

402X7R50V

0.001UF

OMIT

SM

1%1/16W

402

100

MF-LF

402

1%1/16WMF-LF

6.98K

402

1%

MF-LF

150K1/16W

0.1UF

X7R-CERM402

10%16V

1/16W

402MF-LF

1%

20

20

402

1%1/16WMF-LF

10%

X7R402

50V

0.001UF

0

MF-LF

5%

402

1/16W

1%

MF-LF402

1/16W

100

5%

MCP_ISL9563A

1/16W

402

0

MF-LF

1/16W

402MF-LF

0

5%

70

70

MF-LF1/16W

402

1K5%

16V

402

1UF

X5R

10%

SM

OMIT

MF-LF1/16W

402

1%59.0K

MF-LF1/16W

10K

402

1%

0

1/10W

603

5%

MF-LF

402

16VX5R

10%

9.53K1%

MF-LF402

1/16W

CSD58857Q5MLP5X6-LFPAK-Q5

25V10% 0.1UF

X5R25V

402

10%

CERM

0.0027UF

402

10%50V

1/10W

2.2

5%

MF-LF603

X5R25V10%0.1UF

402

0.12UF

CERM-X5R10.0V

402

10%


CRITICAL

402X5R25V

0.1UF10%

MF-LF

1%1/16W

10K

402

11.3K

MF-LF1/16W1%

402

CRITICAL

0603-LF

10KOHM-5%

603

4VX5R

10UF20%

OMIT

MF-LF1/16W

402

1%1K

1.0UH-29A-2.5MOHM

CRITICAL

8X12-TH-HF

270UF

ELEC

20%16V

CRITICAL

10UF

X5R25V10%

805

10UF10%

805

25VX5R

0.22UF

60316V

MCPCORES0_BOOT_R

0.1UF10%

CRITICAL

2.5VPOLY-TANT

330UF20%

20%

CRITICAL

POLY-TANT2.5V

330UF

CASE-D2E-SM

CASE-D2E-SM

1UF

0.1UF

MMD12EZ-SMSWITCHNODE

SM

CRITICAL

108 54

74 54 6

74 54 6

6

6

74 54 6

6

108

MODE

VDDQSNSCOMP

NC0NC1

VTTSNS

VTT

VTTREF

PGOOD

S3S5

VTTGND THRM_PAD GND CS_GNDPGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILTV5IN

SYM (2 OF 2)

IN

IN

NCNC

G

D

S

G

D

S




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8 7 5 4 2 1

PEAK = 11.28AAVG = 6.72A

FEEDBACK THROUGH SHORT

14.75A MAX OUTPUT

<Rb>

<Ra>

EMC CAPS

f = 400 kHz

(Q7335 limit)

PLACE CLOSE TO L7530

VTTREFS3 VDDQ

1.5 V DDR SUPPLY

VTT Enable

S0

S5S3 LO HI

S5 VTTHI ON

ONOFF OFF

ONON

OFFOFF

LO

ON

PPDDR_S3_REG

VOUT = 1.5V

(DDRREG_DRVH)

VDDQ/VTTREF Enable

SHOULD NOT NEED TP

VOUT = 1.50V

(DDRREG_FB)

Vout = 0.75V * (1 + Ra / Rb)

LO

HISTATE

EMC CAPSPLACE CLOSE TO FET

Vout = VDDQSNS/2

Vout = VTTREF

(DDRREG_VDDQSNS)

(DDRREG_CSGND)

(DDRREG_LL)

(DDRREG_DRVL)

10mA max load

VDDQ PGOOD

75 OF 110

051-7845

A.0.0


2

1

XW7501

2

1 C7563

2

1R7562

2

1 C7512

2

1 C7513

2

1 C7511

2

1 C7510

321

4

5

Q7530

321

4

5

Q7535

21

R752521

L7530

2

1 C7545

2

1 C7540

2

1C7541

2

1

XW7500

2

1 C7555

2

1

XW7545

2

1C7531

2

1C7530

2

1R75102

1C7500

2

1C7550

21

XW7535

21

XW7560

2

1C7560

2

1 C7561

21

R7505

2

1C7505

2

5

1

24

23

8

9

22

15

14

25

1110

13

18

127

4

20

3

19

21

17

16

6

U7500

2

1C7520

2

1 C7532

2

1R7521

2

1R7520

21

C7525

MLP5X6-LFPAK-Q5

CRITICAL

CSD58857Q5

CRITICAL


CASE-D2-HF1

330UF-0.009OHM

POLY

CRITICAL

2V20%

CASE-D2-HF1

330UF-0.009OHM

2V20%

POLY

CRITICAL

CRITICAL

1.5UH-22A-4MOHM

PLACEMENT_NOTE=PLACE NEXT TO L7530

GND_DDRREG_SGNDMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

MIN_NECK_WIDTH=0.2 mmVOLTAGE=5V

MIN_LINE_WIDTH=0.6 mmPP5V_S3_DDRREG_V5FILT

DDRVTT_EN

=PPVIN_S5_DDRREGDIDT=TRUE

=PP5V_S3_DDRREG

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmDDRREG_VBST_RDDRREG_VBST


DIDT=TRUE

DDRREG_VTTSNSNO_TEST=TRUE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmDDRREG_PGND

TP_PGOOD_DDRREG_S3

DDRREG_FB MIN_NECK_WIDTH=0.4MMDIDT=TRUE

MIN_LINE_WIDTH=0.4MM1V5_SNUBBER

SWITCHNODE

SWITCH_NODE=TRUEDDRREG_LLDIDT=TRUE MIN_LINE_WIDTH=0.6 mm



DDRREG_DRVHDIDT=TRUEGATE_NODE=TRUE

PPDDR_S3_REG


DDRREG_VDDQSNS

DDRREG_CSGNDMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUEDIDT=TRUE

DDRREG_DRVL


DDRREG_CS

=DDRREG_EN

PPVTT_S3_DDR_BUF

PPVTT_S0_DDR_LDO

1.5V DDR SUPPLYSYNC_MASTER=MASTER SYNC_DATE=N/A

SM

5%1000PF

NP0-C0G25V

402

NOSTUFF

MF

1%0.499

603

1/10W

NOSTUFF

603

16VCERM

0.1UF20%

16VCERM603

0.1UF20%

603

20%16VCERM

0.1UF16VCERM603

20%0.1UF

5%

603

1/10WMF-LF

0

MSQ12111R5LF-TH

6.3V20%10UF

X5R603

SM

10UF

X5R

20%6.3V

603

SM

ELEC16V20%

270UF

CRITICAL

8X12-TH-HF

270UF

ELEC16V20%

CRITICAL

8X12-TH-HF

5.90K

MF-LF

1%

402

1/16W

70

603CERM

20%6.3V

4.7UF

78 9

10%16V

0.033UF

X5R402

SMPLACEMENT_NOTE=Place next to Q7335

SM

CRITICAL

20%22UF6.3V

CERM-X5R805-3

20%22UF6.3V

CRITICAL

CERM-X5R805-3

MF-LF1/16W5%

4.7

402

10VX5R

1UF10%

402-1

CRITICAL

QFNTPS51116

100PF

402CERM

5%50V

NO STUFF

10%10UF

0805X5R-CERM16V

15.0K

402

1%

MF-LF1/16W

15.0K

MF-LF1/16W1%

402

0.1UF

20%

603CERM25V

6

30 6

6

6

6

OUT

ILIM1

NC

GND PGNDTHRM_PAD

ILIM2REFIN2

EN2OUT2

VIN

POK1REF

TON

EN_LDO

LDOLDOREFIN

BYPFB1

EN1

PVCC

LGATE2

BOOT2

PHASE2

UGATE2

POK2

SKIP*

VCC

OUT1LGATE1PHASE1

UGATE1BOOT1

IN

D1

G1

S2

G2

S1/D2

D1

G1

S2

G2

S1/D2




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8 7 5 4 2 1



AVE=0.46APEAK=0.69A

K22/K23

AVE=2.88APEAK=5.28A

K22/K23POWER BUDGET

VTT_FSB_S0

FSB VTT AND 3.3V S5 RAILS

EN1 (PPVTT_S0) CONTROLLED SEPARATELY

Vout = 1.212V for Wolfdale

f = 200 kHz

(R7614 LIMIT)

6.7A MAX OUTPUT

PLACE CLOSE TO FETEMC CAPS

(PVTTS0_LGATE)

(P1V05S0_UGATE)

EN REG ASAPAFTER LDO OUT

EN_LDO TIED TO 12V_S5 TO EN LDO FIRST & REGULATOR INTERNAL LOGIC GETS POWEREN2 (3V3_S5) IS TIED TO VCC, TIED INTERNALLY TO PVCCTIED EXTERNALLY TO LDO OUT. SO REGULATOR IS ENABLEDAS SOON AS LDO OUTPUT IS GOOD

<Rb>

INPUT POWER OF 12V_S5

NC

Vout = 0.7V * (1 + Ra / Rb)

(PVTTS0_PHASE)

(=PVTTS0_EN)

SELECTS SWITCHING FREQUENCY

(3.3V NOMINAL)

SEL A3V3 S5

NC

EMC CAPSPLACE CLOSE TO FET

TO LPLACE CLOSEEMC CAPS

POWER BUDGET

EN LDO ASAP

<Ra>

TO LPLACE CLOSEEMC CAPS

INPUT POWER OF 12V_S0

76 OF 110

051-7845

A.0.0


543

7

6

1

2

Q7660

5 4 37

6

1

2

Q7610

2

1C7678

2

1C7679

2

1C7608

2

1C7609

2

1R7663

2

1 C76622

1 C7663

2

1R7662

21

L7660

2

1 C7694

2

1 C7626

2

1 C7625

2

1 C7624

2

1 C7623

2

1 C7611

2

1 C7622

2

1C7613

2

1 R7622

2

1R7643

2

1

XW7651

2

1C7615

2

1C7617

2

1C7612

2

1C7610

2

1C7680

21

R7610

2

1C7601

2

1 C7614

2

1R7614

2

1C7620

21

L76102 1

XW7616

2

1R7620

2

1 C7616

2

1C7621

2

1R7621

2

1 C7683

2

1C7681

6

3

2615

2

33

29

32

1

19

2813

2516

22

3010

205

2318

87

3112

21

11

4

2714

9

2417

U7600

21

XW7650

2

1C7685

2

1R7667

2

1C7670

2

1 R7650

21

R7666

2

1 C7689

2

1 R7675

2

1 C7666

2

1 C7675 2

1C7691

2

1 C7692

2

1C7693

110K

MF-LF402

1%1/16W

110K1%

MF-LF402

1/16W

16V

10UF

=PPVIN_S0_PPVTT_FSB

=PPVIN_S5_P3V3S5DIDT=TRUE

SWITCHNODEMIN_NECK_WIDTH=0.20 MM

3V3S5_SWMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.20 MM

3V3S5_BG

DIDT=TRUE


3V3S5_TGMIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

DIDT=TRUE

PVTTS0_UGATEDIDT=TRUE

MIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.2MMGATE_NODE=TRUE


PVTTS0_LGATE DIDT=TRUE

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.6 mmVOLTAGE=12V

PPVIN_S5_3V3_VTT_R


VOLTAGE=5VMIN_LINE_WIDTH=0.4 MM

3V3REG_VCC

3V3S5_OUT


GND_PP3VREG_SGNDMIN_LINE_WIDTH=0.6 mm

PGOOD_1V05_S0PGOOD_3V3_S5DIDT=TRUEMIN_NECK_WIDTH=0.4MM

MIN_LINE_WIDTH=0.4MMPVTT_SNUBBER

PP5V_S5_LDO

3V3REG_TON

DIDT=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.25MM

PVTTS0_BOOT

3V3S5_ILIM

3V3S5_REF

3V3REG_VCC

3V3REG_TON

3V3S5_REF

=PP12V_S5_REG

0.2MM0.25MM3V3_BOOT2_R

DIDT=TRUE 0.25MM0.2MM

3V3_BOOT2

PVTTS0_BOOT_R


DIDT=TRUEMIN_NECK_WIDTH=0.4MMMIN_LINE_WIDTH=0.4MM3V3_SNUBBER

PP3V3_S5_REG

PVTTS0_FBPVTTS0_ILIM

=PVTT_S0_EN

PVTTS0_VSNS

SWITCHNODE DIDT=TRUE

SWITCH_NODE=TRUEMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM

PVTTS0_PHASE


FSB VTT/3.3V S5 SUPPLIES

WPAK

CRITICAL

RJK0384DPA

WPAKRJK0384DPA

CRITICAL

10%16V

X5R-CERM

10UF

08050805

10UF

X5R-CERM16V10%

10%

X5R-CERM0805

16V

10UF

X5R-CERM0805

16V10%

10UF

1%

MF1/10W

0.499

603NOSTUFF

402

5%25VNP0-C0G

1000PF

NOSTUFF

1000PF5%25VNP0-C0G402

NOSTUFF

0.4991/10W1%

MF603

NOSTUFF

CRITICAL

MMD06EZ-SM

2.2UH-10A-13.6MOHM

6.3V20%CERM

10UF

805-1

603CERM

0.1UF20%16V

20%0.1UF

603CERM16V

20%0.1UF

603CERM16V

20%

603CERM16V

0.1UF20%

603CERM16V

20%

603

16V

0.1UF

CERM0805

X5R-CERM

10%

5%

402

1/16WMF-LF

0

402MF-LF1/16W5%0

NOSTUFF

SM

OMIT

X5R-CERM

10%16V

0805

10UF16V

0805X5R-CERM

10UF

10UF10%16V

0805X5R-CERM

0805X5R-CERM

10%16V

10UF

0805

10UF16V10%

1/10W5%

0

MF-LF603

16V

1206X5R

10UF10%

50V10%

X7R603-1

0.1UF

50V

100PF5%

CERM402

NO STUFF

CRITICAL

1.5UH-12A

MMD06EZ-SM

SM

PLACEMENT_NOTE=Place next to C7516

1%

402MF-LF1/16W

7.32K

0.1UF16VCERM

20%

603

402

0.5%1/16WMF

10.0K

70

10%16V

10UF

080516V

100UF

CRITICAL

20%

POLY6.3X9-TH

ISL6237

QFN

CRITICAL

OMIT

SM

0.1UF10%16V

X7R-CERM402

10%

603

16V1UF

X5R

2.2

805

5%1/8WMF-LF

603MF-LF1/10W

0

5%

603

20%4.7UF

CERM6.3V

5%

402MF-LF1/16W

200K

25V10%X5R402

0.1UF

10%16V1UF

603X5R

70

20%16VCERM

0.1UF

603

20%10UF

CERM6.3V

805-1

330UF20%

CRITICAL

6.3VPOLY-TANT

CASE-D3L-SM

2.5VPOLY-TANT

330UF20%

0.1UF

PPVTT_S0_FSB_REG

CASE-D2E-SM

VOLTAGE=0V

X5R-CERMX5R-CERM

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2MM

OMIT

OMIT

152S1078 1 IND,PWR,1.5UH,20%,9A,12mOHM L7610 CRITICAL

CRITICAL

10%

6

108

6

76

6

76

76

76

76

76

6

6

108

6




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BLANK PAGE

IN

D

SG

D

SG

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

PG

THRMGND

NC

D

VCC

S

ON

PAD

IN

G

SD

D

GS

D

GS

D

GS

OUT

OUT




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8 7 5 4 2 1

60mA max load @ 0.75V45mW max power

LOW THROUGH VTT TERMINATION RESISTORS.

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWAREMUST GUARANTEE MEM_CKE SIGNALS ARE LOW

5V S0 FET 3.3V S0 FET 3.3V S3 FET

UNTIL AFTER RAIL TURNS BACK ON OR DIMMSWILL EXIT SELF-REFRESH PREMATURELY.MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

1.5V S0 FET

78 OF 110

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1

4

5

Q7850

1

4

5

Q7825

1

4

5

Q78003

2

1

4

5

Q7853

1

9

6

8

2

3

4

7

5

U7853

2

1 C7853

1

9

6

8

2

3

4

7

5

U7850

2

1 C7850

1

9

6

8

2

3

4

7

5

U7825

2

1 C7825

1

9

6

8

2

3

4

7

5

U7800

2

1 C7800

12

6Q7875

2

1C7876

2 1

R7875

2

1R7876

45

3Q7875

CRITICAL



PGOOD_1V5_S0

=PPDDR_S3_S0FET

P3V3S3_EN=P3V3S0_EN

=PP12V_S5_PWRCTL



PP1V5_S0_FET

P3V3_S0_EN

VTTCLAMP_EN

=PP5V_S3_VTTCLAMP

=PPVTT_S0_VTTCLAMP

DDRVTT_EN

VTTCLAMP_L

=PP12V_S5_PWRCTL

PP3V3_S0=PP3V3_S5_S0FET

=MCPDDR_EN

=PP12V_S5_PWRCTL

P5V_S0_EN

PP5V_S0

P1V5_S0_EN

=PP12V_S5_PWRCTL

P3V3_S3_EN

PP3V3_S3

=PP3V3_S5_S3FET

=P5VS0_EN

=PP5V_S3_S0FET

PGOOD_5V_S0

S3 & S0 FETsSYNC_DATE=N/ASYNC_MASTER=MASTER

70

70

CRITICAL

IRFH7914PBFPQFN

CRITICAL

IRFH7914PBFPQFN

PQFN

IRFH7914PBF

CRITICAL CRITICAL

POWER33FDMC8296

70

TDFNSLG5AP001

402

0.1UF10%

X5R16V

70

SLG5AP001TDFN

CRITICAL

402

0.1UF10%

X5R16V

SLG5AP001TDFN

CRITICAL

70

X5R

0.1UF10%

402

16V

70

CRITICAL

SLG5AP001TDFN

402

0.1UF10%

X5R16V

SOT563SSM6N15FEAPE

CERM50V20%

402

0.001UF

NO STUFF

603MF-LF1/10W5%

10

402

5%1/16WMF-LF

100K

SOT563SSM6N15FEAPE

75 9

54

6

78 70 38 6

6

6

78 70 38 6

6

6

78 70 38 6

110 6

78 70 38 6

110 6

6

6

THRM_PAD

PVINAVIN

PGMODE

OVT FB

AGND PGND

SWEN




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<Ra>

MAX Current = 0.55A

Vout = 1.1V

<Rb>

(ENABLED AT 2,8V MINIMUM)

MCP 1.1V_S5 AUXC SUPPLY

VOUT = 0.6V * (1 + Ra / Rb)

FREQ = 1Mhz

79 OF 110

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2

1 C7901

2

1 R7923

2

1 C79832

1R7980

2

1 R7981

21

L7920

2

1 C7982

2

1 C7920

2

1 R7922

2

1 C7981

11

1

10

2

8

5

7

4

6

93

U7950

BQA

CRITICAL

TPS62510

X5R

0.1UF10%16V

402

5%

MF-LF402

11/16W

805-3CERM-X5R6.3V20%22UF

402

50V5%CERM

22PF

CRITICAL

2.2UH-3.25AIHLP1616BZ-SM

402

1/16W1%

MF-LF

60.4K

402

1/16WMF-LF

1%51.1K

805-3CERM-X5R

20%6.3V

22UF

23.2K1%

MF-LF402

1/16W

NOSTUFF

0.1UF10%16VX5R402

1V1 S5 POWER SUPPLYSYNC_DATE=10/31/2008SYNC_MASTER=K51

PP1V1_S5_REG

1V1S5_FB

P1V1_S5_EN

PGOOD_1V1_S5


1V1S5_AVIN

=PP3V3_S5_P1V1S5

MIN_NECK_WIDTH=0.1MMSWITCHNODE1V1S5_SW

MIN_LINE_WIDTH=0.3MMDIDT=TRUE

6

70

6

VIN

GND

FBSWEN




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MAX CURRENT = 300MA

VOUT = 0.5 * (1 + RA/RB)

<RA)

<RB)

VOUT = 1.8V

MCP ONLY 1.8V_S0 POWER SUPPLY

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2

1C8025

2

1R8020

21

L8010

2

1C8015

2

1C8013

2

1C8014

2

1C8012

2

1R8011

2

1R8010

2

1 C8016

1

5

2

4

3

U8001

IG

PP1V8_S0_REG

20%

IG

DIDT=TRUE


1V8_SWSWITCHNODE


=PP5V_S3_1V8

1V8_FB

1V8S0_EN

=PP5V_S0_PWRCTL

1V8 POWER SUPPLYSYNC_MASTER=MASTER SYNC_DATE=N/A

6.3V

IG

402CERM

10%0.68UF

MF-LF402

1/16W1%

49.9K

IG

10UH-1.7A

IG

MSCDRI5D48-SM

CRITICAL

50V5%

402CERM

100PF

NOSTUFF

805

IG

10V

10UF20%

X5R

10UF

805X5R10V20%

33PF

402

NOSTUFF

CERM

5%50V

IG

1%1/16WMF-LF

402

18.2K

402

1/16W1%

47.5K

IG

MF-LF

10UF

X5R10V

805

SOT23-5-LF

CRITICAL

TPS62200

IG

6 108

6

6




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3V3

5V

PWR_SRC

(4 OF 4)

PCI-E

DP

(2 OF 4)

PEX_TX15*

DP_A_AUX*

PEX_TX1*

PEX_TX13

PEX_TX11*

PEX_TX7*

PEX_TX8*

PEX_TX9

PEX_TX10

PEX_STD_SW*

PEX_TX15

PEX_TX14*PEX_TX14

PEX_TX13*

PEX_TX12*

PEX_TX12

PEX_TX11

PEX_TX10*

PEX_TX9*PEX_TX8

PEX_TX7

PEX_TX6*PEX_TX6

PEX_TX5*PEX_TX5

PEX_TX4*PEX_TX4

PEX_TX3*PEX_TX3

PEX_TX2*PEX_TX2

PEX_TX1

PEX_TX0*PEX_TX0

PEX_REFCLK*PEX_REFCLK

PEX_RST*

DP_C_HPD

DP_D_HPD

DP_B_HPD

DP_A_HPD

PEX_RX15*PEX_RX15

PEX_RX14*PEX_RX14

PEX_RX13*PEX_RX13

PEX_RX12*

PEX_RX12

PEX_RX11*PEX_RX11

PEX_RX10*

PEX_RX10

PEX_RX9*PEX_RX9

PEX_RX8*

PEX_RX8

PEX_RX7*PEX_RX7

PEX_RX6*

PEX_RX6

PEX_RX5*PEX_RX5

PEX_RX4*PEX_RX4

PEX_RX3*PEX_RX3

PEX_RX2*PEX_RX2

PEX_RX1*PEX_RX1

PEX_RX0*PEX_RX0

CLK_REQ*

DP_C_L0*DP_C_L0

DP_C_L1*

DP_D_L0*

DP_C_L1

DP_D_L0

DP_C_L2*

DP_D_L1*

DP_C_L2

DP_D_L1

DP_C_L3*

DP_D_L2*

DP_C_L3

DP_D_L2

DP_D_L3*DP_D_L3

DP_B_L0*

DP_B_L0DP_B_L1*

DP_A_L0*

DP_B_L1

DP_A_L0

DP_B_L2*

DP_A_L1*

DP_B_L2

DP_A_L1

DP_B_L3*

DP_A_L2*

DP_B_L3

DP_A_L2DP_A_L3*

DP_A_L3

DP_C_AUX*DP_C_AUX

DP_D_AUX*

DP_D_AUX

DP_B_AUX*

DP_B_AUX

DP_A_AUX




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Page Notes


APPLE P/N: 516S0699


- =PP3V3_S0_MXM

PLATFORM DEPENDENT

(NOT NECESSARILY THE SAME FOR EVERY MODULE)MXM SPEC POWER REQUIREMENTS

VOLTAGE

PWR (7-20V)

- =PP5V_S0_MXM

(NONE)

12.5 W3.3 W

POWERCURRENT

UP TO 10 A

2.5 A1.0 A3V3

5V


- =PPV_S0_MXM_PWRSRC

- MXM

84 OF 110

051-7845

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8486

9092

9698

102104

108110

114116

120122

136

138

48

50

5456

60

62

6668

72

74

7880

142144

148

150

19

8587

9193

9799

103105

109111

115117

121123

135137

49

51

5557

61

63

6769

73

75

7981

141143

147

149

156

153

155

224226

218220

212

214

206208

236

230232

217219

211

213

205207

199

201

234

223225

264

266

258260

252254

246248

274

270272

271273

265267

259261

253255

276

277279

154

J8400

E2

E1

97531

280278

J8400

2

1 C8415

2

1 C84162

1R8400

2

1 C8414

2

1 C8413

2

1 C8412

2

1 C8410

2

1 C8401

2

1 C8400

MXM_PCIE_STD_SWING_L

MXM_RESET_L

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_N<11>

MXM_DP_A_ML_P<0>MXM_DP_A_ML_N<1>MXM_DP_A_ML_P<1>MXM_DP_A_ML_N<2>MXM_DP_A_ML_P<2>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<6>

MXM_PCIE_D2R_P<12>MXM_PCIE_D2R_N<12>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<15>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_P<11>



MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_N<1>MXM_PCIE_D2R_P<0>MXM_PCIE_D2R_N<0>

MXM_PCIE_R2D_N<2>MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<5>MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<8>

MXM_PCIE_R2D_N<1>


MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_R2D_N<11>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_P<13>



MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<13>

MXM_PCIE_R2D_N<12>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_N<0>

MXM_DP_C_AUX_P

MXM_DP_B_ML_N<0>

MXM_CLKREQ_L

MXM_DP_B_AUX_P

MXM_DP_B_HPD

MXM_DP_B_ML_P<0>

CLK_100M_MXM_NCLK_100M_MXM_P

MXM_DP_C_HPD

MXM_DP_D_HPD

MXM_DP_A_HPD

MXM_DP_C_ML_N<0>MXM_DP_C_ML_P<0>

MXM_DP_C_ML_N<1>

MXM_DP_D_ML_N<0>

MXM_DP_C_ML_P<1>

MXM_DP_D_ML_P<0>

MXM_DP_C_ML_N<2>

MXM_DP_D_ML_N<1>

MXM_DP_C_ML_P<2>

MXM_DP_D_ML_P<1>

MXM_DP_C_ML_N<3>

MXM_DP_D_ML_N<2>

MXM_DP_C_ML_P<3>

MXM_DP_D_ML_P<2>MXM_DP_D_ML_N<3>MXM_DP_D_ML_P<3>

MXM_DP_B_ML_N<1>

MXM_DP_A_ML_N<0>

MXM_DP_B_ML_P<1>

MXM_DP_B_ML_N<2>MXM_DP_B_ML_P<2>MXM_DP_B_ML_N<3>MXM_DP_B_ML_P<3>

MXM_DP_A_ML_N<3>MXM_DP_A_ML_P<3>

MXM_DP_C_AUX_N

MXM_DP_D_AUX_NMXM_DP_D_AUX_P

MXM_DP_B_AUX_N

=PP3V3_S0_MXM

MXM_DP_A_AUX_N

MXM_DP_A_AUX_P

=PPV_S0_MXM_PWRSRC

=PP3V3_S0_MXM

=PP5V_S0_MXM

MXM PCIe, DP & PowerSYNC_DATE=10/31/2008SYNC_MASTER=K51

B35P101-0121

MXM

F-RT-SM

CRITICAL

B35P101-0121

MXM

F-RT-SM 0.001UF50V

402X7R

10%

MXM

22UF20%6.3V

MXM

CERM-X5R805-3

MXM

MF-LF

5%1/16W

402

100K

0.001UF50V

402

10%

X7R

MXM

0.001UF50V10%

X7R402

MXM

0.001UF50V

402

10%

X7R

MXM

50V

402X7R

10%

MXM

0.001UF 22UF20%6.3V

MXM

CERM-X5R805-3

MXM

20%

6.3X5.5-SM1ELEC35V

22UF

85

87

102 86

102 86

102 86

102 86

107 91

107 91

107 91

107 91

107 91

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

102 86

87

87

87

87

87

87

87

87

87

91

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

87

107 91

87

87

87

87

87

107 91

107 91

87

87

87

87

85 84 6

107 93

107 93

53

85 84 6

6

WC*

SDA

SCL

E2/NC2E1/NC1E0/NC0

VSS

VCC

GPIO0

VGA_DISABLE*

TH_OVERT*TH_PWM

LVDS_DDC_CLK

LVDS_UTX1

LVDS_UTX2*

RSVD1

PNL_PWR_EN

LVDS_UTX1*

RSVD2

LVDS_UTX2

LVDS_UTX3*

LVDS_LCLK

PRSNT_R*

LVDS_LTX3

DVI_HPD

PWR_EN

SMB_CLK

LVDS_LTX0LVDS_LTX0*

LVDS_LTX1

LVDS_LTX2LVDS_LTX2*

LVDS_LTX3*

LVDS_UTX0

LVDS_UTX0*

LVDS_UTX3

PNL_BL_EN

PRSNT_L*

PWRGOOD

VGA_BLUEVGA_GREENVGA_HSYNCVGA_RED

VGA_VSYNC

VGA_DDC_DAT

GPIO1

GPIO2

HDMI_CEC

OEM0OEM1

OEM2OEM3OEM4OEM5

OEM7

VGA_DDC_CLK

RSVD3RSVD4RSVD5

RSVD7RSVD8RSVD9

RSVD10RSVD11RSVD12RSVD13

RSVD14RSVD15RSVD16RSVD17RSVD18

RSVD19

RSVD21

SMB_DAT

TH_ALERT*

LVDS_UCLK*

LVDS_UCLK

RSVD20

LVDS_LCLK*

LVDS_LTX1*

RSVD6

RSVD0

RSVD22

RSVD23

PWR_LEVEL

LVDS_DDC_DAT

PNL_BL_PWM

OEM6

WAKE*

SYSTEM MANAGEMENT

(1 OF 4)

LVDS

ANALOG DISPLAY

POWER/THERMAL

MANAGEMENT

GNDGND

(3 OF 4)




36

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REVISION

DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

FLOAT = LOW SWINGGND = HIGH SWING


- =PP3V3_S0_MXM

Page NotesPower aliases required by this page:

- =PM_MXM_PGOOD_PULLUP

STUFF FOR WRITE PROTECT


PULLED TO GROUND ON MXMWE DON’T USE CARD DETECT

PLACE CLOSE TO J7800

MXM SYSTEM INFORMATION ROM

OR ANOTHER OPEN-DRAIN PGOOD SIGNAL DEPENDING ON DESIRED BEHAVIORSYSTEM INTEGRATOR MUST ALIAS THIS EITHER TO A VOLTAGE RAIL,

I2C ADDRESS: AC

- =SMB_MXM_THRM_CLK- =SMB_MXM_THRM_DATA PULLUPS & PULLDOWNS AT MXM CONNECTOR

FLOAT = NORMAL VGA MODEGND = SECONDARY DISPLAY CARD

85 OF 110

051-7845

A.0.0


2 1

R8510

2 1

R8504

5352

283282

E4

275269268

263

47

262257256

251250E3244

228222221

46

216215

210209204203

198197192191

37

186185180179

174173166157152

151

36

146145

140139134133125

124119118

17

113

112107106101

10095948988

15

83827776

71706564

5958

1311

J8400

4

162168164170

21

158

160

172

2420

22

32

34

231229227

167165163161

1614249247

12

245243242241

240239238237

235233

15910

618

8

2

281

23

27

25

4544434241

403938

175

177

181183

187189

193195

169171

182184

188190

194196

200202

176178

3335

29

30282631

J8400

2 1

R8503

21

R8501

7

4

8

5

6

3

2

1

U8570

2

1 C8570

2

1R8570

21

R8500

MXM

NOSTUFF

0

5%

402

0

MF-LF

NOSTUFF

0

402

5%1/16WMF-LF

402CERM

20%10V

0.1UF

MXM

100K

1/16W5%402

MF-LF

M24C02-WMN6TPHFSO8

CRITICALMXM

100K

5%MF-LF 1/16W402

402

MF-LF 5%

10K

1/16W

B35P101-0121

MXM

F-RT-SM F-RT-SM

MXM

B35P101-0121

402

5%MF-LF 1/16W

1/16W

MXM I/OSYNC_DATE=10/31/2008SYNC_MASTER=K51

MXM_PCIE_STD_SWING_L

TP_MXM_VGA_GREENTP_MXM_VGA_HSYNC

MXM_PNL_BL_EN

=PP3V3_S0_MXM

MXM_DETECT_R

=PP3V3_S0_MXM

MXM_LVDS_A_DATA_N<0>

MXM_LVDS_A_DATA_P<0>

MXM_VGA_DISABLE_L

MXM_LVDS_DDC_CLK

MXM_ROM_WP

MXM_LVDS_DDC_DAT

MXM_DETECT_L

PM_MXM_ENPM_MXM_PGOODMXM_PWR_LEVEL

=SMB_MXM_THRM_SCL=SMB_MXM_THRM_SDA

MXM_ALERT_LMXM_OVERT_L

MXM_DETECT_LMXM_DETECT_R

TP_MXM_WAKE_L




MXM_LVDS_A_DATA_N<3>MXM_LVDS_A_DATA_P<3>

MXM_LVDS_B_CLK_PMXM_LVDS_B_CLK_N

MXM_LVDS_B_DATA_P<3>MXM_LVDS_B_DATA_N<3>

MXM_LVDS_B_DATA_N<2>



MXM_LVDS_B_DATA_P<2>

PM_MXM_PGOOD


TP_MXM_VGA_BLUE

TP_MXM_VGA_VSYNCTP_MXM_VGA_RED

TP_MXM_VGA_DDC_DATTP_MXM_VGA_DDC_CLK

TP_MXM_TH_PWM

MXM_LVDS_A_CLK_PMXM_LVDS_A_CLK_N

TP_MXM_DVI_HPD

MXM_LVDS_DDC_DAT

MXM_LVDS_DDC_CLK

TP_MXM_GPIO0

TP_MXM_GPIO1TP_MXM_GPIO2

TP_MXM_HDMI_CEC

=PM_MXM_PGOOD_PULLUP

MXM_PNL_PWR_EN

MXM_PNL_BL_PWM

MXM_VGA_DISABLE_L

84

85

89

6 84 85

85

6 84 85

89

89

85

85 89

85 89

9 85

70

70 85

50

52

52

50

50

9 85

85

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

70 85

89

89

89

85 89

85 89

70

89

89

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT




36

BRANCH

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

MXM RX CAPSMXM TX CAPS

86 OF 110

051-7845

A.0.0


21C8631

21C8629

21C8630

21C8627

21C8628

21C8626

21C8625

21C8624

21C8623

21C8621

21C8622

21C8619

21C8620

21C8617

21C8618

21C8616

21C8615

21C8614

21C8613

21C8612

21C8611

21C8610

21C8609

21C8608

21C8607

21C8606

21C8605

21C8603

21C8604

21C8601

21C8602

21C8600

21C8661

21C8659

21C8660

21C8663

21C8662

21C8658

21C865621C8657

21C8655

21C8654

21C865021C8651

21C8653

21C8652

21C8649

21C8648

21C8647

21C8646

21C8645

21C8644

21C8643

21C8642

21C864021C8641

21C8639

21C8638

21C8637

21C8636

21C863421C8635

21C8633

21C8632

MXM_PCIE_R2D_P<11>

MXM_PCIE_R2D_N<11>

MXM_PCIE_D2R_N<15>

PEG_D2R_N<0>

PEG_D2R_P<3>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_R2D_C_N<5>

MXM_PCIE_D2R_P<4>

MXM_PCIE_D2R_N<1>

MXM_PCIE_D2R_P<0>

MXM_PCIE_D2R_N<0>

MXM_PCIE_D2R_P<1>

MXM_PCIE_D2R_N<2>

MXM_PCIE_D2R_P<13>

MXM_PCIE_D2R_N<13>

MXM_PCIE_D2R_P<12>

MXM_PCIE_D2R_N<12>

MXM_PCIE_R2D_N<15>PEG_R2D_C_P<0>

MXM_PCIE_R2D_P<14>

PEG_R2D_C_N<2>

MXM_PCIE_R2D_P<12>

MXM_PCIE_R2D_N<14>

MXM_PCIE_R2D_N<10>

PEG_R2D_C_P<13>

PEG_R2D_C_N<14>

PEG_R2D_C_P<14>

PEG_R2D_C_N<15>

PEG_R2D_C_P<15>

MXM_PCIE_R2D_P<15>

MXM_PCIE_R2D_P<13>

MXM_PCIE_R2D_N<12>

PEG_R2D_C_P<4>

PEG_R2D_C_P<1>

MXM_PCIE_D2R_N<14>

MXM_PCIE_D2R_P<14>

MXM_PCIE_R2D_P<9>

MXM_PCIE_R2D_P<10>

PEG_R2D_C_P<10>

MXM_PCIE_R2D_P<5>

MXM_PCIE_R2D_P<8>

PEG_D2R_P<4>

PEG_R2D_C_P<12>

PEG_R2D_C_N<12>

PEG_R2D_C_N<13>

PEG_R2D_C_N<10>

PEG_R2D_C_N<11>

PEG_R2D_C_P<5>

PEG_R2D_C_N<6>

PEG_R2D_C_P<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_P<11>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_N<7>

MXM_PCIE_R2D_N<5>

MXM_PCIE_R2D_P<4>

MXM_PCIE_R2D_N<4>

MXM_PCIE_R2D_N<3>

MXM_PCIE_R2D_P<3>

MXM_PCIE_R2D_P<2>

MXM_PCIE_R2D_N<2>

MXM_PCIE_R2D_N<1>

MXM_PCIE_R2D_P<1>

MXM_PCIE_R2D_N<0>

MXM_PCIE_R2D_N<9>

MXM_PCIE_R2D_N<8>

MXM_PCIE_R2D_P<7>

MXM_PCIE_R2D_N<7>

MXM_PCIE_R2D_P<6>

MXM_PCIE_R2D_N<6>

MXM_PCIE_R2D_P<0>

MXM_PCIE_D2R_P<3>

MXM_PCIE_D2R_N<3>

MXM_PCIE_D2R_P<2>

MXM_PCIE_D2R_P<8>

MXM_PCIE_D2R_N<5>

MXM_PCIE_D2R_P<7>

MXM_PCIE_D2R_P<5>

MXM_PCIE_D2R_N<8>

MXM_PCIE_D2R_N<9>

MXM_PCIE_D2R_P<9>

MXM_PCIE_D2R_N<10>

MXM_PCIE_D2R_P<10>

MXM_PCIE_D2R_N<11>

MXM_PCIE_D2R_P<11>

PEG_D2R_P<7>

PEG_D2R_P<12>

PEG_D2R_P<6>

PEG_D2R_N<7>

PEG_D2R_P<10>

PEG_D2R_N<14>

PEG_D2R_N<4>

PEG_D2R_N<9>

PEG_D2R_P<9>

PEG_D2R_N<11>

PEG_D2R_N<13>

PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<11>

PEG_D2R_N<6>

PEG_D2R_N<2>

PEG_D2R_P<2>

MXM_PCIE_R2D_N<13>

PEG_D2R_N<3>

MXM_PCIE_D2R_N<4>

MXM_PCIE_D2R_P<15>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_P<0>

MXM_PCIE_D2R_N<7>

MXM_PCIE_D2R_N<6>

MXM_PCIE_D2R_P<6>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_R2D_C_N<0>

PEG_R2D_C_N<4>

PEG_R2D_C_P<3>

PEG_R2D_C_N<3>

PEG_R2D_C_P<2>

PEG_R2D_C_N<1>

MXM PCIE CAPSSYNC_MASTER=MASTER SYNC_DATE=N/A

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

16V 40210%0.1UF X5RMXM

102 84

102 84

102 84

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V X5R 40210%0.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

10% X5R 4020.1UF 16VMXM

16V10% 4020.1UF X5RMXM

16V X5R 4020.1UF 10%MXM

16V10% X5R0.1UF 402MXM

16V10% X5R0.1UF 402MXM

102 84

102 84

102 84

102 84

102 84

102 84

102 84

0.1UF 40210% 16V X5RMXM

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

0.1UF 40210% 16V X5RMXM

0.1UF 16V10% X5R 402MXM

0.1UF 16V10% X5R 402MXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

40216V10% X5R0.1UFMXM

0.1UF 16V10% X5R 402MXM

0.1UF 10% 16V 402X5RMXM

0.1UF 402X5R10% 16VMXM

402X5R10% 16V0.1UFMXM

0.1UF 402X5R10% 16VMXM

102 9

402X5R10% 16V0.1UFMXM

0.1UF 402X5R10% 16VMXM

0.1UF 40210% X5R16VMXM

0.1UF 16V 402X5R10%MXM

0.1UF 402X5R10% 16VMXM

0.1UF X5R10% 40216VMXM

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

0.1UF 402X5R10% 16VMXM

0.1UF 402X5R10% 16VMXM

0.1UF 402X5R10% 16VMXM

0.1UF 402X5R10% 16VMXM

102 9

402X5R10% 16V0.1UFMXM

0.1UF 402X5R10% 16VMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

0.1UF 402X5R10% 16VMXM

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

102 9

10%0.1UF X5R 40216VMXM

102 9

102 9

102 9

16V10% X5R 4020.1UFMXM

0.1UF 402X5R10% 16VMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

102 84

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

16V10% X5R 4020.1UFMXM

10% X5R0.1UF 40216VMXM

16V10% X5R 4020.1UFMXM

16V10% X5R0.1UF 402MXM

16V X5R 40210%0.1UFMXM

X5R 4020.1UF 10% 16VMXM

10% 16V0.1UF X5R 402MXM

10% 16V 4020.1UF X5RMXM

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84

102 84 10% 4020.1UF X5R16VMXM102 9

102 9

102 84

102 9

102 9

102 9

0.1UF 402X5R10% 16VMXM

10%0.1UF X5R 40216VMXM

0.1UF 16V X5R10% 402MXM

402X5R10% 16V0.1UFMXM

40216V0.1UF X5R10%MXM

102 84

102 84

10% X5R0.1UF 40216VMXM

102 9




36

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SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

(NONE)

Page Notes

(NONE)

- =PP5V_DP_AUX




UNUSED DP INTERFACESMCP CONNECTIONS

87 OF 110

051-7845

A.0.0


MXM_DP_C_HPD

MXM_DP_C_ML_P<0..3>

MAKE_BASE=TRUENC_MXM_DP_C_AUX_N

NO_TEST=TRUE

MAKE_BASE=TRUENC_MXM_DP_C_ML_N<0..3>

NO_TEST=TRUE

NC_MXM_DP_C_ML_P<0..3>MAKE_BASE=TRUENO_TEST=TRUE

MAKE_BASE=TRUENC_MXM_DP_C_AUX_P

NO_TEST=TRUE

MXM_DP_C_AUX_N

MXM_DP_C_ML_N<0..3>

MAKE_BASE=TRUETP_MXM_DP_C_HPD

MXM_DP_C_AUX_P


NC_MXM_DP_B_ML_N<0..3>MXM_DP_B_ML_N<0..3>


NC_MXM_DP_B_AUX_NMXM_DP_B_AUX_N


NC_MXM_DP_B_ML_P<0..3>MXM_DP_B_ML_P<0..3>


NC_MXM_DP_B_AUX_PMXM_DP_B_AUX_P

MAKE_BASE=TRUETP_MXM_DP_B_HPDMXM_DP_B_HPD

NC_MXM_DP_D_ML_N<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

MXM_DP_D_ML_N<0..3>

NC_MXM_DP_D_ML_P<0..3>NO_TEST=TRUEMAKE_BASE=TRUE

MXM_DP_D_ML_P<0..3>

NC_MXM_DP_D_AUX_NNO_TEST=TRUEMAKE_BASE=TRUE

MXM_DP_D_AUX_N

NC_MXM_DP_D_AUX_PNO_TEST=TRUEMAKE_BASE=TRUE

MXM_DP_D_AUX_P

TP_MXM_DP_D_HPDMAKE_BASE=TRUE

MXM_DP_D_HPD

MAKE_BASE=TRUEGPU_CLK100M_PCIE_PCLK_100M_MXM_P

MAKE_BASE=TRUEGPU_CLK100M_PCIE_NCLK_100M_MXM_N

PEG_RESET_LMAKE_BASE=TRUE

MXM_RESET_L

MXM ALIASESSYNC_MASTER=MASTER SYNC_DATE=N/A

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

102 9 84

102 9 84

90 9 84




36

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DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

88 OF 110

051-7845

A.0.0



BLANK PAGE

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1

SYM_VER-1




36

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DRAWING NUMBER SIZE

DR


SHEET

PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1

PLACE CHOKES CLOSE TO J9002SHARE 0-OHM RES WITH CHOKE PADS

IG pullups always stuffed to prevent floating inputsIN MXM CONFIG, PULL-UPS ON CARD

WE WILL ROUTE FROM MCP TO THE 0-OHM RESISTORS, THEN ON THROUGH MXM TO THE LCD CONNECTOR

THESE RESISTOR OPTIONS SELECT BETWEEN MCP AND MXM TO DRIVE THE INTERNAL DISPLAY

IG-ONLY O-OHM RESISTORS NEED TO BE PLACED AT THE MXM CONNECTOR TO AVOID STUBS

IF THIS ROUTING IS NOT FEASIBLE, MXM ALIASES WILL BE REPLACED WITH ADDITIONAL 0-OHM RESISTORS

89 OF 110

051-7845

A.0.0


3

4

2

1

RP8954

3

4

2

1

RP8953

3

4

2

1

RP8952

3

4

2

1

RP8951

4 3

21

L8954

21

R8957

4 3

21

L8953

21

R8956

21

R8955

4 3

21

L8952

21

R8954

21

R8953

4 3

21

L8951

3

4

2

1

RP8950

21

R8951

21

R8952

4 3

21

L8950

21

R8950

21

R8907

4 3

21

L8903

21

R8906

21

R8905

4 3

21

L8902

21

R8904

4 3

21

L8901

21

R8903

21

R8902

21

R8900

21

R8901

4 3

21

L8900

2

1R8933

2

1R8931

21

R8932

21

R8930

2

1R8923

21

R8922

2

1R8921

21

R8920

3

4

2

1

RP8903

3

4

2

1

RP8902

3

4

2

1

RP8901

4 3

21

L8904

3

4

2

1

RP89802

1R8980

2

1R8981

3

4

2

1

RP8904

3

4

2

1

RP8900

LCD_CONN_A_DATA_P<1>

LVDS_IG_B_DATA_P<2>

LVDS_B_DATA_N<3>MAKE_BASE=TRUE

LCD_CONN_B_CLK_P

=PP3V3_S0_VIDEO

LVDS_IG_DDC_CLKLVDS_IG_DDC_DATA

MXM_LVDS_DDC_CLK

LVDS_IG_BKL_PWM

LCD_BKL_ONMAKE_BASE=TRUE

LCD_CONN_B_DATA_P<3>

LVDS_IG_B_DATA_P<0>


LVDS_IG_B_DATA_N<1>



LVDS_IG_B_CLK_PLVDS_IG_B_CLK_N

MXM_LVDS_B_CLK_PMXM_LVDS_B_CLK_N

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>



LVDS_IG_B_DATA_N<2>


LVDS_IG_B_DATA_P<1>

LVDS_B_CLK_NMAKE_BASE=TRUE

LVDS_B_CLK_PMAKE_BASE=TRUE

LCD_CONN_B_CLK_N

LVDS_B_DATA_P<3>MAKE_BASE=TRUE LCD_CONN_B_DATA_N<3>

LCD_CONN_B_DATA_N<2>LVDS_B_DATA_P<2>MAKE_BASE=TRUE



LCD_CONN_B_DATA_N<1>LCD_CONN_B_DATA_P<1>LVDS_B_DATA_P<1>

MAKE_BASE=TRUE

MXM_LVDS_B_DATA_N<1>MXM_LVDS_B_DATA_P<1>

LVDS_IG_B_DATA_N<0>



LVDS_B_DATA_P<0>MAKE_BASE=TRUE LCD_CONN_B_DATA_N<0>

LCD_CONN_B_DATA_P<0>LCD_CONN_A_DATA_P<0>LCD_CONN_A_DATA_N<0>

LVDS_A_DATA_P<0>MAKE_BASE=TRUELVDS_A_DATA_N<0>MAKE_BASE=TRUE


MXM_LVDS_A_DATA_P<0>MXM_LVDS_A_DATA_N<0>


MXM_LVDS_A_DATA_P<1>MXM_LVDS_A_DATA_N<1>

LCD_CONN_A_DATA_N<1>

LCD_CONN_A_DATA_P<2>LCD_CONN_A_DATA_N<2>





LCD_CONN_A_CLK_P

LCD_CONN_A_CLK_N

LVDS_A_CLK_PMAKE_BASE=TRUELVDS_A_CLK_NMAKE_BASE=TRUE







LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_P<3>

MXM_LVDS_A_CLK_NMXM_LVDS_A_CLK_P

LVDS_IG_A_CLK_NLVDS_IG_A_CLK_P

MXM_LVDS_DDC_DAT

MAKE_BASE=TRUELCD_CONN_DDC_DATMAKE_BASE=TRUELCD_CONN_DDC_CLK

MXM_PNL_BL_EN

MXM_PNL_BL_PWM

LVDS_IG_BKL_ON

LCD_PANEL_PWRMAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MXM_PNL_PWR_EN

LCD_BKL_PWMMAKE_BASE=TRUE

LCD MUX & CHOKESSYNC_MASTER=MASTER SYNC_DATE=MASTER

DLP0NS90-OHM

NOSTUFF

0

1/16W5%402 MF-LF

0

1/16W5%402 MF-LF

NOSTUFF90-OHMDLP0NS

MF-LF402 5%1/16W

0

DLP0NS90-OHM

NOSTUFF

MF-LF402 5%1/16W

0

0

1/16W5%402 MF-LF

MF-LF402 5%1/16W

0

0

1/16W5%402 MF-LF

NOSTUFF90-OHMDLP0NS

10K5%

MF-LF1/16W

402

NOSTUFF

402

1K5%

MF-LF1/16W

IG

1/16W5%

0

MF-LF

MXM

402

402MF-LF

5%

0

1/16W

IG

1K

IG

MF-LF402

5%1/16W

402

5%

MF-LF1/16W

IG

0

1K

IG

MF-LF402

5%1/16W

402

5%

MF-LF1/16W

IG

0

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

CRITICAL

DLP0NS90-OHM

SM-LF

5%

0

1/16W

IG

2.7K

402MF-LF1/16W

5%MF-LF

402

2.7K1/16W

5%

1/16W

0

5%

IG

SM-LF1/16W

0

5%

IG

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

1/16W

0

IG

5%

SM-LF

CRITICAL

DLP0NS90-OHM

MF-LF402 5%1/16W

0

DLP0NS90-OHM

NOSTUFF

0

1/16W5%402 MF-LF

0

1/16W5%402 MF-LF

NOSTUFF90-OHMDLP0NS

MF-LF402 5%1/16W

0

MF-LF402 5%1/16W

0

DLP0NS90-OHM

NOSTUFF

1/16W

IG

5%

SM-LF

0

1/16W

IG

5%

SM-LF

0

0

1/16W5%402 MF-LF

0

1/16W5%402 MF-LF

NOSTUFF90-OHMDLP0NS

MF-LF402 5%1/16W

0

MF-LF402 5%1/16W

0

107 90

107 18

107

107 90

90 6

18

18

85

18

90 6

107 90

107 18

85

107 18

107

85

107 18

107 18

85

85

107 18

107 18

85

85

107 18

85

107 18

107

107

107 90

107

107 90

107 90

107 107 90

107 107 90

107 90 107

85

85

107 18

85

107

107

107 90

107 90 107 90

107 90

107

107

107

107

85

85

107 18

107 18

85

85

107 90

107 90

107 90

107 90

107 90

107

107

107

107

107 90

107 90

107

107

85

107 18

107 18

85

107 18

107 18

85

85

107 18

107 18

85

85

107 18

107 18

85

90

90

85

85

18

90 18

85

90

Y

B

A

Y

B

A

GND

GND

G S

D




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518S0685

INTERNAL LCD INTERFACE


IG, MXM

(NONE)

- =PP3V3_S0_VIDEO- =PP12V_S0_LCD


Page Notes


PANEL POWER CONTROL

IF NOT BYPASSED, THIS CAN BE USED TO FORCE THE USE OF THE BACKLIGHT ENABLE SIGNAL EVEN IF THE INVERTER DOES NOT TAKE THIS AS AN INPUT

IT MAY BE BYPASSED IF THE PWM SOURCE IS THE MXM

BACKLIGHT CONTROL SUPPORT

PLACE NEAR J9002

THIS AND GATE CIRCUIT PROVIDES BACKLIGHT GLITCH PREVENTION WHEN MCP GLITCHES GPIOS ON POWERUP

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9

8

7

6

5

4

34

33

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J9002

2

1C9010

4

3

6

5

2

1

Q9000

4

5

3

1

2

U9021

2

1 C9051

2

1 C9050

21

L9050

21

R9080

4

5

3

1

2

U9020 21

R9081

2

1R9000

21

R900121

C9000 21

L9000

2

1C9020

2

1C9001

2

1R90702

1

3

Q9001


PP5V_LCD_CONNVOLTAGE=5V =PP3V3_S0_VIDEO

LCD_CONN_DDC_DAT

LCD_CONN_A_DATA_N<3>LCD_CONN_A_DATA_P<3>LCD_CONN_B_DATA_N<0>LCD_CONN_B_DATA_P<0>

LCD_CONN_B_DATA_N<1>LCD_CONN_B_DATA_P<1>

LCD_CONN_B_DATA_N<2>

LCD_CONN_A_CLK_N


LCD_CONN_A_DATA_P<0>LCD_CONN_A_DATA_N<1>


LCD_CONN_A_CLK_P



LCD_CONN_B_DATA_P<2>LCD_CONN_B_CLK_NLCD_CONN_B_CLK_PLCD_CONN_B_DATA_N<3>

LCD_CONN_DDC_CLK


LCD_BKL_ON

LCD_PWM_GATE1

PEG_RESET_L


PP5V_LCDVOLTAGE=5V

=PP5V_S0_LCD

LCD_PANEL_PWR

LCD_PWM_FILT LCD_PWM

LCD_PANEL_PWR_L

LCD_PWM_R

=PP3V3_S0_VIDEO

LCD_BKL_PWM

LCD_PANEL_PWR_L_RC

SYNC_DATE=MASTERSYNC_MASTER=MASTER

INTERNAL DISPLAY

1/16W5%

100K

MF-LF402

SOT23-HF12N7002

1/16W

402

5%

MF-LF

100K

MF-LF

29.4K

1/16W

402

1%

X7R603-1

50V

0.1UF

10%

SM

FERR-250-OHM

10%16V

10UF

0805X5R-CERM

50VCERM

0.001uF20%

402

CRITICAL

F-RT-SM20389-Y30E-01

0.001uF

402CERM50V20%

MLB_PNL_PWR

SM

CRITICAL

FDC638P_G

SOT665

IG

TC7SZ08AFEAPE

IG

CERM

0.1UF20%10V

402 402

0.1UF

10VCERM

IG

20%

FERR-250-OHM

CRITICAL

SM

1/16WMF-LF402

0

MXM

5%

TC7SZ08AFEAPESOT665

IG

5%1/16WMF-LF

47

402

6

90 89 6

89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

107 89

89

107 89

89 6

87 9

6

89

6

90 89 6

89




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MAY SHARE THE COMMON PAD BETWEEN R9125 AND R9130

K50 NOTE: PLACE THESE CAPACITORS ATLEAST 1INCH AWAY FROM DP CONNECTOR

DCOX: PLACE AT MXM CONNECTOR IF THERE IS ROOM

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21 C9114

21 C9164

21 C9112

21 C9162

21 C9110

21 C9160

21 C9158

21 C9108

21 C9156

21 C9106

21 C9154

21 C9104

21 C9152

21 C9102

21 C9150

21 C9100

21

R9130

21

R9125

21

R9124MXM_DP_A_HPD

MXM_DP_A_ML_P<3>

MXM_DP_A_ML_P<2>

DP_IG_ML_P<2>

MXM_DP_A_ML_N<3>

DP_IG_ML_P<3>

DP_IG_ML_N<3>

MXM_DP_A_ML_P<1>

MXM_DP_A_ML_N<2>

DP_IG_ML_N<2>

MXM_DP_A_ML_N<1>

DP_IG_ML_P<1>

DP_IG_ML_N<1>

DP_IG_ML_N<0>

MXM_DP_A_ML_N<0>

DP_IG_ML_P<0>

MXM_DP_A_ML_P<0>

DP_IG_HPD

DP_HPD

DP_ML_P<3>

DP_ML_N<3>

DP_ML_P<2>

DP_ML_N<2>

DP_ML_P<1>

DP_ML_N<1>

DP_ML_P<0>

DP_ML_N<0>


DP MUX SUPPORT

X5R40210%16V

0.1UF MXM

IG0.1UFX5R40210%16V

X5R40210%16V

0.1UF MXM

IG0.1UFX5R40210%16V

X5R40210%16V

0.1UF MXM

IG0.1UFX5R40210%16V

X5R40210%16V

0.1UF MXM

IG0.1UFX5R40210%16V

MXM0.1UF16V 10% 402 X5R

16V 10% 402 X5R

0.1UF IG

MXM0.1UF16V 10% 402 X5R

16V 10% 402 X5R

0.1UF IG

MXM0.1UF16V 10% 402 X5R

16V 10% 402 X5R

0.1UF IG

MXM0.1UF16V 10% 402 X5R

16V 10% 402 X5R

0.1UF IG

20.0K

402MF-LF1/16W1%

MXM

MF-LF

0

402

5%1/16W

IG

402

MXM

1/16W

05%

MF-LF

84

107 84

107 84

107 9

107 84

107 9

107 9

107 84

107 84

107 9

107 84

107 9

107 9

107 9

107 84

107 9

107 84

9

94

107 94

107 94

107 94

107 94

107 94

107 94

107 94

107 94




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BLANK PAGE

BI

BI

BI

BI

BI BI

BI

D

G S

IN

OUT

DSG

D SG

D

G S

IN

DSG

DSG




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TO DP CONNECTOR

STUFF FOR IG SYSTEMS

STUFF FOR MXM SYSTEMS

FOR IG SYSTEMS, Q9300 SWITCHES BETWEEN AC COUPLED AUX

AND DC-COUPLED DDC

THE CARD IS RESPONSIBLE FOR SWITCHING DDC SIGNALS ONTO THE AUX PAIR

FOR MXM, Q9350 BYPASSES THE AC COUPLING CAPS

MXM/IG MUX AND AUX/DDC SWITCHING

TO MCP

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2

1R9303

21

R9300

12

6

Q9300

21

C9300

21

C9301

45

3

Q9300

21

R9301

2

1R9352

21

3

Q9351

45

3

Q9350

21

C9351

12

6

Q9350

21

C9350

21

3

Q9301

2

1R9302

DDC_CA_DET_LS5V_L

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

DDC_CA_DET_LS5V

DP_AUX_CH_C_N

DP_AUX_CH_C_P

MXM_DP_A_AUX_P

MXM_DP_A_AUX_N

DP_CA_DETMAKE_BASE=TRUE

=PP5V_S0_DP_AUX_MUX

=PP5V_S0_DP_AUX_MUX

DP_AUXCH_SW_P

DP_AUXCH_SW_N

DP_IG_CA_DET

DISPLAYPORT SUPPORTSYNC_MASTER=MASTER SYNC_DATE=N/A

SSM6N15FEAPESOT563

IGIG

0.1UF

X5R

10%

402

16V

X5R16V

402

10%

0.1UF

IG

IG SSM6N15FEAPESOT563

9

IG

5%1/16W

33

402

SIGNAL_MODEL=EMPTY

MF-LF

402

100K

MF-LF

5%1/16W

MXM

SSM3K15FVSOD-VESM-HF

MXM

SSM6N15FEAPESOT563

MXM

0.1UF

X5R

10%

402

16V

MXM

SOT563SSM6N15FEAPEMXM

MXM

0.1UF

10%16VX5R402

100K

402MF-LF

5%1/16W

18

94

SSM3K15FVSOD-VESM-HF

107 94

107 94 107 18

107 18

9

107 84

107 84

MF-LF1/16W5%1K

IG

402

MF-LF

SIGNAL_MODEL=EMPTY

402

33

1/16W5%

IG

93 6

93 6

107

107

IN

OC*

OUT

ENGND

IN

IN

ML_LANE2PML_LANE2NRETURN

GNDML_LANE1N

ML_LANE0NGNDML_LANE1P

ML_LANE0P

GND

AUX_CHPAUX_CHNDP_PWR

GND

ML_LANE3N

ML_LANE3PGND

HPDCONFIG1CONFIG2

SHIELD PINS

IN

IN

IN

IONC NC

IO

GND

OUT

IO

NC NC

IO

GND

IONC NC

IO

GND

IONC NC

IO

GND

IN

IN

IN

IN

G

SD

G

SD

G

D

S

G

D

S

OUT

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2




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APPLE PART NO 514-0686

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19

10

12

15

17

9

11

3

5

22

21

2

1413

87

1

20

6

4

16

18

J9400

2

1 C94852

1 C9481

2

1 C94801

3

5

2

4

U9400

4

3 2

1

FL9403

4

3 2

1

FL9402

4

3 2

1

FL9401

4

3 2

1

FL9400

2

1R9423

1

2

6

Q9441

4

5

3

Q9441

2

1R9445

2

1R9444

4

5

3

Q9440

2

1R9422

2

1R9442

1

2

6

Q9440

21

L9400

2

1 C9400

109

12

3

D9411

2

1R9425

76

45

3

D9411

52

6

43

1

D9400

109

12

3

D9410

2

1R9420

76

45

3

D9410

2

1R9421

2

1R9443

PP3V3_S0_DPPWRMIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 MM

DP_CA_DET_Q

DP_ML_CONN_N<1>DP_ML_CONN_P<1>

DP_HPD_Q

DP_ML_CONN_P<0>DP_ML_CONN_N<0> HDMI_CEC

DP_ML_CONN_N<3>

DP_AUX_CH_C_N

DP_ML_CONN_P<2>

DP_ML_CONN_N<2>

DP_AUX_CH_C_P

DP_ML_CONN_P<3>

DP_ML_N<0>

DP_ML_P<2>

=PP3V3_S0_DPCONN

DP_CA_DET_L_Q

DP_CA_DET

DP_HPD_L_Q

DP_HPD

=PP3V3_S0_DPCONN

DP_ML_N<1>

DP_ML_P<0>

DP_ML_N<2>


MIN_LINE_WIDTH=0.38 MMPP3V3_S0_DPFUSE

=PP3V3_S0_DPCONN

TP_DP_OC

=PP3V3_S0_DPCONN

PM_SLPS3_BUF1_L

DP_ML_P<1>DP_ML_P<3>DP_ML_N<3>

DisplayPort ConnectorSYNC_MASTER=MASTER SYNC_DATE=N/A

TCM1210-4SM12-OHM-100MA

TCM1210-4SM12-OHM-100MA



5%

402

1/16WMF-LF

100K

91

SOT-3632N7002DW-X-G

SOT-3632N7002DW-X-G

402MF-LF1/16W

5%10K

10K

1/16W

402

5%

MF-LF

2N7002DW-X-GSOT-363

MF-LF

5%1/16W

402

1M

100K

1/16W1%

402MF-LF

SOT-3632N7002DW-X-G

107 91

107 91

MF-LF402

1%1/16W

100K

SM-1

400-OHM-EMI

603

20%0.01UF50VCERM

107 91

107 91

SLP2510P8RCLAMP0524P

CRITICAL

MF-LF

1M

402

1/16W5%

RCLAMP0524P

CRITICAL

SLP2510P8

SC70-6-1

CRITICAL

RCLAMP0504F

RCLAMP0524PSLP2510P8

CRITICAL

100K5%

1/16W

402MF-LF

93

SLP2510P8RCLAMP0524P

CRITICAL

100K

402MF-LF1/16W

5%

107 91

107 91

107 91

CRITICAL

MDP-K22F-ANG-TH1

73 9

6.3V

CRITICAL

X5R603

10UF20%

107 91

402

10VCERM

20%0.1UF

20%10UF

603X5R6.3V

CRITICAL

TPS2051BSOT23

107

107

107

107

107

107 93

107

107

107 93

107

94 6

94 6

94 6

94 6




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MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM


LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM







TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM





























FSB 1X Signals

Group 1

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

CPU Signal Constraints

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

Group 0

Group 0

Group 1

Group 3

Group 2

FSB 4X Signal Groups

FSB (Front-Side Bus) Constraints

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

Signals within each 4x group should be matched within 5 ps of strobe.DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 90 ps. (Tighther than MCP79)

All 4x FSB signals with impedance requirements are 42-ohm single-ended.

FSB 2X signals / groups shown in signal table on right.Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

FSB 1X signals shown in signal table on right.Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

Intel Design Guide recommends FSB signals be routed only on internal layers.

FSB 4X signals / groups shown in signal table on right.

All 2x/1x/Async FSB signals with impedance requirements are 50-ohm single-ended.

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET PHYSICAL

FSB Clock Constraints

MCP FSB COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5


FSB 2X

Signals

NET_TYPE

SPACING

Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MOST CPU SIGNALS WITH IMPEDANCE REQUIREMENTS ARE 50-OHM SINGLE-ENDED.

SR DG recommends at least 25 mils, >50 mils preferred

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XDP_CPURST_LCPU_ITPCPU_50S

CPU_27P4S CPU_VCCSENSE VR_CPU_VSNS_R_P

CPU_27P4S CPU_VCCSENSE VR_CPU_VSNS_R_N

CPU_50S CPU_ITP CPU_XDP_BPMB<3..0>CPU_ITPCPU_50S CPU_XDP_BPM_L<5..0>CPU_ITPCPU_50S CPU_XDP_TRST_LCPU_ITPCPU_50S CPU_XDP_TCK

CPU_50S CPU_ITP CPU_XDP_TMSCPU_ITPCPU_50S CPU_XDP_TDO

CPU_50S CPU_ITP CPU_XDP_TDICPU_COMP<0>CPU_COMPCPU_27P4S

CPU_FERR_LCPU_50S CPU_8MIL

CPU_AGTL CPU_A20M_LCPU_50S

FSB_1X FSB_LOCK_LFSB_50S

FSB_1X FSB_HIT_LFSB_50S

FSB_1X FSB_DEFER_LFSB_50S

CLK_FSB FSB_CLK_CPU_PCLK_FSB_100D

CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N

CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N

FSB_DSTB_42S FSB_DSTB_L_P<1>FSB_DSTB

FSB_DSTB_42S FSB_DSTB FSB_DSTB_L_N<2>

FSB_1XFSB_50S FSB_BREQ1_L

FSB_1X FSB_DBSY_LFSB_50S

FSB_DRDY_LFSB_50S FSB_1X

CPU_AGTLCPU_50S CPU_IERR_L

CLK_FSB_100D CLK_FSB FSB_CLK_ITP_P

CLK_FSBCLK_FSB_100D FSB_CLK_MCP_NFSB_CLK_MCP_PCLK_FSB_100D CLK_FSB

MCP_50S MCP_CPU_COMP_GNDMCP_FSB_COMP

CPU_AGTL CPU_DPRSTP_LCPU_50S

CPU_AGTLCPU_50S CPU_DPSLP_LCPU_50S CPU_AGTL FSB_CPUSLP_L

CPU_8MILCPU_50S PM_THRMTRIP_L

FSB_50S FSB_CPURST_LFSB_1X

FSB_1X FSB_RS_L<2..0>FSB_50S

FSB_1X FSB_TRDY_LFSB_50S

FSB_50S FSB_ADSTB_L<0>FSB_ADSTB

FSB_ADDRFSB_50S FSB_REQ_L<4..0>FSB_ADDRFSB_50S FSB_A_L<16..3>

FSB_1XFSB_50S FSB_ADS_L

FSB_DSTB_L_P<2>FSB_DSTB_42S FSB_DSTB

FSB_DATA FSB_DINV_L<2>FSB_42S

FSB_DSTBFSB_DSTB_42S FSB_DSTB_L_N<3>

CPU_AGTLCPU_50S CPU_STPCLK_L

MCP_50S MCP_BCLK_VML_COMP_VDDMCP_FSB_COMP

CPU_AGTLCPU_50S CPU_SMI_L

MCP_BCLK_VML_COMP_GNDMCP_FSB_COMPMCP_50S

CPU_50S CPU_AGTL CPU_PWRGDCPU_AGTL CPU_PROCHOT_LCPU_50S

CPU_BSEL<2..0>CPU_AGTLCPU_50S

FSB_1XFSB_50S FSB_BREQ0_L

FSB_DSTBFSB_DSTB_42S FSB_DSTB_L_P<3>FSB_42S FSB_DATA FSB_DINV_L<3>FSB_42S FSB_DATA FSB_D_L<63..48>

FSB_42S FSB_DATA FSB_D_L<47..32>

FSB_DATAFSB_42S FSB_D_L<15..0>

FSB_DSTB_42S FSB_DSTB FSB_DSTB_L_P<0>FSB_DATAFSB_42S FSB_DINV_L<0>

FSB_1XFSB_50S FSB_BPRI_L

FSB_1X FSB_HITM_LFSB_50S

CPU_AGTL CPU_INIT_LCPU_50S

CPU_IGNNE_LCPU_50S CPU_AGTL

CPU_AGTL CPU_INTRCPU_50S

MCP_50S MCP_CPU_COMP_VCCMCP_FSB_COMP

CPU_AGTL CPU_NMICPU_50S

FSB_50S FSB_ADDR FSB_A_L<35..17>

FSB_50S FSB_ADSTB FSB_ADSTB_L<1>


FSB_42S FSB_D_L<31..16>FSB_DATA

FSB_42S FSB_DATA FSB_DINV_L<1>

FSB_1XFSB_50S FSB_BNR_L


CPU_GTLREF0CPU_GTLREFCPU_50S

CPU_GTLREF1CPU_GTLREFCPU_50S

CPU_COMP<8>CPU_COMPCPU_27P4S

CPU_COMP CPU_COMP<2>CPU_27P4S


CPU_50S CPU_VID<7..0>CPU_8MIL

CPU_27P4S CPU_VCCSENSE CPU_VCC_PKG_SENSE_NCPU_VCCSENSECPU_27P4S CPU_VCC_PKG_SENSE_P



CPU/FSB Constraints

=50_OHM_SE =STANDARD* =STANDARDCPU_50S =50_OHM_SE =50_OHM_SE=50_OHM_SE

=27P4_OHM_SE 0.175 MM0.175 MM=27P4_OHM_SE*CPU_27P4S =27P4_OHM_SE=27P4_OHM_SE

=STANDARDCPU_AGTL ?*

0.2 MM*CPU_8MIL ?

0.6 MM ?CPU_COMP *

=4x_DIELECTRIC ?CLK_FSB TOP,BOTTOM

=3x_DIELECTRICTOP,BOTTOM ?FSB_1X

=4x_DIELECTRIC ?TOP,BOTTOMFSB_ADSTB

TOP,BOTTOM =3x_DIELECTRICFSB_ADDR ?

TOP,BOTTOMFSB_DSTB =5x_DIELECTRIC ?=3x_DIELECTRIC*FSB_DSTB ?

=2x_DIELECTRIC ?*FSB_DATA

FSB_1X =STANDARD* ?

=42_OHM_SE =1:1_DIFFPAIR* =1:1_DIFFPAIRFSB_DSTB_42S =42_OHM_SE =42_OHM_SE =42_OHM_SE

TOP,BOTTOM =4x_DIELECTRICFSB_DATA ?

=2x_DIELECTRIC ?*FSB_ADSTB

=3x_DIELECTRIC ?CLK_FSB *

=42_OHM_SE =42_OHM_SE=42_OHM_SE =42_OHM_SEFSB_42S =STANDARD =STANDARD*

=50_OHM_SE =50_OHM_SE =STANDARDFSB_50S =50_OHM_SE =50_OHM_SE =STANDARD*

=2x_DIELECTRICTOP,BOTTOMCPU_AGTL ?

0.2 MM ?*MCP_FSB_COMP

=STANDARD ?FSB_ADDR *

0.6 MMCPU_GTLREF * ?

=2:1_SPACINGCPU_ITP * ?

* 0.6 MM ?CPU_VCCSENSE

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF*CLK_FSB_100D =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

=50_OHM_SE =50_OHM_SE=50_OHM_SEMCP_50S * =STANDARD =STANDARD=50_OHM_SE

13

71

71

13 11

13 11

13 11

13 11

13 11

13 11

13 11

11

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 13

14 10

14 10

14

14 10

14 10

10

14 13

14

14

14

14 11

14 11

14 11

50 14 11

14 13 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14

14 10

14

14 13 11

50 14 11

14 11

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14

14 10

14 10

14 10

14 10

14 10

14 10

14 10

14 10

29 11 10

29 11 10

11

11

11

71 12

71 12

71 12

11




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TABLE_SPACING_ASSIGNMENT_ITEM







AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD















































Memory Net Properties

Memory Net PropertiesNET_TYPE

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SETNeed to support MEM_*-style wildcards!

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

SPACINGPHYSICAL

DDR2:

DDR3:

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.No DQS to clock matching requirement.

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.All DQS pairs should be matched within 100 ps of clocks.

A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Constraints

DQ signals should be matched within 20 ps of associated DQS pair.DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

MCP MEM COMP Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair.

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MEM_DQS MEM_A_DQS_N<1>MEM_70D

MEM_B_DQS_P<1>MEM_70D MEM_DQS

MEM_B_DQS_N<3>MEM_70D MEM_DQS

MEM_40S_VDD MEM_CTRL MEM_B_ODT<3..0>MEM_40S_VDD MEM_CTRL MEM_B_CS_L<3..0>MEM_40S_VDD MEM_CTRL MEM_B_CKE<3..0>

MEM_40S_VDD MEM_CMD MEM_B_WE_LMEM_40S_VDD MEM_CMD MEM_B_CAS_L

MEM_B_BA<2..0>MEM_40S_VDD MEM_CMD

MEM_40S_VDD MEM_CMD MEM_B_RAS_L

MEM_40S_VDD MEM_CMD MEM_B_A<14..0>

MEM_DATAMEM_40S MEM_B_DM<1>MEM_B_DQ<15..8>MEM_DATAMEM_40S

MEM_B_DM<0>MEM_40S MEM_DATA

MEM_DATAMEM_40S MEM_B_DQ<7..0>

MEM_40S MEM_DATA MEM_B_DM<3>MEM_DATAMEM_40S MEM_B_DQ<31..24>

MEM_DATAMEM_40S MEM_B_DM<2>MEM_40S MEM_DATA MEM_B_DQ<23..16>

MEM_DATAMEM_40S MEM_B_DM<5>MEM_40S MEM_DATA MEM_B_DQ<47..40>

MEM_DATAMEM_40S MEM_B_DM<4>MEM_DATAMEM_40S MEM_B_DQ<39..32>

MEM_DATAMEM_40S MEM_B_DM<7>MEM_DATAMEM_40S MEM_B_DQ<63..56>

MEM_B_DM<6>MEM_DATAMEM_40S

MEM_B_DQ<55..48>MEM_DATAMEM_40S

MEM_CLKMEM_70D_VDD MEM_B_CLK_P<4..3>

MEM_70D MEM_DQS MEM_A_DQS_P<7>

MEM_70D MEM_B_DQS_N<4>MEM_DQS



MEM_70D MEM_DQS MEM_B_DQS_N<6>

MEM_70D MEM_DQS MEM_B_DQS_P<7>

MEM_70D MEM_DQS MEM_B_DQS_N<7>

MEM_70D_VDD MEM_CLK MEM_B_CLK_N<4..3>

MEM_CLKMEM_70D_VDD MEM_B_CLK_P<1..0>

MEM_CLKMEM_70D_VDD MEM_B_CLK_N<1..0>

MEM_70D MEM_DQS MEM_A_DQS_N<5>

MEM_70D_VDD MEM_CLK MEM_A_CLK_N<4..3>

MEM_A_ODT<3..0>MEM_CTRLMEM_40S_VDD

MEM_A_DQ<15..8>MEM_DATAMEM_40S

MEM_40S MEM_DATA MEM_A_DM<2>


MEM_DQSMEM_70D MEM_A_DQS_P<2>




MEM_DQSMEM_70D MEM_A_DQS_P<0>


MEM_DQS MEM_A_DQS_P<6>MEM_70D

MEM_DQS MEM_A_DQS_P<5>MEM_70D


MEM_40S MEM_A_DM<7>MEM_DATA

MEM_A_DQ<63..56>MEM_40S MEM_DATA

MEM_A_DM<6>MEM_DATAMEM_40S


MEM_40S MEM_DATA MEM_A_DQ<47..40>

MEM_A_DM<4>MEM_DATAMEM_40S



MEM_A_DM<1>MEM_40S MEM_DATA

MEM_DATAMEM_40S MEM_A_DQ<7..0>

MEM_40S_VDD MEM_A_WE_LMEM_CMD

MEM_40S_VDD MEM_A_CAS_LMEM_CMD

MEM_A_RAS_LMEM_CMDMEM_40S_VDD

MEM_CMD MEM_A_BA<2..0>MEM_40S_VDD

MEM_CMDMEM_40S_VDD MEM_A_A<14..0>

MEM_CTRLMEM_40S_VDD MEM_A_CS_L<3..0>MEM_CTRL MEM_A_CKE<3..0>MEM_40S_VDD

MEM_CLKMEM_70D_VDD MEM_A_CLK_P<4..3>

MEM_A_CLK_P<1..0>MEM_CLKMEM_70D_VDD




MEM_70D MEM_DQS MEM_A_DQS_N<3>

MEM_DATA MEM_A_DM<5>MEM_40S



MEM_A_CLK_N<1..0>MEM_CLKMEM_70D_VDD

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD







MEM_B_DQS_P<4>MEM_DQSMEM_70D


MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND


Memory Constraints

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE =STANDARD* =STANDARDMEM_40S

=STANDARD =STANDARDMEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE=40_OHM_SE

MEM_70D =70_OHM_DIFF=70_OHM_DIFF* =70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF

*MEM_DQS MEM_2OTHER*

**MEM_DATA MEM_2OTHER

* *MEM_CMD MEM_2OTHER

**MEM_CTRL MEM_2OTHER

MEM_70D_VDD =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF* =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF

?*MEM_CLK2MEM =4:1_SPACING

=1.5:1_SPACING ?*MEM_CMD2CMD

*MEM_CLKMEM_CLK MEM_CLK2MEM

*MEM_DATAMEM_CLK MEM_CLK2MEM

MEM_CTRL2MEM*MEM_CTRL MEM_DQS

?* =2:1_SPACINGMEM_CTRL2CTRL

?*MEM_DATA2DATA =1.5:1_SPACING

MEM_CTRLMEM_CMD * MEM_CMD2MEM

MEM_DATA MEM_CMD2MEMMEM_CMD *

MEM_DQS *MEM_CMD MEM_CMD2MEM

MEM_DATA2MEMMEM_CLKMEM_DATA *

MEM_CTRL MEM_DATA2MEM*MEM_DATA

*MEM_DATA MEM_DATA2DATAMEM_DATA

MEM_CMD2CMDMEM_CMD *MEM_CMD

?* =3:1_SPACINGMEM_DATA2MEM

?*MEM_DQS2MEM =3:1_SPACING

?*MEM_CTRL2MEM =2.5:1_SPACING

* MEM_CLK2MEMMEM_CTRLMEM_CLK

*MCP_MEM_COMP ?0.2 MM

0.175 MM0.175 MM =STANDARD* Y =STANDARD =STANDARDMCP_MEM_COMP

* *MEM_CLK MEM_2OTHER

MEM_DQS MEM_DQS2MEM*MEM_CTRL

MEM_CLK *MEM_CMD MEM_CMD2MEM

* MEM_DQS2MEMMEM_DQS MEM_CMD

MEM_DQS MEM_DQS2MEM*MEM_CLK

MEM_CMD *MEM_DATA MEM_DATA2MEM

MEM_CTRL * MEM_CTRL2MEMMEM_DATA

MEM_CTRL MEM_CTRL2MEM*MEM_CMD

MEM_DQS MEM_DQS2MEM*MEM_DATA

* MEM_DQS2MEMMEM_DQS MEM_DQS

?*MEM_CMD2MEM =3:1_SPACING

?*MEM_2OTHER =3:1_SPACING

*MEM_CLK MEM_CLK2MEMMEM_CMD

*MEM_DQSMEM_CLK MEM_CLK2MEM

*MEM_CLK MEM_CTRL2MEMMEM_CTRL

MEM_CTRL *MEM_CTRL MEM_CTRL2CTRL

MEM_DQS *MEM_DATA MEM_DATA2MEM

33 15

33 15

33 15

32 16 15

32 16 15

32 16 15

32 15

32 15

32 15

32 15

32 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 16

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 16

33 15

33 15

33 15

33 16

31 16 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

31 15

31 15

31 15

31 15

31 15

31 16 15

31 16 15

33 16

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

16

33 15

33 15

33 15

33 15

33 15

33 15

33 15

33 15

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TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM















PCIE REF CLOCKS

SATA

PCIE GRAPHICS

PCI-ExpressNET_TYPE

SPACINGPHYSICALELECTRICAL_CONSTRAINT_SET

PCIE I/OSATA Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

MISC

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PCIE_90D PCIE PCIE_MINI_R2D_L_N

PCIEPCIE_90D PCIE_MINI_R2D_C_N

PCIE_90D PCIE PCIE_MINI_R2D_L_P

PCIE_MINI_D2R_PPCIE_90D PCIE

PCIE_MINI_D2R_NPCIEPCIE_90D

PCIE PCIE_FW_R2D_PPCIE_90D

PCIE_90D PCIE PCIE_FW_R2D_N

PCIEPCIE_90D PCIE_FW_R2D_C_PPCIE_FW_R2D_C_NPCIE_90D PCIE

PCIE_FW_D2R_PPCIEPCIE_90D

PCIE_FW_D2R_NPCIE_90D PCIE

PCIE_FW_D2R_C_PPCIEPCIE_90D

PCIE_90D PCIE_FW_D2R_C_NPCIE

PCIE_MINI_R2D_C_PPCIE_90D PCIE

CLK_PCIE_100D PCIE_CLK100M_FW_PCLK_PCIE

CLK_PCIE PCIE_CLK100M_FW_NCLK_PCIE_100D

PCIE_CLK100M_MINI_CON_NCLK_PCIECLK_PCIE_100D

PCIE_CLK100M_MINI_NCLK_PCIECLK_PCIE_100D

PCIE_CLK100M_MINI_CON_PCLK_PCIECLK_PCIE_100D

PCIE_CLK100M_MINI_PCLK_PCIECLK_PCIE_100D

CLK_PCIECLK_PCIE_100D GPU_CLK100M_PCIE_NCLK_PCIE_100D CLK_PCIE GPU_CLK100M_PCIE_P

MCP_50S SATA_TERMP MCP_SATA_TERMP

SATA_ODD_D2R_C_PSATA_100D SATA

SATA_100D SATA SATA_ODD_D2R_C_N

SATA_ODD_D2R_NSATA_100D SATA

SATA_ODD_D2R_PSATA_100D SATA

SATA_ODD_R2D_NSATA_100D SATA

SATA_ODD_R2D_PSATASATA_100D

SATA_100D SATA_ODD_R2D_C_NSATA

SATA_100D SATA_ODD_R2D_C_PSATA

SATA_HDD_D2R_C_NSATASATA_100D

SATASATA_100D SATA_HDD_D2R_C_PSATA_100D SATA SATA_HDD_D2R_NSATA_100D SATA SATA_HDD_D2R_PSATA_100D SATA SATA_HDD_R2D_NSATA_100D SATA_HDD_R2D_PSATA

SATA_100D SATA_HDD_R2D_C_NSATA

SATA_100D SATA_HDD_R2D_C_PSATA

PCIE MXM_PCIE_D2R_N<15..0>PCIE_90D

MXM_PCIE_D2R_P<15..0>PCIEPCIE_90D

MCP_PEX_COMPMCP_50S MCP_IFPAB_VPROBEMCP_PEX_COMPMCP_DV_COMP MCP_IFPAB_RSET

PCIE_90D PCIE_MINI_R2D_NPCIE

PCIE_90D PCIE_MINI_R2D_PPCIE

PCIE PEG_D2R_N<15..0>PCIE_90D

PEG_R2D_C_N<15..0>PCIE_90D PCIE

PEG_D2R_P<15..0>PCIE_90D PCIE

PCIE_90D MXM_PCIE_R2D_P<15..0>PCIE

PCIE_90D MXM_PCIE_R2D_N<15..0>PCIE

PCIE_90D PEG_R2D_C_P<15..0>PCIE

PM_SLP_S4_L

PM_SLP_S3_L

MCP_PEX_CLK_COMPMCP_50S MCP_PEX_COMP

MCP Constraints 1SYNC_MASTER=MASTER SYNC_DATE=N/A

=100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF

TOP,BOTTOMPCIE ?=4X_DIELECTRIC=3X_DIELECTRIC ?*PCIE

* 0.2 MM ?MCP_PEX_COMP

0.5 MM ?*CLK_PCIE

=100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFFSATA_100D =100_OHM_DIFF* =100_OHM_DIFF

* ?SATA_TERMP 0.2 MM

?SATA * =4x_DIELECTRIC

PCIE_90D =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF*

=3x_DIELECTRICTOP,BOTTOMSATA ?

34

34 17

34

34 17

34 17

41

41

41 17

41 17

41 17

41 17

41

41

34 17

41 17

41 17

34

34 17

34

34 17

87 9

87 9

20

110 45

110 45

45 20

45 20

110 45

110 45

45 20

45 20

110 45

110 45

45 20

45 20

110 45

110 45

45 20

45 20

86 84

86 84

26 18

26 18

34

34

86 9

86 9

86 9

86 84

86 84

86 9

70 21

21 9

17




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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

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B

8 7 5 4 2 1












































PCI Bus Constraints

XTAL Constraints


SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints


HD Audio Interface Constraints




USB 2.0 Interface Constraints

NET_TYPE

PHYSICAL SPACING


SMBus Interface Constraints


LPC Bus Constraints

103 OF 110

051-7845

A.0.0


HDA_55S HDA HDA_SDOUT

HDA AUD_SPDIF_IN

MCP_CLK25M_XTALINXTALCLK_MCP_XTAL

USB_90D USB USB_IR_L_P

USBUSB_90D USB_SDCARD_N

MCP_50S SPI SPI_CLK_R

USB_90D USB USB_IR_N

USB_BT_L_PUSB_90D USB

USB_90D USB_BT_NUSB

USB_90D USB USB_BT_P

USB_90D USB USB_SDCARD_L_NUSBUSB_90D USB_SDCARD_L_P

USB_90D USB USB_SDCARD_PUSBUSB_90D USB_IR_L_N

USB_90D USB USB_D_MUXED_P

USB USB_PORT3_NUSB_90D

USB_CAMERA_NUSB_90D USB

CLK_PCICLK_PCI_55S PCI_CLK33M_MCPCLK_PCI_55S CLK_PCI PCI_CLK33M_MCP_RPCI_55S PCI PCI_REQ1_L

LPC_55S LPC_AD<3..0>LPC

LPC_AD_R<3..0>LPC_55S LPC

LPCLPC_55S LPC_FRAME_L

USB_EXTA_PUSB_90D USB

USB_EXTA_NUSB_90D USB

USB_PORT0_PUSB_90D USB

USB_90D USB USB_CAMERA_L_NUSB_CAMERA_L_PUSB_90D USB

USB_CAMERA_PUSBUSB_90D

USB_90D USB USB_EXTD_P

USB_90D USB USB_EXTD_N

USB_90D USB USB_D_MUXED_N

USBUSB_90D USB_PORT3_P

USB_90D USB USB_PORT1_N

USB_90D USB USB_PORT2_P

USB_90D USB_PORT1_PUSB

USB_90D USB_PORT0_NUSB

USB_EXTB_PUSBUSB_90D

USB USB_EXTC_NUSB_90D

PM_CLK32K_SUSCLKCLK_LPCCLK_LPC_55S

LPC LPC_FRAME_R_LLPC_55S

LPC_55S LPC_RESET_LLPC

LPC_CLK33M_SMC_RCLK_LPC_55S CLK_LPC

MCP_USB_RBIAS MCP_USB_RBIAS_GND

PM_CLK32K_SUSCLK_RCLK_LPC_55S CLK_LPC

CLK_LPC_55S LPC_CLK33M_SMCCLK_LPC

PCI PCI_REQ0_LPCI_55S

USBUSB_90D USB_EXTC_P

USB_90D USB_PORT2_NUSB

SPIMCP_50S SPI_MISO_R

USB_EXTB_NUSBUSB_90D

HDA_55S HDA_RST_R_LHDA

MCP_50S SPI SPI_CS0_L

HDA HDA_SYNCHDA_55S

HDA_55S HDA_RST_LHDA

HDA_SDOUT_RHDAHDA_55S

HDA HDA_BIT_CLKHDA_55S

SPI_MISOMCP_50S SPI

LPC_CLK33M_LPCPLUSCLK_LPC_55S CLK_LPC

USB_90D USB USB_IR_PUSB_BT_L_NUSB_90D USB

MCP_50S SPI SPI_MOSIMCP_50S SPI SPI_MOSI_RMCP_50S SPI SPI_CLK

HDA_55S HDA HDA_SDIN0

MCP_HDA_PULLDN_COMPMCP_HDA_COMP

HDAHDA_55S HDA_BIT_CLK_R

HDA_55S HDA AUD_SDI_R

MCP_50S SPI SPI_CS0_R_L

HDAHDA_55S HDA_SYNC_R

HDA AUD_SPDIF_OUT

XTAL RTC_CLK32K_XTALOUTCLK_MCP_XTAL

AUD_SPDIF_CHIPHDA

RTC_CLK32K_XTALINXTALCLK_MCP_XTAL

MCP_CLK25M_XTALOUTCLK_MCP_XTAL XTAL

MCP Constraints 2SYNC_MASTER=MASTER SYNC_DATE=N/A

=55_OHM_SE =55_OHM_SE =STANDARD* =55_OHM_SE =55_OHM_SECLK_PCI_55S =STANDARD

?*PCI =STANDARD

=STANDARD=55_OHM_SE=55_OHM_SE =STANDARD*CLK_LPC_55S =55_OHM_SE=55_OHM_SE

LPC ?* 0.15 MM

0.2 MM0.2 MM =STANDARD=STANDARD=STANDARD =STANDARD*MCP_USB_RBIAS

=100_OHM_DIFF* =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFCLK_MCP_XTAL

* ?=4X_DIELECTRICXTAL

SPI 0.2 MM ?*

* ?USB =2x_DIELECTRIC

* =STANDARD=STANDARDHDA_55S =55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

=90_OHM_DIFF =90_OHM_DIFF*USB_90D =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

=2x_DIELECTRICSMB * ?

0.2 MM ?*MCP_HDA_COMP

=4x_DIELECTRICTOP,BOTTOMUSB ?

* ?0.2 MMCLK_LPC

=2x_DIELECTRICHDA * ?

=55_OHM_SE=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SESMB_55S * =STANDARD

=STANDARD=STANDARD=55_OHM_SE* =55_OHM_SE =55_OHM_SELPC_55S =55_OHM_SE

=55_OHM_SE=55_OHM_SESPI_55S =55_OHM_SE=55_OHM_SE* =STANDARD =STANDARD

* =55_OHM_SE=55_OHM_SE =55_OHM_SE =STANDARD =STANDARDPCI_55S =55_OHM_SE

?*CLK_PCI 0.2 MM

62 21

66 9

28 21

110 47

47 20

61 51 21

47 20

110 47

47 20

47 20

110 47

110 47

47 20

110 47

46

46

47 20

19

19

19

51 49 19

19

51 49 19

46 20

46 20

46

110 47

110 47

47 20

46 20

46 20

46

46

46

46

46

46

46 20

46 20

49 9

19

19 9

19 9

20

21 9

49 9

19

46 20

46

61

46 20

21

51

62 21

62 21

21

62 21

61 51 21

51 9

47 20

110 47

61

61 51 21

61

62 21

21

21

62

51 21

21

66 62

28 21

62

28 21

28 21




36

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PAGE TITLE

C

A

D

2 1


Apple Inc.

PAGE


A

B

C

345678

D

B

8 7 5 4 2 1














NET_TYPE

SPACING

MCP RGMII (Ethernet) Constraints


SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

RTL8211CLGR (ETHERNET PHY) CONSTRAINTS

104 OF 110

051-7845

A.0.0


ENET_MDI_100D ENET_MDI_T_N<3..0>ENET_MDI

ENET_MDI_100D ENET_MDI ENET_MDI_T_P<3..0>ENET_MDIENET_MDI_100D ENET_MDI_N<3..0>ENET_MDIENET_MDI_100D ENET_MDI_P<3..0>

MCP_MII_COMP_GNDMCP_MII_COMP

ENET_CLK125M_TXCLKENET_MII_55S ENET_MII

ENET_TX_CTRLENET_MIIENET_MII_55S

ENET_TXD<3..1>ENET_MII_55S ENET_MII

ENET_TXD<0>ENET_MII_55S ENET_MII

ENET_CLK125M_RXCLK_RENET_MIIENET_MII_55S

ENET_MDCENET_MIIENET_MII_55S

MCP_CLK25M_BUF0_RMCP_BUF0_CLKENET_MII_55S

ENET_MII ENET_RXD_R<3..1>ENET_MII_55S

MCP_MII_COMP MCP_MII_COMP_VDD

ENET_RXD<0>ENET_MII_55S ENET_MII

ENET_MII_55S ENET_MII ENET_RXCTL_RENET_RX_CTRLENET_MII_55S ENET_MII

ENET_MII ENET_RXD<3..1>ENET_MII_55S

ENET_CLK125M_RXCLKENET_MIIENET_MII_55S

RTL8211_CLK25M_CKXTAL1MCP_BUF0_CLKENET_MII_55S

ENET_RXD_R<0>ENET_MII_55S ENET_MII

ENET_MDIOENET_MIIENET_MII_55S


FIT;

Ethernet Constraints

0.2 MM 0.2 MM=STANDARD =STANDARD =STANDARD*MCP_MII_COMP =STANDARD

0.6 MM ?*ENET_MDI

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFFENET_MDI_100D * =100_OHM_DIFF

0.3 MM ?*ENET_MII

=55_OHM_SEENET_MII_55S =55_OHM_SE=55_OHM_SE =STANDARD =STANDARD* =55_OHM_SE

=3:1_SPACING* ?MCP_BUF0_CLK

39

39

39 37

39 37

18

37 18

37 18

37 18

37 18

37

37 18

38 18

37

18

37 18

37

37 18

37 18

37 18

38 37

37

37 18









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A

D

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PAGE


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B

C

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D

B

8 7 5 4 2 1

FireWire Interface ConstraintsNET_TYPE

PHYSICAL

PORT 1 & 2 NOT USED

ELECTRICAL_CONSTRAINT_SET SPACING

FireWire Net Properties

105 OF 110

051-7845

A.0.0


FW_110D FW_TP FW_PORT0_TPA_P

FW_P0_TPB_L_PFW_TPFW_110D

FW_P0_TPA_L_PFW_TPFW_110D

FW_PORT0_TPA_NFW_110D FW_TP

FW_TP FW_PORT0_TPB_PFW_110D

FW_PORT0_TPB_NFW_TPFW_110D

FW_P0_TPB_L_NFW_TPFW_110D

FW_P0_TPA_L_NFW_TPFW_110D

* =3:1_SPACING ?FW_TP

=110_OHM_DIFF=110_OHM_DIFFFW_110D =110_OHM_DIFF=110_OHM_DIFF=110_OHM_DIFF* =110_OHM_DIFF


FireWire Constraints

43 42

42

42

43 42

43 42

43 42

42

42




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PAGE


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B

C

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SMBus Interface Constraints

SMC SMBus Net Properties

PHYSICAL

NET_TYPE

SPACINGELECTRICAL_CONSTRAINT_SET

106 OF 110

051-7845

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SMB SMBUS_SMC_B_S0_SCLSMB_55S

SMB_55S SMB SMBUS_SMC_B_S0_SDA

SMB_55S SMB SMBUS_SMC_BSA_SDA

SMB_55S SMB SMBUS_MCP_0_CLK

SMB_55S SMB SMBUS_MCP_0_DATA

SMB_55S SMB SMBUS_SMC_A_S3_SCL

SMBUS_SMC_MGMT_SDASMBSMB_55S

SMBUS_SMC_MGMT_SCLSMBSMB_55S

SMB SMBUS_SMC_A_S3_SDASMB_55S

SMB_55S SMBUS_SMC_0_S0_SCLSMB

SMB_55S SMBUS_SMC_BSA_SCLSMB

SMB_55S SMB SMBUS_SMC_0_S0_SDA

SMBUS_SMC_MGMT_SDASMBSMB_55S

SMB SMBUS_SMC_MGMT_SCLSMB_55S


SMC Constraints

=55_OHM_SE =STANDARD=55_OHM_SE =55_OHM_SE=55_OHM_SESMB_55S * =STANDARD

SMB * ?=2x_DIELECTRIC

52

52

52

52 21 13

52 21 13

52

106 52

106 52

52

52

52

52

106 52

106 52




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PAGE TITLE

C

A

D

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Apple Inc.

PAGE


A

B

C

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D

B

8 7 5 4 2 1







TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM


TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

Digital Video Signal Constraints

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.Max length of LVDS/DisplayPort/TMDS traces: 12 inches.


NET_TYPE

PHYSICAL SPACING

ASSINGED IN CONT. MGR.

107 OF 110

051-7845

A.0.0


MXM_DP_A_AUX_NDP_100D DISPLAYPORT

MCP_HDMI_RSETMCP_DV_COMP

DP_100D DISPLAYPORT DP_IG_AUX_CH_P

DP_100D DP_IG_AUX_CH_NDISPLAYPORT

DISPLAYPORTDP_100D DP_ML_N<3..0>

DISPLAYPORTDP_100D DP_ML_CONN_N<3..0>DISPLAYPORT DP_ML_CONN_P<3..0>DP_100D

DISPLAYPORT DP_ML_P<3..0>DP_100D

DISPLAYPORTDP_100D DP_IG_ML_N<3..0>

MCP_DV_COMP MCP_HDMI_VPROBE

MXM_DP_A_ML_N<3..0>DP_100D DISPLAYPORT

DP_IG_ML_P<3..0>DP_100D DISPLAYPORT

DP_100D DISPLAYPORT MXM_DP_A_ML_P<3..0>

DP_AUXCH_SW_PDP_100D DISPLAYPORT

DP_AUXCH_SW_NDISPLAYPORTDP_100D

DP_AUX_CH_C_PDISPLAYPORTDP_100D

DISPLAYPORT DP_AUX_CH_C_NDP_100D

MXM_DP_A_AUX_PDISPLAYPORTDP_100D

LVDS LVDS_IG_B_CLK_NLVDS_100D

LVDS_100D LVDS LVDS_IG_B_CLK_PLVDSLVDS_100D LVDS_IG_A_DATA_N<3..0>

LVDS_IG_A_DATA_P<3..0>LVDS_100D LVDS

LVDS_100D LVDS_IG_A_CLK_NLVDS

LVDS_IG_A_CLK_PLVDS_100D LVDS

LVDS_A_CLK_PLVDSLVDS_100D

LVDS_B_CLK_NLVDSLVDS_100D

LVDS_100D LCD_CONN_A_CLK_PLVDS

LCD_CONN_A_CLK_NLVDS_100D LVDS

LVDS_A_DATA_N<3..0>LVDSLVDS_100D

LVDS_B_DATA_P<3..0>LVDSLVDS_100D

LCD_CONN_A_DATA_P<3..0>LVDS_100D LVDS

LVDS_A_DATA_P<3..0>LVDSLVDS_100D

LVDS_IG_B_DATA_N<3..0>LVDS_100D LVDS

LVDS_100D LVDS LVDS_IG_B_DATA_P<3..0>

LCD_CONN_A_DATA_N<3..0>LVDS_100D LVDS

LCD_CONN_B_CLK_NLVDSLVDS_100D

LCD_CONN_B_CLK_PLVDS_100D LVDS

LVDS_B_CLK_PLVDS_100D LVDS

LVDS_A_CLK_NLVDS_100D LVDS

LVDS_100D LVDS LCD_CONN_B_DATA_N<3..0>LVDS_100D LVDS LCD_CONN_B_DATA_P<3..0>

LVDS_B_DATA_N<3..0>LVDSLVDS_100D

GRAPHICS CONSTRAINTSSYNC_DATE=N/ASYNC_MASTER=MASTER

=STANDARD* =STANDARD0.5 MMY 0.5 MM =STANDARDMCP_DV_COMP

=100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFFLVDS_100D =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF* =100_OHM_DIFFDP_100D =100_OHM_DIFF 0.08 MM

?*DISPLAYPORT =3x_DIELECTRIC DISPLAYPORT ?=4x_DIELECTRICTOP,BOTTOM

*LVDS ?=3x_DIELECTRIC TOP,BOTTOM ?=4x_DIELECTRICLVDS

93 84

26 18

93 18

93 18

94 91

94

94

94 91

91 9

26 18

91 84

91 9

91 84

93

93

94 93

94 93

93 84

89 18

89 18

89 18

89 18

89 18

89 18

89

89

90 89

90 89

89

89

90 89

89

89 18

89 18

90 89

90 89

90 89

89

89

90 89

90 89

89












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PAGE TITLE

C

A

D

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PAGE


A

B

C

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D

B

8 7 5 4 2 1


















TABLE_PHYSICAL_ASSIGNMENT_ITEM


PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD












OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
























K50/K51 SPECIFIC NET PROPERTIES


NET_TYPE

SPACING

108 OF 110

051-7845

A.0.0


THERM_DIFF SENSE_1V5_S0_PTHERMAL

THERM_DIFF SENSE_1V5_S0_NTHERMAL

=PP1V5_S3_MEM_APPDDR_MEM

PPDDR_MEM =PP1V5_S3_MEM_BVR_CPU_SW1SWITCHNODE

VR_CPU_SW2SWITCHNODE

THERMAL SNS_T_DP2_DN3THERM_DIFF

3V3S5_SWSWITCHNODE

VR_CPU_SW3SWITCHNODE

SWITCHNODE 5VS3_SW

SNS_T_DN2_DP3THERM_DIFF THERMAL

THERM_DIFF THERMAL SNS_T_DN1_DP6

CPU_THERMD_NTHERMALTHERM_DIFF

CPU_THERMD_PTHERM_DIFF THERMAL

THERM_DIFF THERMAL SNS_T_DP1_DN6

1V8_SWSWITCHNODE

1V1S5_SWSWITCHNODE

PVTTS0_PHASESWITCHNODE

MCPCORES0_PHASESWITCHNODE

THERMAL MCP_THMDIODE_PTHERM_DIFF

THERM_DIFF SNS_T_DP4_DN5THERMAL

THERM_DIFF SNS_T_DN4_DP5THERMAL

THERM_DIFF THERMAL SNS_LCD_P

THERMAL MXM_PWRSRC_SENSOR_PTHERM_DIFF

THERMAL MCP_THMDIODE_NTHERM_DIFF

SNS_DIFF VR_CPU_ISNS1_R_PTHERMAL

THERMALSNS_DIFF VR_CPU_ISNS1_R_N

THERM_DIFF THERMAL SNS_ODD_N

THERM_DIFF SNS_LCD_NTHERMAL

SNS_CPU_H_NTHERM_DIFF THERMAL

THERM_DIFF SNS_CPU_H_PTHERMAL

THERM_DIFF SNS_ODD_PTHERMAL

SNS_DIFF THERMAL VR_CPU_ISNS2_R_P

THERMAL VR_ISNS_CPU_N

THERMAL CPU_VCC_SENSE

THERMAL SMC_GPU_VSENSE

THERMAL SMC_CPU_VSENSE

THERMALSNS_DIFF VR_CPU_ISNS1_NTHERMALSNS_DIFF VR_CPU_ISNS1_P

THERMAL SMC_1V5_S0_ISENSE_R

THERMAL SMC_GPU_ISENSE

VR_CPU_ISNS3_R_NSNS_DIFF THERMAL

THERMAL SMB_PECI_L

THERMAL MXM_PWRSRC_SENSOR_NTHERM_DIFF

THERMAL SNS_MXM_NTHERM_DIFF

THERM_DIFF THERMAL SNS_MXM_PTHERMALTHERM_DIFF SNS_AMB_N

SNS_AMB_PTHERMALTHERM_DIFF

THERM_DIFF THERMAL SNS_MCP_NTHERM_DIFF THERMAL SNS_MCP_P

THERMAL SMC_1V5_S0_ISENSE

THERMAL HDD_OOB_TEMP_FILT

THERMAL HDD_OOB_TEMP

THERMAL HDD_OOB_TEMP_R

THERMAL VR_CPU_IOUTTHERMAL SMC_CPU_ISENSE

SNS_DIFF THERMAL VR_CPU_ISNS2_R_N

VR_CPU_ISNS3_R_PSNS_DIFF THERMAL

SNS_DIFF THERMAL VR_CPU_ISNS3_NSNS_DIFF THERMAL VR_CPU_ISNS3_P

SNS_DIFF THERMAL VR_CPU_ISNS2_NSNS_DIFF THERMAL VR_CPU_ISNS2_P

THERMAL SMC_HDD_OOB_TEMP

THERMAL CPU_PECI_MCP

THERMAL SMC_1V5_S0_VSENSE

SNS_PS_CPU_ISNSTHERMAL

THERMAL CPU_PECI_L

THERMAL VR_ISNS_CPU_P

SMC_MCP_CORE_ISENSETHERMAL

THERMAL SMC_MCP_CORE_VSENSEMCPCORES0_IMONTHERMAL

**AUDIO AUDIO

SWITCHNODE * * SWITCHNODE

GND_P2MMGND *THERMAL

4:1_SPACING* *THERMAL

PWR_P2MM*PWRTHERMAL

PWR_P2MM*PWRCLK_PCIE


K22/K23 SPECIFIC CONSTRAINTS

*GNDSATA GND_P2MM

GND_P2MM*CLK_PCIE GND

* PWR_P2MMMEM_DQS PPDDR_MEM

GND * GND_P2MMMEM_CTRL

PWR_P2MMPPDDR_MEM *MEM_CLK

MEM_CMD GND * GND_P2MM

* 0.20 MM 1000PWR_P2MM

* 10000.20 MMGND_P2MM

PPDDR_MEM PWR_P2MM*MEM_CTRL

GNDUSB * GND_P2MM

GND_P2MM*PCIE GND

PPDDR_MEMMEM_DATA * PWR_P2MM

PWR_P2MMMEM_CMD *PPDDR_MEM

GND_P2MMMEM_DQS *GND

GND * ?=STANDARD

THERM_DIFF * 1:1_DIFFPAIR

SNS_DIFF 1:1_DIFFPAIR*

?PPDDR_MEM * =STANDARD

GND_P2MMFSB_DSTB *GND

GND GND_P2MMCPU_VCCSENSE *

GND_P2MMMEM_CLK GND *

GND_P2MMMEM_DATA GND *

GND_P2MM*GNDCPU_GTLREF

GND_P2MM*CPU_COMP GND

CLK_FSB * GND_P2MMGND

TOP 500 MILPCIE_90D

500 MILTOPUSB_90D

TOP 600 MIL0.1 MMMEM_40S_VDD

600 MILTOPMEM_40S 0.1 MM

TOP 0.1 MM 600 MILMEM_70D

0.25 MM* 250 MILMCP_DV_COMP

500 MILTOP 0.1 MMMCP_DV_COMP

0.23 MM 100 MILBOTTOMCPU_27P4S

500 MIL0.1 MMTOPMCP_USB_RBIAS

TOP 0.1 MM 500 MILMCP_MII_COMP

0.1 MMMCP_MEM_COMP 500 MILTOP

I230

I229

I228

I227

I226

I225

I224

I223

I222

I221

I220

I219

I218

I217

I216

I215

I214

I213

I212

I211

I210

54

54

31 30 6

32 30 6

72

72

55

76

72

73

55

55

55 11

55 11

55

80

79

76

74

55 21

55

55

110 55

53

55 21

71

71

110 55

110 55

55

55

110 55

71

53

53 12

53 49

53 49

72 71

72 71

54

53 49

71

55

53

55

55

110 55

110 55

55

55

54 50

55

55

55

71 53

53 49

71

71

72 71

72 71

72 71

72 71

55

55 14

54 50

53

55 11

53

54 50

54 50

74 54


































































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PHYSICAL_RULE_SETAREA_TYPENET_PHYSICAL_TYPETABLE_PHYSICAL_ASSIGNMENT_HEAD










TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

















CONSTRAINTS ARE BASED ON MCP79 DESIGN GUIDE DG-03328-001_V06PCI,LPC,SMB,HDA,SPI,RGMII,SMBUS ARE ROUTED AS 55 OHM SE SIGNALS

PHYSICAL CONSTRAINTS

CONSTRAINTS FOR BGA AREA

SPACING RULE SET

K50/K51 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

109 OF 110

051-7845

A.0.0


100_OHM_DIFF =STANDARD=STANDARD =STANDARD=STANDARDN* =STANDARD

ISL3,ISL6 0.081 MM 0.1 MM=STANDARD 0.25 MMY100_OHM_DIFF 0.085 MM

TOP,BOTTOM100_OHM_DIFF =STANDARDY 0.1 MM0.085 MM0.091 MM 0.25 MM

=STANDARD*110_OHM_DIFF =STANDARDN =STANDARD=STANDARD=STANDARD

=STANDARD=STANDARD1:1_DIFFPAIR * Y 0.1 MM=STANDARD 0.085 MM

* YPOWER_WIDTH 0.200 MM0.600 MM 3.0 MM =STANDARD =STANDARD

0.085 MMTOP,BOTTOM =STANDARD110_OHM_DIFF 0.15 MMY 0.075 MM 0.320 MM

0.099 MM 12 MM 0.200 MM90_OHM_DIFF 0.1 MMYISL3,ISL6 0.085 MM

Y =STANDARD 0.1 MMTOP,BOTTOM70_OHM_DIFF 0.165 MM 0.085 MM 0.130 MM

=STANDARDN =STANDARD =STANDARD=STANDARD=STANDARD90_OHM_DIFF *

MCP_PEX_COMP BGA_P2MM* BGA_P1MM

0.085 MM55_OHM_SE Y =STANDARDTOP,BOTTOM 0.085 MM

0.275 MM =STANDARD =STANDARDY27P4_OHM_SE * 0.085 MM =STANDARD

CLK_LPC * BGA_P1MM BGA_P1MM

=STANDARD =STANDARD=STANDARDN*70_OHM_DIFF =STANDARD=STANDARD

=STANDARDTOP,BOTTOM Y40_OHM_SE 0.085 MM0.165 MM

MCP_MEM_COMP BGA_P2MM* BGA_P1MM

BGA_P2MMMCP_FSB_COMP * BGA_P1MM

BGA_P1MM*CLK_PCI BGA_P1MM

BGA_P1MMFSB_DSTB BGA_P1MMFSB_DSTB

BGA_P1MM*CLK_FSB BGA_P2MM

BGA_P1MM*MEM_CLK BGA_P2MM

BGA_P1MM*CLK_PCIE BGA_P1MM

BGA_P1MM** BGA_P1MM

?BGA_P2MM * 0.2 MM

=DEFAULT ?*BGA_P1MM

PWR_P2MM 0.2 MM* 1000

CLK_SPACING_0.6MM ?* 0.6 MM

0.380 MM* ?5X_DIELECTRIC

0.400 MM5X_DIELECTRIC ?TOP,BOTTOM

0.320 MMTOP,BOTTOM ?4X_DIELECTRIC

TOP,BOTTOM50_OHM_SE Y 0.085 MM0.1 MM 15 MM

0.1 MMY =STANDARD =STANDARD50_OHM_SE 0.085 MM* =STANDARD

* =STANDARDY =STANDARD0.085 MM =STANDARD0.136 MM42_OHM_SE

40_OHM_SE * =STANDARDY =STANDARD0.085 MM0.15 MM =STANDARD

0.085 MMTOP,BOTTOM27P4_OHM_SE Y =STANDARD0.300 MM

0.240 MMTOP,BOTTOM ?3X_DIELECTRIC

?* 0.300 MM4X_DIELECTRIC

* ?CLK_SPACING_0.5MM 0.5 MM

SWITCHNODE * 10000.6 MM

42_OHM_SE =STANDARDTOP,BOTTOM Y 0.085 MM0.151 MM

=STANDARDY =STANDARD*55_OHM_SE 0.075 MM =STANDARD0.076 MM

90_OHM_DIFF =STANDARDY 0.085 MMTOP,BOTTOM 0.1 MM0.110 MM 0.200 MM

K22/K23 RULE DEFINITIONSSYNC_DATE=N/ASYNC_MASTER=MASTER

VR_CTL_PHY POWER_WIDTH*

POWER POWER_WIDTH*

0.155 MM 0.135 MMY 0.1 MM=STANDARDISL3,ISL670_OHM_DIFF 0.085 MM

?*BGA_P3MM 0.3 MM

* 0.2 MMGND_P2MM 1000

?=DEFAULT*STANDARD

* 0.1 MM ?DEFAULT

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM MMNO_TYPE,BGA_P1MM 15.5.1

0.150 MM2X_DIELECTRIC ?*

2X_DIELECTRIC 0.160 MMTOP,BOTTOM ?

0.220 MM3X_DIELECTRIC * ?

?0.15 MM1.5:1_SPACING *

?* 0.2 MM2:1_SPACING

*2.5:1_SPACING 0.25 MM ?

?*3:1_SPACING 0.3 MM

?0.4 MM4:1_SPACING *

=DEFAULT=DEFAULT =DEFAULTSTANDARD 12.7 MM* Y =DEFAULT

100 MM=50_OHM_SEY* 0 MM=50_OHM_SEDEFAULT 0 MM

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN




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1 PP5V_S3_REG Testpoint near J47002 Ground Testpoints near J4700

J4750 USB CARD READER

2 Ground Testpoints near J4720

FUNCTIONAL TESTPOINTS FOR MAC-1 & ICT

1 PP3V3_S3 Testpoint near J4750

1 PP3V3_S3 Testpoint near J4720

J4700 USB CAMERA


J4720 USB BLUETOOTHJ5551 ODD TEMP SENSOR

J5700 CPU FAN

J5600 ODD FAN

J5601 HD FAN

2 Ground Testpoints near J47801 PP5V_S3_REG Testpoint near J4780

J4780 IR BOARD

J4520 SATA ODD (HIGH SPEED)


1 PP5V_S0 Testpoint near J4520

J4510 SATA HDD (HIGH SPEED)


J6601 AUDIO MICROPHONE

1 Ground Testpoint near J6601

J5520 ANALOG LCD TEMP SENSOR

J5521 AMBIENT TEMP SENSOR J6602 AUDIO RIGHT SPEAKER

J6603 AUDIO LEFT SPEAKER

2 TP’S

16 TP’S

2 TP’S

110 OF 110

051-7845

A.0.0


MIN_ALLOWED_TPS=16FUNC_TEST=TRUEGND

FUNC_TEST=TRUEUSB_BT_L_P

FAN_0_GND FUNC_TEST=TRUE

FUNC_TEST=TRUEUSB_BT_L_N

USB_SDCARD_L_P FUNC_TEST=TRUE

USB_SDCARD_L_N FUNC_TEST=TRUE

FUNC_TEST=TRUEUSB_CAMERA_L_P

FUNC_TEST=TRUEUSB_CAMERA_L_N FUNC_TEST=TRUESNS_LCD_N

FUNC_TEST=TRUESNS_AMB_P

FUNC_TEST=TRUESNS_AMB_N

FUNC_TEST=TRUESNS_ODD_P

FUNC_TEST=TRUESNS_ODD_N

FUNC_TEST=TRUEFAN_0_PWR_L

FUNC_TEST=TRUEPP12V_S0_FAN0_L

FAN_2_PWR_L FUNC_TEST=TRUE

FAN_TACH2_L FUNC_TEST=TRUE

FUNC_TEST=TRUEPP12V_S0_FAN2_LFAN_2_GND FUNC_TEST=TRUE


FAN_1_PWR_L FUNC_TEST=TRUE

FAN_1_GND FUNC_TEST=TRUE

PP12V_S0_FAN1_L FUNC_TEST=TRUE

USB_IR_L_P FUNC_TEST=TRUE

USB_IR_L_N FUNC_TEST=TRUE

SATA_ODD_R2D_P FUNC_TEST=TRUE

SATA_ODD_R2D_N FUNC_TEST=TRUE

SATA_ODD_D2R_C_N FUNC_TEST=TRUE

SATA_ODD_D2R_C_P FUNC_TEST=TRUE

SMC_ODD_DETECT FUNC_TEST=TRUE

FUNC_TEST=TRUESATA_HDD_R2D_P

FUNC_TEST=TRUESATA_HDD_R2D_N

FUNC_TEST=TRUESATA_HDD_D2R_C_N

FUNC_TEST=TRUESATA_HDD_D2R_C_P

AUD_MIC_IN1_N_CONN FUNC_TEST=TRUE

GND_AUDIO_MIC1_CONN FUNC_TEST=TRUE

AUD_MIC_IN1_P_CONN FUNC_TEST=TRUE

FUNC_TEST=TRUESNS_LCD_P

AUD_SPKR_OUTLO1L_N FUNC_TEST=TRUE

AUD_SPKR_OUTLO1L_P FUNC_TEST=TRUE

AUD_SPKR_OUTLO2L_N FUNC_TEST=TRUE

AUD_SPKR_OUTLO2L_P FUNC_TEST=TRUE

AUD_SPKR_OUTLO2R_N FUNC_TEST=TRUE

AUD_SPKR_OUTLO2R_P FUNC_TEST=TRUE

AUD_SPKR_OUTLO1R_N FUNC_TEST=TRUE

AUD_SPKR_OUTLO1R_P FUNC_TEST=TRUE


PP5V_S3_REG FUNC_TEST=TRUEMIN_ALLOWED_TPS=2

PP3V3_S3 FUNC_TEST=TRUEMIN_ALLOWED_TPS=2

MIN_ALLOWED_TPS=1FUNC_TEST=TRUEPP5V_S0


K22/K23 ICT/FCT

66

66

66

102 45

102 45

102 45

102 45

78 6

49 45

102 45

102 45

102 45

102 45

108 55

108 55

108 55

108 55

108 55

108 55

103 47

103 47

73 6

78 6

56

56

56

56

57

57

57

57

56

56

56

56

103 47

103 47

103 47

103 47

103 47

103 47

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