j. parallel (synchronous) counters

18
Parallel (Synchronous ) Counters Prepared by: Bryle S. San Pedro BSIT-401 B

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Page 1: J. parallel (synchronous) counters

Parallel (Synchronous) Counters

Prepared by: Bryle S. San Pedro

BSIT-401 B

Page 2: J. parallel (synchronous) counters

What is Synchronous?

Synchronous means :Working or moving at the same rate

Having the same period and phase of oscillation or cyclic movement.

Page 3: J. parallel (synchronous) counters

What is Circuit?

Circuit means:a route around which an electrical current can flow, beginning and ending at the same point.

Page 4: J. parallel (synchronous) counters

What is Parallel (Synchronous) Counter?

In this chapter we deal with synchronous counters. From a functional point of view, synchronous counters implement finite state machines. However, we use a syntactic definition and show that every circuit that obeys these syntactic rules implements a finite state machine. Correct functionality of a synchronous counters requires satisfaction of certain timing constraints. Most importantly, all data inputs of flip-flops must be stable during the critical sections. A key advantage of the model (in which the critical section and the instability interval of each flip-flop are disjoint) is that it is possible to satisfy all the timing constraints if the clock period is sufficiently long.

Page 5: J. parallel (synchronous) counters

Synchronous Counters with decode wave forms

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In the canonic form, a synchronous counter is decomposed into three parts:

(i) the flip-flops store the state, (ii) a combinational circuit computes

the output, and (iii) a combinational circuit computes the next state.

Finally, we deal with the issue of initialization. Loosely speaking, initialization of the circuit means that the ip-ops output correct and stable values during the rst clock period.

Page 7: J. parallel (synchronous) counters

3 building blocks of a synchronous circuit:

1. combinational gates2. nets3. flip-flops

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A synchronous circuit is a circuit C composed of combinational gates, nets, and flip-flops that satisfies the following conditions:

1. There is a net called clk that carries a clock signal.

2. The clk net is fed by an input gate.3. The set of ports that are fed by the clk net

equals the set of clock-inputs of the flip-flops.

4. Define the circuit C0 as follows: The circuit C0 is obtained by (i) deleting the clk net, (ii) deleting the input gate that feeds the clk net, and (iii) replacing each flip-flop with an output gate (instead of the port D) and an input gate (instead of the port Q). We require that the circuit C0 is combinational.

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The previous condition shows like this:

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In parallel (synchronous) counters the input are pulses (or levels and pulses) with certain restrictions on pulse width and circuit propagation delay. Therefore synchronous circuits can be divided into clocked sequential circuits and uncklocked or pulsed sequential circuits.

Page 11: J. parallel (synchronous) counters

In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for its memory elements there is a(synchronizing) periodic clock connected to the clock inputs of all the memory elements of the circuit, to synchronize all internal changes of state.

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On the other hand in an unclocked or pulsed sequential circuit, such a clock is not present. Pulse mode circuits require two consecutive transitions between 0 and 1 - that is a 0-pulseor a 1 pulse to alter the circuit’s state. A pulse -mode circuit is designed to respond to pulses of certain duration; the constant signals between the pulses are null or spacer signals, which do not affect the circuit’s behavior.

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From the previous block diagrams we can note the following:

1)     Pulse outputs: For pulsed sequential circuits these occur only for the duration of the respective input pulse and in some cases for duration considerably less. For clocked sequential circuits these outputs occur for the duration of the clock pulse.

  2)     Level outputs: These change state at

the start of the respective input or clock pulse and remain in that state until the next state of output is required.

Page 16: J. parallel (synchronous) counters

A synchronous electric motor is an AC motor in which the rotation of the shaft is synchronized with the frequency of the AC supply current; the rotation period is exactly equal to an integral number of AC cycles. Synchronous motors contain electromagnets on the stator of the motor that create a magnetic field which rotates in time with the oscillations of the line current. The rotor turns in step with this field, at the same rate.

Page 17: J. parallel (synchronous) counters

Synchronous AC Motor

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THANK YOU!