introductory digital and analogue electronics .introductory digital and analogue electronics

Introductory Digital and Analogue Electronics A collection of examination problems 1991 - 2010

Magnus Danielsen (Ed.)

Contributions:

Magnus Danielsen 1991-2010 Benadikt Joensen 2008-2010

NVDRit 2010:08

Heiti / Title Introductory Digital and Analogue Electronics A collection of examination problems 1991 - 2010

Hvundar / Authors Magnus Danielsen (Ed.) Contributions: Magnus Danielsen 1991-2010 Benadikt Joensen 2008-2010

Ritslag / Report Type Teaching Material/Undirvsingartilfar

NVDRit 2010:08 Nttruvsindadeildin og hvundurin

ISSN 1601-9741 tgevari / Publisher Nttruvsindadeildin, Frskaparsetur Froya

staur / Address Natn 3, FO 100 Trshavn, Froyar (Faroe Islands) Postrm / P.O. box 2109, FO 165 Argir, Froyar (Faroe Islands)

@ +298 352550 +298 352551 nvd@setur.fo

Contents: Digital Electronics and Microprocessors:

March 2009 Electronics :

December 2008 Digital Electronics (incl. basic analogue electronics):

January 2006 January 2005 January 2003 July 2002 August 2001 January 2001 January 1999 January 1997 July 1995 January 1995 Maj 1993 January 1993 April 1991

Abstract, English Introductory Digital and Analogue Electronics A collection of examination problems 1991 2010 The problems have been used for examinations in the courses Digital Electronics (incl. basic analogue electronics), Electronics, and Digital Electronics and Microprocessors for students in BSc Electrical Engineering, and in BSc ICT-Engineering. Abstract, Faroese Innleiandi digitalur og analogur elektronikkur Savn av prvtkuuppgvum 1991-2010 Uppgvurnar hava veri settar til prvtku skeiunumm Digitalur elektronikkur(i eisini umfatar grundleggjandi analogan elektronikk), Elektronikkur og Digitalur elektronikkur og mikroprosessorar fyri studentum BSc ravmagnsverkfri, og BSc KT-verkfri.

FRSKAPARSETUR FROYA Page 1 of 5 pages (University of the Faroe Islands) Examination: Friday 13 March 2009, time: 9.00 13.00 Subject: Digital electronics and microprocessors (Digitalur elektronikkur og mikroteldur) Helping material permitted: All usual, including books. Assessment: The solutions will be assessed as a whole Problem 1. A computer delivers a string of hexadecimal digits representing two commands in a programme: 424547494E 454EC4 The contents of each pair of hexadecimal digits in the strings were intended to represent ASCII codes expanded with a leading zero. However one of the strings contains an error. 1.1 Determine which of the two strings contains an error, and explain why. Translate the correct string to the corresponding alphanumeric equivalent. Give a good suggestion for the intended alphanumeric equivalent of the erroneous string. Table 1: ASCII codes MSB LSB

000 001 010 011 100 101 110 111

0000 NUL DLE SP 0 @ P ` p 0001 SOH DC1 ! 1 A Q a q 0010 STX DC2 2 B R b r 0011 ETX DC3 # 3 C S c s 0100 EOT DC4 $ 4 D T d t 0101 ENQ NAK % 5 E U e u 0110 ACK SYN & 6 F V f v 0111 BEL ETB 7 G W g w 1000 BS CAN ( 8 H X h x 1001 HT EM ) 9 I Y i y 1010 LF SUB * : J Z j z 1011 VT ESC + ; K [ k { 1100 FF FS , < L \ l | 1101 CR GS - = M ] m } 1110 SO RS . > N N ~ 1111 SI US / ? O o DEL

Continues next page

Page 2 of 5 pages Problem 2. In fig. 2.1 is shown a VHDL programme of a state machine. Analyse this state machine answering the following questions: 2.1 How many states are in the machine, and mention their names.

Mention all input signals. Explain their function and significance for the state machine. Draw a state diagram, including indications of the control inputs.

Modify the state machine, adding a new control input y, so that the machine can be directed to run in either the original sequence, when y=0, or in the reverse sequence, when y=1. For this purpose answer the following questions: 2.2 Write additional statements to the VHDL programme, and show where in the programme

they shall be placed, so that the state machine can run in the original or the reverse sequence.

2.3 Redraw the state diagram for the modified state machine. (Hint: this question dont require solution of question 2.2)

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Page 3 of 5 pages Problem 3. The logic signals from two BCD logic circuits (BCD1 Logic and BCD2 Logic) are given as shown in fig. 3.1, and goes through a 74244 octal tri-state buffer to a D/A-converter. The 74244 is controlled from a 7400 logic gate. The actual BCD logics output values are shown in the figure. (Hint: BCD logic circuits refers to that the code on the output terminals are Binary Coded Decimal numbers) 3.1 Calculate the voltage at the output, Vout when the input control signal C is High and

Low respectively with the actual BCD logics output values as shown in the figure (BCD1 = 1001, and BCD2 = 0011) . Explain shortly what the function of the circuit is.

The 74244 is considered to be replaced by a 74LS244, a 74HC244 or a 74HCT244. 3.2 Explain some advantages with these replacements.

Explain the disadvantages with these replacements, if any.

Continues next page

15V

5V

R1 =5k

R2= 5k

Ref (+) Ref ()

DAC 0808 or MC1408

VEE

MSB A1 A2 A3 A4 A5 A6 A7 A8 LSB

5V VCC

+

R3 =16k

Fig. 3.1

Vout

7400 C

BCD2 Logic 74LS90

MSB LSB

0 0 1 1

74244 __ __ OEa OEb

Ib3 Ib2 Ib1 Ib0

BCD1 Logic 74LS90

1 0 0 1

Ia3 Ia2 Ia1 Ia0

MSB LSB

Ya3 Ya2 Ya1 Ya0

Yb3 Yb2 Yb1 Yb0

Page 4 of 5 pages

Problem 4.

In fig. 4 a device is shown, which converts a BCD-number (Binary Coded Decimal number) with the bits ABCD, where A is the MSB (most significant bit), to a 2421-code with the bits UVXY (the weights of the bits for this code are 2,4,2,1). The non-occurring combinations of the ABCD bits are supposed to result in dont care. The 2421-code is given in the table:

Decimal integer

BCD- code word

2421- code word

A B C D U V X Y 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 0 3 0 0 1 1 0 0 1 1 4 0 1 0 0 0 1 0 0 5 0 1 0 1 1 0 1 1 6 0 1 1 0 1 1 0 0 7 0 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 0 9 1 0 0 1 1 1 1 1

4.1 Find logical minimum sum of products expressions for U, V, X, and Y as functions of

A, B, C, and D. Draw logical circuits diagrams. 4.2 Find logical minimum product of sums expressions for U, V, X, and Y as functions of

A, B, C, and D. Draw logical circuit diagrams. (Hint: use Karnaugh maps)

Continues next page

MSB LSB

A B C D

U V X Y

Fig. 4

Problem 5. Page 5 of 5 pages A synchronous sequence machine shown in fig. 5.1 consists of 3 D flip-flops with clear and set signals D0 D1 D2R , R , R , and D0 D1 D2S ,S ,S respectively, and a clock signal CLK inputs. In addition the circuit contains 2 XOR gates, and 1 AND gate. The outputs Q2 Q1 Q0 run freely through a sequence of values interpreted as binary numbers (Q0 is LSB), starting with Q2 Q1 Q0 = 000. 5.1 Write up a time sequence for the inputs 2 1 0D , D , and D , the outputs 2 1 0Q ,Q , and Q , and

the output X of the AND gate. (Use e.g. a table shown in fig. 5.3). Which type of counter is it, and how many states are in a period. Which values must D0 D1 D2R , R , R , and

D0 D1 D2S ,S ,S have for free running flip-flops. Now the counter shall be modified using a combinational circuit as shown in fig. 5.2, so that it will run through the five binary states 2 6, corresponding to 2 1 0Q ,Q ,Q 010 011 100 101 110= . Notice: If question 5.1 was not answered, its result to be used in the next question can be taken to be a usual binary up-counter. 5.2 Determine the logic equations for D0 D1 D2R , R , R , and D0 D1 D2S ,S ,S as a function of the

D flip-flop outputs 2 2 1 1 0 0Q , Q , Q , Q , Q , and Q . Draw the corresponding logic circuit. Does the machine have glitches.

END

0Q 0

1Q 0

2Q 0 X

1D

2D

0D Fig. 5.3Fig.5.2

__ RD0

__ SD2

Combinational Logic Circuit

Q0 Q1 Q2 __ Q0

__ Q1

__Q2

__ RD2

__ RD1

__ SD0

__ SD1

Q0 Q1 Q2

Fig.5.1

CLK

D0 D1 D2

X

__Q0

__ Q1

__Q2

__ SD0

__ SD1

__ SD2

__ RD0

__ RD1

__ RD2

FRSKAPARSETUR FROYA Page 1 of 6 pages (University of the Faroe Islands) Examination: Friday 19 December 2008, time: 9.00 13.00 Subject: Electronics (Elektronikkur) Helping material permitted: All usual, including books. Assessment: The solutions will be assessed as a whole

Problem 2

A B C D g0 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 10 1 1 0 10 1 1 1 01 0 0 0 11 0 0 1 11 0 1 0 X1 0 1 1 X1 1 0 0 X1 1 0 1 X1 1 1 0 X1 1 1 1 X

The table is the truth table for the g-segment in aBCD-to-7-segment decoder.

2.1 Draw a Karnaugh map for the truth table andfind the minimal sum of products expression andthe minimal product of sums expression for theg segment.

2.2 Draw a circuit with only NOT- and NAND-gates that will realize the truth table.

2.3 Draw a circuit with only NOT- and NOR-gatesthat will realize the truth table.

Page 2 of 6 pages

Problem 3.