ComputerScience1541Introduc)ontoComputerArchitecture

DonaldChiarulliUniversityofPi;sburgh

HardwareDescrip7onLanguages

CompanionReading–AppendixC

HardwareDescrip7onLanguages(HDL)

Images from Patrick Schaumont Virginia Tech, http://www.ece.vt.edu/schaum/

•  Textbasedprogramminglanguagesthatdescribethebehaviorandstructure(op7onal)ofdigitalhardware.

•  Atechnologyindependentmechanismforexchangingdesigns

i.e.soHwareanalogy assembly–plaIormspecific

Highlevellang–plaIormindependent•  HDLswereinventedtoprovidethesame

portabilityfordigitaldesigns.

Verysuccessful..Digitaldesignsareregularlyre‐used/soldinintellectualpropertymarket

ModernDesignFlow

DesignCapture Func7onalSimula7on

PhysicalDesign

HardwareDescrip7onLanguage

Synthesis

Compila7onGenera7on

Designcapturetoolsarenotnecessarilytextinput

Compila7ontranslatesthedesigntoanapplica7onspecificnetlist(outputcanbeinhdl)

Synthesistranslatesthedesigntoanimplementa7onspecificformat

TwocurrentlanguagestandardsVHDL–paSernedaHerADAVerilog–morelikeC,compact,less7ghtlyconstrained

Wewilllookmorecloselyatverilog(text)

MypersonalfavoriteisVHDL

HDLversussoHwareHLLs•  Run7meseman7cs–

– HDL’sareconcurrentbydefault–  Sequen)alwithinblockconstructs

Supportmul7pleviewsofthesamedesign–  notjustmul)plesolu)ons

–  differentrepresenta)onswithdifferentlevelsofdetail

Modeling/Simula7onandsynthesis/hardwaregenera7onsupport

Verilog Datatypes •  TherearetwoprimarydatatypesinVerilog:

–  1.Awirespecifiesacombina7onalsignal.–  2.Areg(register)holdsavalue,whichcanvarywith7me.

•  Aregisterorwire,namedX,32bitswidedeclaredasanarray:•  reg[31:0]X•  wire[31:0]X

•  PossiblevaluesforaregisterorwireinVerilogare0,1,X,orZ

•  Arrayofregistersisusedforaregisterfile–  reg[31:0]registerfile[0:31]

registerfile[0] registerfile[1] registerfile[2]

registerfile[31]

VerilogOperators

•  VerilogprovidesthefullsetofunaryandbinaryoperatorsfromC–  Arithme7coperators(+,‐,*,/)–  Logicaloperators(&,|,~)–  Comparisonoperators(==,!=,>,<,<=,>=)–  ShiHoperators(<<,>>),–  Condi7onaloperator(?,usedintheformcondi7on?expr1:expr2)

•  Verilogaddsasetofunarylogicreduc7onoperators(&,|,^)–  ^Areturnsthereduc7onobtainedbyusingXORonallthebitsofA

VerilogModulesmodule half_adder (A,B,Sum,Carry); input A,B; //two 1-bit inputs output Sum, Carry; //two 1-bit outputs assign Sum = A ^ B; //sum is A xor B assign Carry = A & B; //Carry is A and B endmodule

•  ModulesaresimilartoclassesinC++–  Specifiesitsinputandoutputports

•  Con7nuousassignmentsindicatedwiththekeywordassign

•  Actslikeacombina7onallogicfunc7on:–  Outputiscon7nuouslyassignedthevalue–  “ConcurrentSeman7cs”

A B Carry

Sum half_adder

VerilogalwaysConstructs•  Formorecomplexstructures,assignstatementsmaybetedioustouse

•  UsinganalwaysblockallowstheinclusionofVerilogcontrolconstructs–  if‐then–else,casestatements,forstatements,etc.–  “Sequen7alSeman7cs”

•  alwaysblockspecifiesalistofsignalsonwhichtheblockissensi7ve–  Aliststar7ngwith@

module Mult4to1 (In1,In2,In3,In4,Sel,Out); input [31:0] In1, In2, In3, In4; /four 32-bit inputs input [1:0] Sel; //selector signal output reg [31:0] Out;// 32-bit output always @(In1, In2, In3, In4, Sel) case (Sel) //a 4->1 multiplexor 0: Out <= In1; 1: Out <= In2; 2: Out <= In3; default: Out <= In4; endcase endmodule

In1 In2 In3 In4

out

sel

Behavioralvs.StructuralHDL•  HDLscanspecifybothabehavioralandastructuraldefini7onofadigitalsystem

–  A behavioralspecifica7ondescribeshowadigitalsystemfunc7onallyoperates.–  Astructuralspecifica7ondescribesthedetailedorganiza7onofadigitalsystem

•  Witharrivalofhardwaresynthesistools,mostdesignersnowuseVerilogorVHDLtostructurallydescribeonlythedatapath–  Relyingonlogicsynthesistogeneratethelowlevellogic

•  MostCADsystemsprovideextensivelibrariesofstandardizedparts(gates,ALUs,mul7plexors,registerfiles,memories,etc.)

A B Cin Cout

S

A B Cin Cout

S

A

B Cin

Cout S 2

2

2

Full Adder

Full Adder +

StructuralVerilogExample:4‐BitRippleCarryAdder

module full_adder(a,b,ci,s,co);input a, b, ci;output s, co;

assign s = ci ^ (a ^ b); assign co = (ci & (a ^ b)) | (a & b);

endmodule

module adder_4_bit(x,y,cin,z,cout); input [3:0] x, y; input cin;output [3:0] z;output cout;wire [3:1] carry;

full_adder fa0(x[0],y[0],cin,z[0],carry[1]);full_adder fa1(x[1],y[1],carry[1],z[1],carry[2]);full_adder fa2(x[2],y[2],carry[2],z[2],carry[3]);full_adder fa3(x[3],y[3],carry[3],z[3],cout);

endmodule

StructuralVerilogExample:4‐BitRippleCarryAdder

A B Ci Co

S

A B Ci Co

S

fa0

fa1

X[0] Y[0] cin

Z[0]

carry[1]

X[1] Y[1]

Z[1]

A B Ci Co

S

A B Ci Co

S

fa2

fa3

X[2] Y[2]

Z[2]

carry[3]

X[3] Y[3]

Z[3]

carry[2] cout

adder_4_bit

cout

Z[3:0] Y[3:0]

X[3:0]

carry

BehavioralVerilogDescrip7onofMIPSALU

module MIPSALU (ALUctl, A, B, ALUOut, Zero); input [3:0] ALUctl; input [31:0] A,B; output reg [31:0] ALUOut; output Zero; assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 always @(ALUctl, A, B) begin //reevaluate if these change case (ALUctl) 0: ALUOut <= A & B; 1: ALUOut <= A | B; 2: ALUOut <= A + B; 6: ALUOut <= A - B; 7: ALUOut <= A < B ? 1 : 0; 12: ALUOut <= ~(A | B); // result is nor default: ALUOut <= 0; endcase end endmodule

•  CompleteMIPS32‐BitALUdesignedusing17linesofcode