inter APPLICATION NOTE

AP-29

August 1977

Using Ihe Inlel 8085 Serial I/ O Lines

Contents

INTRODUCTION . . . .. . . ... . ... ... . . •.. . .. . . . . .. I

MCS Famil y Members . . . .. .... . ... .• . . .. . ' . . _. _ Addili() I\. 1 8085 IIlS\rucli() ns . . . . ___ .......... . . .

I I

CRT INT ERFACE .. . _ .... , __ .... .. . • __ ... . _ . . 3

Harnware ll\ le rface _ . . . . , . . . . __ . . _ . • .. ____ . . . _ 3 Software Package .. . _ , .... . •• .. • ....... __ . . 3

OUTPUT RO UTlNE _ ... . , . .. _. _____ ____ . , 5 INPUT RO l n"lNE ... , , , ..... , , ...... 6 TlMlNGANAlYSIS. _ .... ___ .. , _ .. . .. . ,' ... 6 BAUD RAT E IDENTIFICATION ROUTINE .. , 7

CASSETTE RECOR DER INT ERFACE ...... . . , . . .. . 8

lI ardw"~ Desigl\ ___ ... __ ___ . • _ .. . ...... . ...... 8 S() fIWare • .... . . , . .. . .. .. , .. , ... . .. , __ ... 9

OUTP UT RO UTINE ... , . . . , .. .. .. , " ..... , .10 INPUT ROUTI NE. ____ _ . , ., . _ ••. • ' , ..... , . ,1 0

ADDITIONAl- COMMENTS . _ _ ... . __ _ . . .. __ __ .11

APPEN DiX .... . _. __ ' .. __ _ ... . , _ . ... • • " ....... 13

"Ill ....... " ••• """, . ......... "'-IT ' to. ' " .. , " •• , ' '',.'' '' OT' " , ... '''''~ ' '' '"" "" .... "m _"' ... OTH " ","" ... "., " CI .... ... ""'-" ' _ *'"'' co .... .,,,'. " "

INTROOUCTION

This applicalion note is intended to acquaint the read .. with the Intel- MCS-85 family, and to e~pl ain how to use One of its key features, a direct serial data link between th~ CPU and the outside world , Two design examples will be provided , a versatile m~thod for direct communications be-­tween the CPU and a CRT or other peripheral at any rate from 110 to 9600 baud, and a magnetic tape interface oyotem which allowo progr~ms and data (0 bt: Slored Or loaded USing a cheap audio cassette recorder, Both examples use software roulines 10 replace extensive external hardware and to provide add itionalllcxibility ,

MCS f amily Members

The MCS-85 family consists of the new 8085 N..:hannel, 8,bi! microprocessor (Figure I) and a variety of pariS which provide memory, in put/out­put, timing, and peripheral control capability.

" • ~

" , • ~ .... ,"'" , " .". - • " ", . .,.,,, • • " ",W' w ,- , • .~ .. ,,~ , , ",."

"' .. , • • ." ... , " " M. " - " ~

.,.-,. " " '" .. " " • -, " " '. -, " " '" -, " " " -, " " '" .. " " " -, .. " ~

00, " " , , " " , Figu .. 1. 8035 Pinout Di"".m

In many respects the 8085 can be thought of as sim ply • hardware refinement of l he e~trcme1y popular [ntel'" 8080 procelllor, which 110'"' intro­duced in 1973. It is 100% software..:ompatiblc with its predeceo.or. [n add ition to being 50% faster, many uf the external timing and con trol functions needed by the 8080A have been inte' grated into the 8085 (such as the 8224 Clock

,

Generator and the 8228 System Controller), thus reducing the syst~m part count. Addili<Jnal fea· tures indude four add itional m~skable and non­masbble interrupt pins, increased drive capability, and two new in put ~nd ou tput line$. These pins, called SID and SOD, provide • serial [/ 0 data link with the CPU. The 8085 uses a standard 40-pin OIP p.d,agc.

All mem bt:rs o f the MCS-85 family req uire a single 5-"0[t power supply, greatly reducing syste m o .. er­head . Several components combine a number of system funclions (e.K., ROM and I/O), allowing a complete, useful microcom puter system to be assembled with as few as three integrated circuits, as ~hown in Figure 2. For example, the 8155 and 8 156 RAM /IOfTIMER chips each con tain 256 8·bi t bytes o f program or data storage, three pro­grammable I/O ports, and a 14-M timer/counter.

Since the in ternal architectu.-e and inslruction scI of the 8085 i~ an ex tension o f that of the 8080, aU software wnnen for tlle 8080 - incl uding com· piler.;, assembler.;, and individual applications programs - will run without modification On the new processor. In facl, the complete upward COm· patibility of the MCS-85 sy,;tem means that appli­cation$ designed around t he 8080 can be converted to using Ihe 8085 al mini mal COSI, requiring linl. hardware redesign or program modification. An engineer alre ady familiar wilh the 8080 will no t need to learn a new arch itecture or l~nemon ics .

Companies now USing In ters extensive line o f design, dewlopmenl, and debugging tools can aug· ment their system, with a series of 8085 support prodUCIS (such as Ihe SDK·8S, ICE-85, and SHC boards) which an.: compatible with their pr~sent mainframe and peripherals .

Add itiuna l 8085 Inst ructions

The additional hardware featur", of the 8085 (handling multip1e-level maskablo interrupts and .. rial I/O) are ~upported with two new instruc­liom. R[M (machine code 20H) is us~d to read the current SI~lus oflhe three interrupt masks into the accum ulator. Add itional bits are set to .how what in terrupts (if any ) are pending, and thologic. l !latc o f the SID inpul pin (pin 5). The complement of RIM is SI'" ( mach ine code 3011), which has a dual function depending on the current accumulator contents. If bits 3 or 4 of the accumulator are a logical one, SIM ~an be used 10 change Ihe three

interrupt mash; if bit 6~1, SIM can ~t tile SOD output (pin 4), The two funclions of the S[M instruction operdte independently , (If, at this point, the acronyms RIM, SIM, SID, and SOD are slarling to blur in your mind, try to remember thei r ro(>(s instead: Read Interrupt Mask, ScI Inter­rupt Mask, Seria[ In put Data , and Seria[ Output Data. Don't worry: of the other four ordered permutations of R&S, 1&0, and M&D, only ROM is used else where in this note , and then only in its traditional .... nse .)

r Of-] v" "",

I I I " " " . IR ..

_. ''''.' ...

= ...... - -f:: "."'~ w - .... , l-,",, ..,.. .-., WJ ,

"""" i:.f:""'" "" .. ..". "" <l'

:1 .. n " -, .. > ~

• _ .

,0 .. .co _ .

Ik , ..

~i"" _. " lOIII , ..... ~

... fJ ~

~ .. ", > _.

" " •

~; .. --0.,., .... - ." , .. ""' .,

H ,,, ,lU-

1+ '.

Figu,. 2. 8085 Mini"",m Sy".m

,

A detailed e ~planation of tile accumulator con­t~nts after and before RIM and SIM is gjven ;n Figu,," 3. The [/0 pins both function witll respect to positive logic : a "I" in the accumulator corre­sponds to a high ,0I1a8" level, "0" to a [ever near ground . The SID and SOD lines arc elect rically compatible with nonn al TIL logic [evels . (For full e[tctrical specifications, tile teadu should co" , ul1 the MCS-8 S User's Man ua!.) If A6 is "0" prior to e ~ecut inl! SIlt! , SOD will remain unchan8"d, regardk<s of the stat~ of "'" Aft. r a R.",t, SOD will be low. It should be noted that RIM does not affect the Sign Flag; in order to m.ke a conditional jum p based on Ihe Serial Input Data state , • th,..,. inst ruction seq uonce should be used, ,uch as shown in Exa mples I and 2. When seria l da r. is to be aSllemblcd into. parallel word, a sequence such as in Example 3 can be used, wh ich shifts the Con­tents of register pair HL One bit to the left and appends t he input data bi t .

, • -, 1· 1· 1' 1· 1010 1·1 · 1 , • , , , • , ,

~.-"""T'N' -.. .. .. • ... - - , ." ... "" , ,

I L ..,.:..... .... , .... _._ .....

< ..... , _.-.0-... " . • ..... " .. ---- .. ,.

[$~I~:~' ~' ~I ~' ~I ,~I~,~I~,~,~I~:~I~ =;'TOO .:.... , .:. ":' ., .. ~. ~ ,.".. , ?

' ''''' .. , ".". . "".. ..-

~ "" .. ~ .. .. ... "" " ----_ ..........

FI!I<I'.l. EIf«, 01 RIM .oo SIM Innru<,ions

Thi' note does not COncern itself with tile interrupt mask manipulation also made possible with RIM and SIM: for a full understanding of the intelrupt cap.bi lilie, of the 8085, see the User'. Manual. To use SIM for alto ring th e SOD statc without f ... of in terfcring wit h the in terrupt mask ,tatus, One nee"; only make sure that bits 3 .nd 4 of the accumulator a~ se t to zero first .

£) JItf'i. E ~.

'" ""

:1':£1'1) ~ lD If¥£L SET SIGN fl.i% 1~ ~l'=1

, Jl.tf' IF S10 WAS MIG!, ''. ElSE COOTliU .

;"!I(> Sl& ,!tM R7 INTD (')/ "' " SfWIU: ; Cft.L SEf1\'I CE ROOTIIE

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'" PI ~

"' "' ,.,

"' "' I, P. .. '" ... ., .. ",

J ' , If Sl~ WAS ll'l, ; \ T~~ fOOUl£.

; !'£IIl SW fi'!TR SII ;!tM li'!,P' T!flO CY

; f'(!T~T~ ()<,'iJ'fU)I ; I,INICH ; (!tiT IIf..(

On the following pages, example, are gi>en show­ing two possible uses o f the SID and SOO lines. The main purpose of these examples is not to gh'e the reader a de~igtl an~r which he could mod el his Own system - though, of cOUlse. this migh t be the case _ but rather 10 illustrate Ihe hardware and softwa re inlerfaces and lechniquos necessa ry 10 imp lement a typical working subsy~lem.

CRT IJ'<TERF ACE

Mo~t microprocessor systems require some son of serial commu nication •. This may be selected for reasons of economy (to redu ce the number of interconnections required in a distribu ted system). or it may be necessary in order to commu ni cate wit h such COmmOn peripheral< a, CRT's or tele­typewriters .

These peripherals all use a standard conve ntion for transmilting serial ASCII code. Each dala byte is transmiUed as a series of 10 or 11 bits , The uni­form time [>'O r bit corresponds to the data trans­mission rate . For e~ample, if the t ran~miss.ion rate is to be 2400 baud (2400 bils per secood). each bit time mu,t be 1/2400 bp,= 4 16.7 j.(sec/bi t , The ,tandard 100bit .. queoce con:list~ of a logically

ze ro "Start" bit , 8 data b i t~ (least <ignifie>.nt bit first) , and one or more stop bit. (logic I ), An I l ·bi t sequence with tw o sto p bits is used for I I 0 baud TTY·s. The logic one I.vel contin ues until tit. start bit of the nex t byte to enSure Ih.t each 100bit sequence is init iated wit h a one-I()-zero lransition . The 8 bit~ lron~ferred migh t be raw bi nary data or alphanu meric characters using Ihe standard ASal code. [n tltis case. the most signi ficant bit - th. la,t data bit t ransmitted _ will depend on th parity con'~n tion being u<ed, This sequence is illust rated for the ASCII "space" cnaracter in Figure 4.

•••

-<i~-,-,-;--.,.-fVJ 11 1 11 11 .1 11 ------- - - -.,,"'.. ... "> .., ... ... ... " "". ." ~ ...

FiguT. 4. ASCII SJ>iI" a.ota<te •

The algorithm for re ceivi ng ~erial code involve~ sam plin& the incoming data at the midd le of each bi t time . The eight sampled values are sh ifted into a serial byte corresponding to the data originall~ transmitted. The OM·to-zerO transition at th. beginning of each byte makes it poSSible to syn· chronize the sampling points relative to the start o f eaclt data sequence.

Hardware I nterfa~e

[n general, any seria l communications system win r<:quire both hardware and software in terface~. Since t he SOD line ca~ drive on ly one lTL 10~d.

additio ll al cu rren I and voltage huffering is required to be compatible wilh the RS-232C in terface standard used by mo~t periph .. als. A schematic [OJ

achieving this buffe ri ng is shown in Figu r<: 5. The MCI4gS .nd MC 14S9 circui ts interface posi tive logic TTL signals with the RS-232 high voltage invert ed logic levels,

Software Package

The wftware need ed to d rive the CRT interfa ce i, divid ed into three parts . All three use software timing and delay Ioors , with foxed and va riable paramet~rs . I" conjunction , they are able to identi fy incoming signals at any rate from be low 11 0 to over 9600 baud arid respond at the same rate.

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~ , • ,. • • c ..........

• .. " " ::'Q .. , ••• ".".".'p".o.".o,O,Q • o " --

* - -T -"" " ,

-• , -D '

~F~ : -.. ":r- " " --, -

"

fig~ .. 5. RS-232C '"tor ''''' Schom.tic

Upon power-up or resel, or when {he console device baud rate is changed, th e baud rate identifi­cation subroutine (BRID) is calJed. This routine wait, until an ASCII 'pace character (20H) i. received from the console. (Any olh(, character will result in a case of mistaken identification. ) When • space character is received. lwo time parameters a", computed which CQrrespond to the bi t li me and one-half the bit time of the baud rate h";ng used _ These are s{oTtd as "ariabl~s BITfIME and HAlFlllT . To output a charael. r to the con­sole, the character code is placed in register C, and the suhr<.>ut;ne COUT is called. 11>;$ routine ~StS

BITTIME a, a parameter for the software delay loop wttich determ ines the baud rale. To accepl a charaCler from the keyboard. CIN is called. CIN r~tums after the next hy is ty ped. with the corre­spond ing character oode in register C. ON uses both parameter.; OllTIME and HALFB IT .

Since COUT and CIN u"" time parnmetcr.; com­puted by BRID. they will function al a rale the same as that of the initial ,pace character input. Because of the nature o f the software. Ihe rate docs not depend on the CPU clock frequency . This

•

results in additional IIc~ibiljty in the following respects'

I . The software dots not need to be modified if the 8085 crystal frequency is changed or Wai t states are added .

1. SinU! Ihe lime base is no long~r crilical. the quartz crystal could be replaced by a less expensive RC network. provided the fre­quency does not drift by more than a few p<:rcent during a wssion . Additional drift can 00 accommodated by periodically recalling the BRIO routine.

3. Communication is possible at non-standard baud rates which relaxes the constraints on system periphe rals.

It should be noted. though. Ihat slowing down the CPU clock will decrease its throughput proportion· ate ly . In addition . it will degrade the maximum resolution of the delay loups , with the result that rhe highest baud rates may no longer be achievable.

A mOre detailed analysis of the CRT interface ro utines will be presented in the order of increasing complexity : COln. CIN. and BRID. Since SID and

SOD are ideal for many application~ which. inyol"" critical I/O timing, the tim ing techniques used here may be of interest to softwart designers, Accord, ingly, Ihe mathematical deriy,tion of the timing parameters is induded in this analysis, as well as a justification far the BRID algorilhm _ The algebra inyalved might be a bit 100 tedious for designers uncon cerned with generating soflware delays. J f so, they (and other bored 'eaders) haye the freedom of choice to skip over the sectioM they find ohjec­tionable .

OUTPUT ROUTINE

h would seem n. turallO write dat. in th~ standard format in three stages: o utput a zero start bit, then the 8 data bits (Using a loop sequence), th en the stop bit s. Each stage would incorporate it. Own appropriate delay and output sections, leading to unnecessary d uplication_ Instead, the code below executes the same main loop t 1 times . Its bit manipulation routine inherently results in the Cor­rect data sequence being formed. It accomplishes this by using the carry and C register as a 9·bit pseudo·circular shift register . Initially CY-o. The algorithm outputs CY, wailS one bit time, se ts CY"I, an d then totates the pseudo·register right one bit. This repealS for 11 cycles. On the tenth and all subsequent loops, the output bit will be a logical one, since that bit had been set nine loops earlier while in the CY (see Figur~ 6).

When com is called the registers to be used must be preserved and interru pt' disabled so the timing loop will not be disr upted . Clear the CY in prepara­tion for outputting the start bit, and set the loop coun ter for 11 bilS (if 110 baud will never be used, the countCT wuld be set 10 10) :

"m "" , "'" " " ~ • ~I 8· 11

Output of the cotltents of the CY :

The numbers in brackets indicate bow many rna­cine cydes are required for each instruclion. They will be referred to in the liming analys;" sec tion .

,

-..... ,," ., ...... ., '" D, .. --c, , coo ., .. , '"

« ... , ., .. Do ... , Do ., __ c -coo -, ...

-I ' I, 1",1 .. 1"1<><1 0.1"'1 __ c

'c .-----. _c_ - • coo -

"" " 1" " .

c

"'-1,1 , 1, 1,1 , 1, 1,1+ + ,,"".T.

_L;J "". . .. . --.._._-- .

Get sluck in a loop for the app ropriat e time (don't worry for now how "'a IITIME" is determined) :

~. eITT!!f: (16)

CUl '" , i t. ) ,. COl i ~)

'" " ," ., l')Z (0)

Rotate the contents of register C right into the CY, while mOving a one in to the ldt end. Continue until all bits have been transmitted,

<CO m

'" " ( 4:' ~ '" '" C. (~)

"' • (4)

"" "' (1e>

Restore processor status ~nd return :

INPUT ROlJTlNE

" •

The console input routine US<$ the opposit~ pro­cedure ; instead of moving a b it from I~giS\e[ C \0 Ihe CY. then 10 A, . Ilten 10 SOD. C1N loads a bit from SID in10 A7, tlten mOWS it 10 CY, then in l<) register C.

First, SCI up Ihe CPU 35 before :

em " ., When a starl bit transition arrives, the first ~"m­

pIing should not be taken until the middle of the first data bit , One and one-half b it limes after the transition. Await the start bit transition, then set up lite delay parameler for one-half bi t time :

CIt - "" ... ';7)

{1i>

Loop for one-half bi t time before starting 10 sam ple data:

, '" " CI2

Wait until Ihe middle of th e 1l<x1 bit before Sam­pling SID. the" move Ihe data bit inlo CY:

en "<0 ernu£ ~IP

0 4: "' , (~)

"" 0. '" '" " ':~i

"" W ", R!~ (4)

"' (4)

l)ecrement '", bit cou nter. " this '" '", ninth. c)'cle, the 8 data bits are in register C, so quil (the firsl stop bil will already have been received, and be in CY):

• '"

•

Otherwise, continue. Rol .I. Ihe data bi l righl inlo regisIer C, and repeallhe cycle:

" ., ( 4) ,. m

'" c. '" ., '" ,~ en (1~)

(A NOP is ,,«ded 10 ma ke Ihe COUT and CIN loops exact ly equal in nu mber of machine c ycl~s, so thaI each can use the ... me delay parameter .) Restore statu' and return. ..

" ., TIMING ANAL YSIS

"

COUT and CIN now need to be provided with parameters for B1TT1ME and HALFB1T 11 can b. seen from Ihe above code Ihal each rouline uses 61 + 0 machine cycl~s per inpul OJ outpul bil , where 0 is Ihe number of cycles spent in either four line delay segmen t. If (H) and (L) a,.., the conten ls of Ihe Hand L registers going inlO Ihis seclion of code, then :

o ~ 22+«U - 1)X 14+«H)-I)X

1(255 X 14) + 151

, , If(U) _ (] I) _ I , (U_(U _I ,and

(HU' '" 256 (H)' + (U' then ,

D·22 + 14(L)+3595(J1)

This can be approximated by;

o = 22 + 14(HU

,

OJ

(2)

(3)

", This approximation is exact for (H) = 0; otherwise, it is accurate to wil h in 0.3%. Thus each loop of COUT Or CIN us<:s a tOlal of:

, C = 61 + D = 83 + 14 (HU machine cycles (5)

Each machine cycle uses Iwo "1)151.1 cycles in the 8085. $0 the result ing data rale is;

-B • cycle frequency

C

(cryst~l frcquency)72

83 + 14 <Hu' ",

For a typical calculation, $ee Exampte 4.

EXAM~LE 4

To p.ooUot 2400 baud with tilt "an1.,d 6, 144 MI! , ery,,,I:

(tIl)'

• (6.144 )( 106) + 2

8) + 14 (HI)'

• ( 6 , 144 )( 1(l6i2) _ ", "00

~ [(61442~o:t+2) _ 8 3] ~ 1 4 "85,5 .. 80

.. 8610 " 0056H

.. 015111 .. ~ ITI[ME

To det"''';nt Iho I,,," d.t. "t. Ih;, p".mo,e, will prod""", . ub"i'u'e i,,'o .., •• 1;0" (6):

DUe ROIo .. •\'c·c·;''ol,~o·ii·"' 83 + [4(86)

.. 23 87 b.ud, which is 0,)4~ ' low.

for 9600 bmd, til ... ",. <.leul'li"n, will yi.ld (HI)'

.. 17, which j • • ct".ily O,J"" .. ,,":. ,;",Ii", 19200 ba ud or 38400 baud could eoch b' teno"ted to with_ i" S% if {HI)' - 6 or 0' Tool< I pre .. "" Iho poram, 01", fo, ,."".1 ".nd" d 0.u1 " ' e •.

Notice that the resolution o f the delay algorith m ­the difference between hit times result ing from parametc~ which differ by one _ i~ 14 machine cycles. As a result , the true bit delay produced can always manage to be with in ±2.3 "see of the de lay

Tablo 1

desired . This guarant ees that at rates up to 9600 baud, where each bit time is at leasl 104 I'secwide, some value of B I TTI~I E can be found which will be accura te to with in 2.2%.

BAUD RATE ID ENTIFICATION ROUTINF-

The function of BRID is to compute the appropri­ate parame ters BITTIME and HALFBIT. It aCcom­plishes this by observing the data pane", TCceivcd when the spa~ bar is pressed on the console device . Since a space character has the ASCII code 20H ,. OO IOOOOOB. the pa l1ern represented back in Figure 4 is tnmsmitted. Notice that the initial zero level is 6 bits wide , Suppose it could be detemlined that this COITc-spond, to M machine cycle<, l nen one bit would correspo nd to (M-;-6) machine cycles. The reaSon for d ividing down a space ,"veral bits long is SO that any distorlion caused by the signal ri.e and fall tirnes, or any lack of pte­cision in detecting Ih e two transitions, will be TCduced by a fac tor of !>i x. Since tht bit ~riod of

• CO UT and C1 N is g3 + 14 (Ill). BRID must gener-ate a value (]IU' such th at:

M+6 ~ S3+ 14 (HU'

• <HU • (M -;-6)-S3

" <HI)' " . " - 6 (approximately)

(8)

(9)

This value can be detenninl"<l by set ting register pair HL to -6, then incn:menting it once every S4 machine cycles during t he period that the incom-

OELAV PARAMETE RS FOR STANOAAO BANO RATES USING 6.14~ MH. CRVSTAl

TARG~T • (HU o r ACTUAl (HL) 1. {H U "

, ~"' BITTI ME HAlFan BAUOIlATE RATE

IS .. T ... / {s .. Tadl (s .. lu.) PRODUCEO ERROR

"0 "" 0 )C5 0= ~" IO\UI9 _0006 ,~ 145) 050t 00" 00" 149.99 -0.005

'00 ,~ o~ OJD7 o~, 299 ,80 - 0.008 ... "0 0 .. ' " .. OtA5 599.6 5 -0059

" 00 on ~, 0 162 Ot59 1199,5 - 0,()J9

~OO M OO~ 0157 a t :lC :13869 _0.&47 .... '" 00'" mn 0115 47n.6 _0.4 69

0000 " 00" 0112 moo 9570.1 - 0.312

t9200 • ~ 0107 m~ t8395.2 -4.31

,

in, signal is leTO. RlTT[ME is then obtained by indi.idoally incremenling registers Hand L. To oblain HALFBIT, divide the value of <BU' deler­mined above by two before incrementing each register .

[n order 10 implement this algorithm, set HL to - 6,

verify that t he incoming signal is a logic one, th"" wait for the start bit tramilion.

BRIO: ~, , ... ". l~1 "~ am : .. , '"

, • BPI1 ... .. , • ."

Increment register pair HL, then delay so Illat each cycle will require 84 machine cycles :

BIlE ,~ " '" ~, E, e-\M (7)

f>:14 ' "" , (51)

'" ." ," ) o,eck if SID is still [ow. [f so, repe at:

'" '" .. , '" • ." (1~)

Oth~rwise wntinue. Store lIL temporarily for the IIALFBIT calculation. Obtain and sto,", B1TT[ME:

""' " [II': ~ ,~ , SIU 8[Tl1~

Restore HL, calculate HALFIlIT, and relum : .. " .. , .. A, H .. "" ", , .. , , .. "" ,,' 111': " ,~ , "'> HfUen .,

•

The assembled lislings for th ese subroutines, alonll with a sim ple rest program, is p,",sented in the Appe nd ix ,

CASSETTE RECORIJER INTERfACE

There are many situations where data has to be transn,itted Ihroogh a non-ideal medium. To give three Iypical example" a system wit h electrically isolated elements might require thaI signals be AC coupled, C<lmmunicati"n, through. an audio nel­work (such as te lephone or radio) are gtoatly band­wid th limited, and some applications (such as a distributed network in an industrial environment) must lokrate random electrical noise, Attempting to record data on a cheap casset te recorder (the One used for th is note cost S17.OO) will reveal all of these shortcomings, plos one: The wp;: speed fluctuates significanlly and varies as the batteries run down, hence the data rate is inconsistent,

The recording ~chcme used here make. very few demands on the transmission med ium. It makes no attempt 10 uansmit DC voltage levels. Instead, data is transmiHod by a series of variable lenzlh tone bursts. The dominant frequency of the tone used can be selected to be wilhin Ihe passband of the particular medium. Data is lransmitted with each bil composed of a tone bu~t followed by a pause. The firsl lhird of a bit period is a lways a lone burst, the middle third is either a tone bu~1 con­tinuou, wil li the filSl Or a pause corresponding to , respectively, a one or zero, and the final third is always a pause, as shown in Figure 7. Thus, dala is d istinguished by the bUIst/paUse ratio.

Hartlware Design

These tone bursts are obtained from the 8085 SOD line, using analog signal wnditioning to elimina!e the DC component of lhe wavefonn . (This low freq uency component is due 10 the single-endcd nature of tile SOD line ; it's devialions from ground are all pOSitive. which unbalances the capacitive input <rage of the ",corder.) A suggested in krface circuit is shown in Figure 8, using one LM324 quad op amp and a few standard value discrete component' which should be available in even a digilal design laboratory . On playback, analog cir­cuilry is again u$ed to delect t he presence of a tone burst , In Figur~ 8, A2 buffers the incoming signal, and A3 inveTlS it. The pcaks of these Iwo signals are t ransm itted throuih [) I or 02 and are filtered by an RC network , Comparator A4 !hen squares up the output and produces the logic signal read

by Ihe SID pin. Since Ihe o p am ps are powered by the si ngle S·volt $uppl y, a 2 .0·volt refe rence lev. l is obtained fro m 3 resistive voltage divider. The waveforms present at several points in Ihe ci rcuit are shown in Figure 9 .

s<'ftware

The algorit hm for reading a dala bit off the tape is $i mple and straightforward : If the lone burst is

longer than the pause , the bit is a Oll e . Olherwi"". it is a zero . Since only the li me ralio is considered, any vari ation in tape speed will not affect the data determination.

0" . ... ·

._. ,;--:;:-' ., -

-

VOLUME CONTROL

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After the CRT software analylois, 11K tlpe rou tines ...., almall trivial. TAPEO is a lubrou line for 011\' puUinl the rootenu of ugi'<ler C to a CI_lIe reoorder. T APElN reads 8 bilS in \0 teeister C.

OUTPlfI'ROlfTlNE

TAPEO calls I SIIbroutine named BURST three l,mes for each bit If A6 (the SOD enable bit ) is $01: 1 when Il URST i. called , " square·wave lone burs t will Ix tran lmi lled . If A<; is not 5<:\ , IlU~ ST simply de lays fo r exactly the ~mc ~mou nl of time before re lurnina_ The th..,. call. Ire used 10. respj:e tiyely, output the ini tial bUISt, output Ih. dati bUrst/SPice, Dnd creale Ihe space a t the end of nell bit. Nine bits will be output; Ihe ci&h t data hilS (LSD fint) followed by a uro bi t . The st,,1 or the ;n,lial bunt of Ihe lrailiol zero is needed to mal k Ihe end of Ihe rlllal space of I"" p",cedinS dUI bit,

Starl each bit by outpulling a lone bursl :

TFf'Ell MIlT TOl : MY!

CA' " .... ""

Rotat. regisler C through CY:

... ". ...

Mo ve CY to the SOD enable b1l position. A6_ Simultaneously "" t A, to one. and dear all olher bilS. OUlput • tone bursl or space, d Cp"nding on the previous conlen ts ofCY:

Ckar tIM: lICcumuL:nor.and ou lpull space:

'" . "" ... S<

Keep Welin, unlil Ihe fun 9-bil ",'!u.nce: i~ fin­i.tled:

• '"

The BURST subroutine e~ecu l CS Ihe SIM in· struction CYCNO times. 1\ interval! of 29 + 14 (J-IA LFCYO machine cycles. In be l""een each SIM, bil 1\7 is complemented. CYCNO should be an evell number. If A6 is set upon calli", BURST a sq.u • ..,·""ave will be c..,.ted. Otherwise, Ihe »me cod. sequence i. followed but SOD does nol change - thus a space resu lts ,

• • S< ~, M\\)j() '" "' ;c. '" ., E. fiUCYC '" "" ... , '" ,. .. (MID .. .. '" '" • '" ,.

"" Ollf>

'" {Ie}

INPUT ROUTIN E

TAPEIN ~ a sub.outine caJled BITIN to mo'". Ihe <lUI at the SID pin in to the CY. The maximum .... te a' which SID is ",ad ii limIted by • delay loop ill S ITIN.

Initialize the bit coun ler and lhe regis ter D. which wi!! keep track of th e lone burst time. If a tone

bUrsl is bei~g received when TAPEIN is called. wait until the burst is ove r:

TiffiN ~I • 8

'" V. !l\iI1

'" Ci'U ~iTW

X ill au W IN K HI

(ThroUgJlOut this subrou tine. a level tran.i 1io~ i. recognized only .fler it h •• been read once inilially and then verified on the nex t reading. This pro­vide. somr dC81M o f software no;" immuni ty. ) Now .wait Ihe .t.rl o f Ihe next bursl :

m m: liZ ~L BJ;JH JI(: 112

The next burst has nOw arrived . Keep reading Ihe SID pin. decrementi ng register D (thus making it more negative). each cycle until th e pause is detected:

m "' ,

lOU ~i!l~

" 113 (fill. BIlIH , Tl,

Now continue reading the SID pin. incrementing the D register (back towards zero), each cyde until the ne xt burst is received:

'" '" , "" miN J~~ '" '" BlIIN

" '" Now. if the burst lasted longer than the space, D was not incremented all Ihe way back to lero; it is still negative . If the spa~ was longer. D was incre· mented up through zero; it i, now positive . In other words, the Sign bit of D will now corrcspond to the data bit that wo uld lead 10 each of these ~ull, . Move the sign bit into the CY, then rOlate it in to register C:

'" " '" '" " 8~ ., "' ., ~, "'"

"

Conlinue until t he last bit has been received:

"" . m2 Tn

"' (Noti~ that the first hal f of this su broutine is incorporated in the second haIr. In fact , the as· sembled li,ting included in Ihe Appendix make, use o f this fact to elimi nate 24 bytes of dupl icated code.)

8ITlN waits a short time in order to regulate the sampling rate, Ihen reads SID and move~ the data bit into the CY:

BlTlN ' '" E, o;IIlH£ G )

'" '" ,

'" ,. '" (7/1~)

RIM W

"- ,~ >

RC:T (f~)

The tone burst frequency and durution. and the TAPEIN sampling rale arc determined by HALFCYC, CYCNO, and CKRATE Tables 2 and 3 give t}·pical value, .

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AU ""'U IN ,",elM"

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Tobit 3

MAXIMUM SAMP LI NG RATES FOR VARtOUS VALUE S OF

CKRATE

CKRATE SAMnlNG RATE

(lNCLUDtNG VALUE

CALL & RET) , 17.6 -, ~ ". , .. ~ '" , .. ,~ 1.14m....,

,-cYCIMJ ...

~ ----

T~e Appendix also includes a simple block record routine utilizing T APEO. Before calling llLKRCD, HL mUlt be &<:t to the start of the desired block, and the recorder turned on manually. Succel><ive bytes will be recorded until the end of that page, i.e ., until L is incr~meJlted to UfO. The playback routine r"quir~s presetting ilL to the target address and turning on tne rccomer before PlAYlIK is called. These routines incorporate a long tone burst before each data block to allow a record er with Automatic Gain Control to stab iJi.e befof~ the data stans.

ADD ITIONAL CO,\Ift-I ENTS

The two design examples given SO far were bu ilt up using an SDK-SS System Design Kit Both hard­ware in terfaces were wire-wrapped on the ample breadboarding area provided on the board. The connection. between SID and SOD and tt,. On· board TTY interface were broten, so as not to affect the 8085 I/O electrical characteristics.

The CRT in terface waS tested with a Beehive Mini­Be~ II Terminal in the full duplex mode at each of its 14 possible transmission rat~s. from 110 to 9600 baud. II was also checked out at 19200 baud using a Beehive B-1OO Terminal. In addiTion, Th e software was exer(ised using an SBC 80/20 .y.lem as a variable baud rate character gen~rator and receIver.

An additional advantage to having software sele(t­able communications rates is that it would be pos­sible to communicate wit h several system periper­also each at its OWn prefe",:d wle, without having to duplicate hardware. For example , the addition of a single 7408 AND gate and an outp.,t port (such as on the 8155) would make it possib le to USe the same two RS-232 drcuits to interface with up to seven I/O devices(see Figure 10). Thru of the MC1488 dn.ers ha>. Enable inputs which can be controlled by the output port. One AND gate can be used to buffer the SOD line and drin Ihe MCI488 Data inputs, The rest of the 7408 can be configured as a four input At"1D gate . This would act as.n inverted logic 0 1{ gate!o reduce the four MCI489 receiver outpuTS to a single line, which coutd be rud by the SID. This assumes that only One input device (CRT, PTR) at a time will be used (which is usually the case in a non-time shared. interactivc application), and that Ihe unused devices are transmitting a logic one level (which 'hould also be tho ""-,,,).

"

.... . ,,..

"1',--...... ,,,. " ".

" ....... "'" -~.

-Fig~r. to. lMerlt<:i"i 8085 to Mu ltiple P., iph ... h

The software needed to support add itional periph­eral, would be simple and straightforw~rd. A routine int~ndcd to dump a section of memory 10 a paper tape punch, for example. would first have to store BIITIME and HALF BIT somewhere (per. haps on stack), load the variables with nCw paramo eters corresponding to the paper tape punch rate, and then write a bit pattern to the output port which would disable the console driver and enable the punch (and pethaps a typewriter). After the dump was over. the original time parameters and dri,"CT status would be restored.

As explained before, the BRIO routine computed fate parameters based on Ihe faCT that an A$Cll "space" charaCTer re,ulted in • zero level 6 bits long , Conceivably, some obscure p~ripherals might produce • transient between successive zero bit • . (This might be the ca'<', for example, if the signal was produced by mechanical rather than electronic means.) If so. Ibe BR IO algorit~m used here prob­ably would not work reliably. Once the two time parameters we re identified. though, COUT and CIN could still be used. An al ternate algorithm for baud rate identification would require a table in ROM (note th e fiftb and final R/5-I/Q-M /I) permu· tation). This table would contain a list of delay parameters corresponding to the standard trans",is·

sion rates, as computed for tile sdected elYstal fre<:! uency, Initialization would require th e oper­ator to hit a specific key s<verallimes(usually the "U" key, which generates a pattern of a1ternatinK ones and zeros). The identification routine would attempt to '"read n Ihis pattern at each baud rate, in turn . until find ing t he ra te at which the read was succ<:ssful.

The cassellC recorder used to dc,clop the tape interface was a Uoyd's push-button model which COSt S17 in 1972. Empirical testing has indicated thai for Ihis application. the quality of t he cassette recorder is less cri tical than the quality of Ihe tape its<l f. In other words, some 33~ cassettes were not very reliable, even when u,"d with mOre expensive recorders.

When using a cassette a! the beginnin g o f a side. allo w Ihe lape to run for about 10 ,"conds until the leader has passed befo re starting to write data. Otherwise , data will be lost to the leader,

Depending on the recorder quali ty. Ihe tone burst freq uency and duration can be optimized for higher data rates by modifying HA LFCYC and CYCNO. If sO, CKRATE should also be reduced, so that between about 10 and gO data sampl ingS are made during a sin gle (one-third width ) tone bUl'$t . At grea tl y increased fre quencies, some of the

components in the analog interface might also be mod ified ,

The two simpte rout ines fo r recording and playing back blocks of data Were in tended 10 illustrate o ne way of using TAPEIN and TAPEO, and Ihe",fore do not contain any provisions for errOl detec tion 01 corre ction. De pending on the nature of a partic­ular apphcation. (hese routines ~ould be aug­mented with parity bit or checksum comparison, Of an errOr correcting code technique.

Funny things happcn whcn recording and playing back a page of RA M whic h includes th~ subroutine Slack. Eventually, PLA YB K will start writing m'er the data at the top of the ,tack, destroying the subroutine t!""dc<:back sequence. The ne xt RET instruction will t hen cause a jump to a place where you'd rather not be .

The printout ",produced in the Appendix includes the assembled listi ngS for the CRT and magnetic tape inte rfaces d i,cussed in th is application nOk The object code produced was programmed into an 8755 EPROM. which was installe<l in the expan­sion PROM w cket of Ihe SDK-8S board , Som~ ""IY minor differenCl:s c~i st between this lis ti ng and the code segments presented earlier, wh ich were written for ma~imum clarit y,

APPENDIX

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