institut für angewandte mikroelektronik und datentechnik phase 5 architectural impact on asic and...

Institut fürAngewandte

Mikroelektronikund Datentechnik

Phase 5Architectural impact on ASIC and FPGA

Nils Büscher

Selected Topics in VLSI Design(Module 24513)

26.04.23 © 2013 UNIVERSITÄT ROSTOCK | Fakultät für Informatik und Elektrotechnik 1





Contents1. Differences in Hardware2. Impact of Hardware-Description3. Examples4. Impact on Performance5. Conclusions

26.04.23 2© 2013 UNIVERSITÄT ROSTOCK | Fakultät für Informatik und Elektrotechnik





1.1 Differences in Hardware


Hardware of an FPGA





1.1 Differences in Hardware


Hardware of an FPGA

– Functionality realised with Basic Logic Blocks (BLE)

– BLE connection via switch-matrices

– ~90% of the area of an FPGA is used for wiring and interconnection

– Additional elements for FPGA (e.g. DSP, Adder, Multiplier,

Microcontroller, RAM-Cells)

– Configuration stored in SRAM or persistent EEPROM





1.2 Differences in HardwareHardware of an ASIC

– No predifined structure

– Logical functions are realizeddirectly with transitors or standard-cells

– Wiring is done between the cellson additinal layers

– Size of the design mostly infuenced by number of cells





2. Impact of Hardware-Description


Impact on FPGA– Architecture can use specialized cells in the FPGA(e.g. Adder, Multiplier, DSPs, RAM-Cells)

– Simple logical functions like in an adder (3 input XOR)have no need for optimization (lookup-tables)

– Pipelining important to reduce or prevent long wires

– Number of wires/connections important







Impact on FPGA (Problems)

– Sometimes wiring may not be possible although enough logic-blocks are available

– Some configurations can result in really long wires

– Errors in circuit description can be easily corrected







Impact on ASIC– All functions are realised with standard-cells or directly in transistors

– Possible to optimize even very simple functions

– Logic-depth and fanout more important than wire-length

Problems:– Sometimes wiring is not possible because of number of layers

Both:Many optimizations are also done by the tools





3. Examples


1. Adder with (apparently) superfluous registerFPGA with superfluous register: ~560 MHz

FPGA without superfluous register: ~380 MHz

ASIC with superfluous register: ~2.4 GHz

ASIC without superfluous register: ~2.39 GHz





3. Examples


2. 3-Input XOR in AdderFPGA: no difference size both are realised with one LUT

ASIC: Second design slightly slower

3. Pipelined Wallace-Tree vs. 4:2 Compressor TreeFPGA: The compressor tree is faster and needs less logic-blocks

ASIC: Wallace-Tree is faster but slightly bigger





4. Architectural impact on Performance


Impact on FrequencyFPGA

• Length of wires has highest impact→ Pipelining (e.g. also for register with high fanout)

• Complex functions (with multiple Logic-Cells)• Sometimes FPGA itself restricts using higher frequencies

ASIC• Logic-depth mostly influences timing• With higher frequencies wiring becomes more important• Fanout also influences timing







Impact on SizeFPGA

• The size of the design does not change the size of an FPGA only the usage

ASIC• Size directly influenced by number and complexity of logicalfunctions.• Minimal size also influenced by the pads







Impact on Power ConsumptionFPGA

• Wiring complexity and number of logic elements influencethe consumed power

• Static power consumption of the FPGA

ASIC• Power consumption of circuit proportional to the size of the circuit

• Circuit itself needs much less power than the pads





5. Conclusions


FPGA and ASIC need slightly differenct approach for the architecture– The optimization of the simple logic functions have little to no

effect on an FPGA

– Pipelining has a huge influence on both

– Timing of ASIC is more dependent on complexity of the circuit, on FPGA more dependent on wiring

– On both other aspects are also restrictive• Pads in an ASIC• Clock Buffer or overall size in FPGA



Thanks for your attention!

(Questions?)

26.04.23 © 2013 UNIVERSITÄT ROSTOCK | Fakultät für Informatik und Elektrotechnik 15

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