implementing matlab and simulink algorithms on · pdf fileimplementing matlab and simulink...

9/21/2011

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Implementing MATLAB and Simulink Algorithmsg

on FPGAs

Stefano Olivieri Marco Visintini

1© 2011 The MathWorks, Inc.

Stefano Olivieri

Senior Application Engineer

MathWorks

Marco Visintini

Sales Account Manager

MathWorks

Daniele Bagni

DSP Specialist EMEA

Xilinx

Agenda

9:45 Welcome

10:00 Reduce FPGA Development Time with Model-Based Designp g

11:00 Break

11:15 Integrated HDL Verification

12:00 Xilinx Target-optimized FPGA Design Using MATLAB and Simulink

13:15 Lunch

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13:15 Lunch

14:15 FPGA Design Optimization Techniques

15:45 Q&A, Summary and Wrap-up

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Introducing The Speakers

Xilinx:

Daniele Bagni Daniele BagniDSP Specialist EMEA

MathWorks:

Stefano OlvieriSenior Application Engineer

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Signal Processing and Communication

Marco VisintiniSales Account Manager

MathWorks and Xilinx Goals

MathWorks: accelerate the pace of engineering and science by providing best in class Software for:

De elopment and erification of algorithms and control logic– Development and verification of algorithms and control logic

– Embedded Systems implementation

Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms :– Offers FPGAs and Zynq – an Extensible Processing Platform

P t ith M thW k t id i t t d kfl

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– Partner with MathWorks to provide an integrated workflow

Purpose of the joint seminar: – to demonstrate a Model-Based Design workflow for FPGAs -

from first idea down to the Hardware.

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MathWorks at a Glance

Headquarters:N ti k M h tt USNatick, Massachusetts US

Other US Locations: California, Michigan, Texas, Washington DC

Europe:France, Germany, Italy, Spain, the Netherlands, Sweden, Switzerland, UK

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Asia-Pacific:Australia, China, India,Japan, Korea

Worldwide trainingand consulting

Distributors in 25 countries

Earth’s topography on an equidistant cylindrical projection,

created with MATLAB and Mapping Toolbox.

MathWorks Today

Revenues ~$600M in 2010

Privately held Privately held

More than 2000 employees worldwide

Worldwide revenue balance:45% North America, 55% international

More than 1 million users in 175+ countries

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1984 1989 1994 1999 2004 2009

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Key Industries

Aerospace and Defense

Automotive

Biotech and Pharmaceutical

Communications

Education

Electronics and Semiconductors

Energy Production

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Financial Services

Industrial Automation andMachinery

Who is Who???

Who is a System Engineer?

Wh i FPGA d i ? Who is an FPGA designers ?

Who is using MATLAB?

Who is using Simulink?

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Your Expectations Beyond the Agenda...

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Corner Detection in Video Mosaicking(A Brief Example)

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Use Model-Based Design to provide an integrated workflow

Things to remember ….

DESIGN

Speed up algorithm development with a unified design environment

Automate manual steps in FPGA implementation to enableshorter iteration cycles

AlgorithmDevelopment

MATLABSimulinkStateflow

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Integrate FPGA development tools to reduce verification time

Agenda

9:45 Welcome


11:00 Break



13:15 Lunch

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13:15 Lunch



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Memory

Customized interfaces to peripherals

Memory

We are going to focus on

Why do we use FPGAs?

Analog I/O

Digital I/O

ARM

Bridge

MemoryMemory

Memory High-speed communication

interfaces to other processors

Finite state machines, digital logic, timing and memory control

FPGAAnalog I/O

Digital I/O

ARM

Bridge

MemoryMemory

Memoryto focus on this use case today

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DSP

High speed, highly parallel DSP Algorithms or Control Algorithms

DSPAlgorithms

FPGA DesignerSystem Designer

Algorithm Design System Test Bench RTL Design Verification

Separate Views of DSP Implementation

Algorithm Design

Fixed-Point

Timing / Control Logic

Architecture Exploration

Algorithms / IP

System Test Bench

Environment Models

Algorithms / IP

Analog Models

Digital Models

RTL Design

IP Interfaces

HW Architecture

Verification

Functional Simulation

Static Timing Analysis

Timing Simulation

Behavioral Simulation

Back AnnotationImplement Design

Map

SynthesisFPGA Requirements

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Map

Place & Route FPGA HardwareHardware Specification

Test Stimulus

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Where do you spend most of your time?

Simulating designs?

Creating designs and test benches?

Algorithm Design System Test Bench

System Designer

Analyzing and combining results from multiple tools?

Exploring implementation ideas and architectures?

Floating point to fixed-point?

Writing HW specifications?

Algorithm Design

Fixed-Point



Algorithms / IP

System Test Bench

Environment Models

Algorithms / IP

Analog Models

Digital Models

FPGA Requirements

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Iterating over designs with the FPGA designer?

Blaming the FPGA designer?

Hardware Specification

Test Stimulus

FPGA Designer

Where do you spend most of your time?

Simulating designs and validating against HW specs?

Creating designs and writing test RTL Design Verification

benches?

Hardware architecture design?

Writing interfaces to existing IP?

Synthesis, Map, PAR cycles?

Iterating over designs with the system designer?

RTL Design

IP Interfaces

Hardware Architecture

Verification



Timing Simulation



Map

Synthesis

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system designer?

Blaming the system designer?

ap

Place & Route FPGA Hardware

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1. Increase simulation speed

2. Simplify design entry, system test harness

A Few Ways to Reduce Development Time

creation, and exploration

3. Shorter iteration cycles required for RTL design & verification

4. Integrate the separate workflows to facilitate collaboration, re-use, and prototyping

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Model-Based Design for Implementation

Algorithm Design System Test Bench RTL Design Verification

MATLABMATLAB® ® andand SimulinkSimulink®®

Algorithm and System DesignAlgorithm and System Design

Algorithm Design

Fixed-Point



Algorithms / IP

System Test Bench

Environment Models

Algorithms / IP

Analog Models

Digital Models

RTL Design

IP Interfaces


Verification



Timing Simulation



Map

SynthesisFPGA Requirements

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Map

Place & Route FPGA HardwareHardware Specification

Test Stimulus

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Algorithm and System DesignAlgorithm and System DesignModel Refinement for HardwareModel Refinement for Hardware


RTL Design VerificationRTL Design

IP Interfaces


Verification



Timing Simulation



Map

Synthesis

Automatic HDL Automatic HDL Code GenerationCode Generation

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Map





VerificationVerification



Timing Simulation



Map

Synthesis

HDL CoHDL Co--SimulationSimulationAutomatic HDL Automatic HDL

Code GenerationCode Generation


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Map


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Verification



Verification


Timing Simulation


Map

Synthesis


Back Annotation




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Map

Place & Route FPGA HardwareImplement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation





Back Annotation




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FPGA HardwareImplement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation


FPGA HardwareFPGA HardwareFPGAFPGA--inin--thethe--LoopLoop

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Why Model-Based Design?

Back Annotation





Automate manual steps in FPGA implementation to

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Implement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation



FPGA implementation to enable shorter iteration cycles


Ch ll

AT4 wireless Increases Internal Test Coverage to Over 90% for LTE Physical Layer Test Equipment Designs

ChallengeDevelop test systems for LTE wireless equipment

SolutionUse MATLAB and Simulink to design and simulate the LTE physical layer, verify the FPGA implementation, and analyze test results

Results Internal test coverage increased to over 90% Test harness reused throughout the project

“MATLAB is a universal language that

makes it easy to exchange algorithms

and test results across our team. Our

physical layer model in MATLAB and

Simulink enabled us to better

AT4 wireless LTE layer 1 tester.

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Test harness reused throughout the project life cycle

Development effort reduced by 25–30%

understand the LTE specifications, and

Model-Based Design enabled us to

verify that our FPGA implementation

conformed to those specifications.”

Francisco Javier Campos

AT4 wireless

Link to user story

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Challenge

Semtech Speeds Development of Digital Receiver FPGAs and ASICs

gAccelerate the development of optimized digital receiver chains for wireless RF devices

SolutionUse MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation

Results Prototypes created 50% faster

“Writing VHDL is tedious, and the

handwritten code still needs to be

verified. With Simulink and Simulink

HDL Coder, once we have simulated

the model we can generate VHDL

The Semtech SX1231 wireless transceiver.

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Verification time reduced from weeks to days Optimized, better-performing design delivered

the model we can generate VHDL

directly and prototype an FPGA. It

saves a lot of time, and the generated

code contains some optimizations we

hadn’t thought of.”

Frantz Prianon

SemtechLink to user story

Case Study: Corner Detection Algorithm

31© 2011 The MathWorks, Inc.

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Corner detection is used in many Image Processing applications

Harris-Stephens’ Corner Detection

– Image mosaicking

– Tracking

– Object recognition

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Horizontal Gradient


Corner Metric Mc

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Vertical Gradient

Sobel Edge Filter

Threshold & Find Local Maxima

Calculate Corner Metrics

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From Algorithm to Synthesizable RTL



Implement Design Verification

Back Annotation




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Implement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation



Flexible Design EnvironmentDesign, Simulation and Implementation

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Choice of best modeling methods (Simulink, MATLAB and Stateflow)

Integrate with MATLAB Algorithm Design

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Fixed Point AnalysisCorner Detection

Convert floating point to optimized fixed point models– Automatic tracking of signal range (also intermediate quantities)Automatic tracking of signal range (also intermediate quantities)

– Word / Fraction lengths recommendation

Bit-true models in the same environment

Automatically identify and solve fixed point issues

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Automatic HDL Code GenerationCorner Detection

Full bi-directional traceability!!

Automatically generate bit true, cycle accurate HDL code from

Simulink, MATLAB and Stateflow

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Requirements

traceability!!

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Simulink Library Support for HDLHDL Supported Blocks

170 blocks supported

Core Simulink Blocks– Basic and Array Arithmetic, Look-Up Tables,

Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs

Signal Processing Blocks– NCOs, FFTs, Digital Filters (FIR, IIR, Multi-

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, , g ( , ,rate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max)

Communications Blocks– Psuedo-random Sequence Generators,

Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders

MATLAB– Relevant subset of the MATLAB

MATLAB & Stateflow for HDLHDL Supported Blocks

– Relevant subset of the MATLAB language for modeling and generating HDL implementations

– eml_hdl_design_patterns: Useful MATLAB Function Block Design Patterns for HDL

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Stateflow– Graphical tool for modeling Mealy

and Moore Finite State Machines

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Integrating Legacy HDL CodeHDL Supported Blocks Integrate legacy HDL code

in Simulink using black boxes

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Configure the interface to legacy HDL code

EDA Simulator Link is a special black box

Summary: Modeling and Code Generation

Model-Based Design provides an integrated workflow– Optimized design on a System LevelOptimized design on a System Level

Speed up algorithm development with a unified design environment– Collaborate with other engineers

– Use Simulink blocks, Stateflow or MATLAB for modeling and implementation

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implementation

Shorter iteration cycles– Assisted Fixed-Point Conversion

– Automatic HDL Code Generation

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Break

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DESIGN





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Wh t ld lik t tWhat would you like to get

from automatic code

generation?

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generation?

DESIGN

Hardware Design Challenges:Optimizing for Speed, Area or Power

Optimize HDL code

Verify optimized HDL

Place & Route



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Analyze result

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IIR Low Pass FilterDirect-Form II Transposed SOS

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From Algorithm to Optimized RTL




Back Annotation




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Implement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation



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Hardware Design Challenges:Speed Optimization

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Finding the critical path in your model can be challenging

Demo: HDL Workflow Advisor>> Choose target workflow:• FPGA-in-the-Loop• FPGA Turnkey• Design exploration:

Generic ASIC/FPGA

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Choose FPGA target

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Demo: HDL Workflow AdvisorPerform relevant checks for HDL code generation

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Demo: HDL Workflow Advisor

Set options and generate automatically HDL code

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Demo: HDL Workflow AdvisorCreate FPGA project

Run P&R -and-

Annotate timing information

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Automated workflow from model to FPGA Analysis &

Implementation

Identifying the critical pathSpeed Optimization

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Critical Path highlighting: Visual representation of critical path in your model Easier to identify bottlenecks of your model

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Balancing pipeline registersSpeed Optimization

critical path

parallel paths

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Multiple parallel paths through your model High risk to have unmatched latencies

Demo: Configuring Pipelining OptionsSpeed Optimization

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Distributed PipeliningSpeed Optimization

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Distributed pipelining (model retiming) Automatic balancing of pipeline registers

(focus on critical path only) You are in full control of your pipelining strategy

Bottom-up and top-down


Minimum period: 23.796ns Maximum Frequency: 42 024MHz

Section 1

Maximum Frequency: 42.024MHz

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Section 2

Section 3

Device,package,speed: xc5vsx50t,ff1136,-1

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Minimum period: 9.379ns Maximum Frequency: 106 62MHzMaximum Frequency: 106.62MHz

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Section 2

Section 3

Device,package,speed: xc5vsx50t,ff1136,-1

Hardware Design Challenges:Area Optimization

XXXX

XXXX

XXXXXX

MUX DEMUX

SCHEDULING

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XX

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IIR Low Pass FilterDirect-Form II Transposed SOS

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Challenges:

Data dependent resources to be shared

Feedback loops

Vectorized inputs

Demo: Configuring Sharing OptionsArea Optimization

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Resource Sharing and StreamingArea Optimization

Easy to explore different sharing options

Direct feedback through resource utilization report Direct feedback through resource utilization report

Prove correctness through validation models

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Power Dissipation = Static Power + Dynamic Power

Hardware Design Challenges:Power Optimization

– Static Power = Due to transistor leakage current Significant in smaller silicon geometries

– Dynamic Power = CV2f Function of load capacitance, operating frequency, and voltage swing

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Steps To Reduce Power– Smaller/Efficient Designs

Better Algorithm DesignPower Optimization

Smaller/Efficient Designs

– Reduce Clock Frequency

– Control Subsystem Execution (enabled/triggered subsystems)

– Low Power Design Libraries/FPGA Devices

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Multi-rate Models to Reduce Clock FrequencyPower Optimization

Cycle accurate simulation and implementation

Multiple or single clock implementationp g p

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clk

clk_enable

enb_1_2_1

enb_1_2_0

clk_enable

Timing Controller

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Control Subsystem ExecutionPower Optimization

Enabled Subsystems Modules can be enabled and disabled

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Triggered Subsystems Modules can be triggered: rising / falling / either edge

Control Subsystem ExecutionPower Optimization

gg g g g

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How do these techniques work with our Corner Detection algorithm??


Detection algorithm??

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Summary: Corner Detection Demo

Multipliers 154

Adders/Subtractors 90

Registers 852

Multipliers 6

Adders/Subtractors 46

Registers 679

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Easy approach to explore different implementations

No costly mistakes

Registers 852

RAMs 0

Multiplexers 2

Registers 679

RAMs 4

Multiplexers 302

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Summary: Code Generation Optimizations

Shorter iteration cycles– Automatic HDL code generationAutomatic HDL code generation

Flexible automatic HDL Code generation– Speed Optimization

– Area Optimization

– Make the right design choices to save power

– Analyze implementation results, resource utilization report

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Analyze implementation results, resource utilization report

– Validation models to prove that implementation is correct

Agenda

9:45 Welcome


11:00 Break



13:15 Lunch

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13:15 Lunch



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DESIGN





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HDL Verification

How do you do HDL verification today?y y

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Verification Challenges:HDL Verification

Design the Test Bench twice Design the Test Bench twice– 10 – to – 1 ratio of Test bench LOC – to – Design LOC

Many stimuli-files from MATLAB

These are ideal references which require pre- and post-processing

How to analyze results?

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Verification Challenges:HDL Verification

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Demo: Re-Use System Level Test Bench

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Digital Down Converter

DDC acceptsp– A high sample-rate passband signal (may be 50 to 100 Msps)

DDC produces– A low sample-rate baseband signal ready for demodulation

~70 MSPS ~270 KSPS

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DigitalDown

Converter

A/DConv

RFSection Demod

Integrated HDL Verification




Back Annotation




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Implement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation



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What is the impact of

Verify Handwritten HDL Vector-Based Digital Down Converter

What is the impact of these differences?

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Difficult to analyze simulation results

Re-use system level test bench

Flexible testbenchcreation in Simulink

Co-Simulation with HDL simulatorsDigital Down Converter

bench creation in Simulink

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Direct simulation link to HDL Simulators

Difference is small and in the stopband of the filter

Automatically generated HDL co-simulation

models

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Additional Methods for VerificationHDL Verification Techniques

Co-simulation with MATLAB– Test Bench

– Component

Generate vector based test benches for standalone verification

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FPGA-in-the-Loop

Integrate MATLAB Algorithm DevelopmentCo-Simulation with MATLAB

Test Bench Verify HDL against high-level

MATLAB

Verify HDL against high level MATLAB design

ComponentR l “B k ” fi i h d

HDL Simulator

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Replace a “Broken” or un-finished block in a full HDL test bench with a working high level component

Test alternate algorithms for system trade-off without developing HDL

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Ch ll

Harris Accelerates Verification of Signal Processing FPGAs

ChallengeStreamline a time-consuming manual process for testing signal processing FPGA implementation

SolutionUse EDA Simulator Link to verify the HDL design from within MATLAB

Results Functional verification time cut by more than 85% 100% of planned test cases completed

“EDA Simulator Link enabled us to

greatly reduce functional verification

development time by providing a direct

cosimulation interface between our

MATLAB model and our logic simulator.

Harris FPGA-based system.

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100% of planned test cases completed Design implemented defect-free

MATLAB model and our logic simulator.

As a result, we verified our design

earlier, identified problems faster,

completed more tests, and compressed

our entire development cycle.”

Jason Plew

Harris Corporation

Link to user story

Compile and simulation scripts are provided

Collaborate with Other Design TeamsTest Benches for Standalone Verification

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Automatically generate self-checking test

benches

Can be used in any HDL Simulator

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Challenges:Testing algorithms on real hardware

Motivation: building confidence

But …… interfaces with peripherals

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p p& rest of the system needed

Difficult to construct testbenches in real hardware

Demo: Re-Use System Level test bench

FPGA-in-the-Loop verification Digital Down Converter

Integration with FPGA development boards

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Automatic creation of FPGA-in-the-Loop verification models

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FPGA-in-the-Loop verification Digital Down Converter

Flexible testbenchcreation in Simulink

Re-use system level test bench for FPGA

verification

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Building confidence that the design works on real

hardware

Summary: Verification

Integration of FPGA development tools enhances verificationverification

– Improved analysis, flexible testbench creation (multi domain, feedback loops)

– Integration with HDL verification

– Integration with FPGA verification

A tomation gi es shorter iteration c cles

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Automation gives shorter iteration cycles– Automatically generated verification models for:

HDL Co-Simulation

FPGA-in-the-Loop

– Wizards for legacy HDL code

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From Algorithm to FPGA Implementation




Back Annotation

EDA Simulator LinkEDA Simulator LinkModelSimModelSim

HDL CoHDL Co--SimulationSimulation

SimulinkSimulink HDL CoderHDL CoderRTL CreationRTL Creation


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Implement Design

Map

Place & Route

Synthesis

Verification


Timing Simulation


EDA Simulator LinkEDA Simulator LinkFPGAFPGA--inin--thethe--LoopLoop

Agenda

9:45 Welcome


11:00 Break



13:15 Lunch

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13:15 Lunch



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Agenda

9:45 Welcome


11:00 Break



13:15 Lunch

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13:15 Lunch



Agenda

9:45 Welcome


11:00 Break



13:15 Lunch

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13:15 Lunch



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DESIGN





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y


Shorter implementation time by 48% (total project 33%)

Reduced FPGA prototype development schedule by 47%

ROI: Customer Adoption Of Model-Based DesignTime spent on FPGA/ASIC implementation

Shorter design iteration cycle by 80%

1st FPGA Prototype 2nd FPGA Prototype

1st FPGA Prototype

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How to adopt MathWorks technologies?

MathWorks tools provide a technology to speed up p gy p pdevelopment

MathWorks services provide the support to roll out this technology in your organization

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Example MathWorks Services

MathWorks Training– Private training “Simulink HDL Coder”

– Public training “Signal Processing with MATLAB/Simulink”Public training Signal Processing with MATLAB/SimulinkFundamental trainings for uniform knowledge, quick ramp up

MathWorks Consulting – Jumpstart service to get you up and running quickly with

Simulink HDL Coder

– Advisory service for ongoing expert advice during technology adoption

– Based on industry experience, assistance with tailoring workflow

On site expert customization / optimization of your workflow

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– On site expert customization / optimization of your workflow

Technical Support– Comprehensive, product-specific Web support resources

– 70% cases solved within 24 hours

– Included in Software Maintenance Service

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Were Your Expectations Met?

Please complete and return seminar survey forms

Your comments and feedback are very important to us

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1. Visit www.mathworks.com/fpga

Next Steps …

pgfor more information

2. Visit www.xilinx.com/dspfor more information

3. Watch our FPGA webinars:

th k / / t / bi

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– www.mathworks.com/company/events/webinars

4. Contact your local sales reps for a trial of our FPGA tools

Questions?

implementing matlab and simulink algorithms on · pdf fileimplementing matlab and simulink...

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