implementing hardware and software for an arm cortex …rtcgroup.com/arm/2007/presentations/203 -...

Implementing Hardware and Software for an ARM Cortex-M1 in FPGA

Mike Thompson Senior Manager, IP and Application Solutions

October 2007

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AgendaOverview Processor ToolsCoreConsoleLiberoSoftConsolePorting code from ARM7 to Cortex-M1DEMO – Build a Cortex-M1 System

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Cortex-M1 - Next Member of the M SeriesDesigned for FPGA Implementation

Soft Processor (Implemented in FPGA Fabric)

Small, Powerful, Highly-optimized for FPGAsConfigurableARMv6-M Architecture

Subset of Thumb-2All 16-bit Thumb Instructions and some 32-bit Instructions

Delivered as Black Box via CoreConsoleHighly secureUsers can connect IP to processorFully implemented in fabricUser can program into device

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Actel Cortex-M1 Design Flow

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CoreCoreConsoleConsole

• Select Processor

• Choose Peripherals

• Add Optional User Custom IP

• Auto Stitch to Build System

•• Select ProcessorSelect Processor

•• Choose PeripheralsChoose Peripherals

•• Add Optional User Custom IPAdd Optional User Custom IP

•• Auto Stitch to Build SystemAuto Stitch to Build System

• Combine System with Non-Processor Code

• Synthesis, Simulation, andLayout

• Optional Timing/PowerAnalysis

• Easy to use GUI

•• Combine System with Combine System with NNonon--Processor CodeProcessor Code

•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout

•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis

•• Easy to use GUIEasy to use GUI

Libero IDELibero IDE

HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW

SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE

•• GNU CGNU C--CompilerCompiler

•• GNU DebuggerGNU Debugger

•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import

Industry Standard SupportIndustry Standard Support

•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU

•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus

•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research

•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR

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SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW

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• Easy to use GUI
















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CoreConsole - HW Development Tools

SOC Builder and IP Deployment Fast assembly and configuration of user designsEasy-to-use graphical user interfaceWide range of AMBA peripheral IP

CoreConsole v1.3Can be downloaded from www.actel.com

System output as configured RTLAllows easy system setup and configurationCortex-M1 output as a blackbox

Full support for Cortex-M1 Seamless integration with Libero IDE

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System-on-Chip - Cortex-M1Processor System

ProcessorBus FabricComponents

ComponentsCortex-M1AMBA IP Cores

CoreConsole Automatically Creates Basic System

… OR … User Can Create System Manually

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IP Cores Available in CoreConsoleProcessors

Cortex-M1, CoreMP7 Core8051s, CoreABC

AMBA Interfaces CoreAHB, CoreAHBLiteCoreAPB, CoreAPB3 CoreAHB2APB

Other Interfaces Core10/100, Core429, CorePCIFCore1553BRT, Core1553BRM

Subsystem Cores CoreAHBNvmCoreAHBSramCoreAICoreCFICoreDDRCoreFMEECoreFROMCoreGPIOCoreI2CCoreInterruptCoreMemCtrlCorePWMCoreRemapCoreSDRCoreSMBusCoreTimerCoreUART, CoreUARTapbCoreWatchdog

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Building an SoC with CoreConsole

Decide on components needed to meet system requirements.

Add busses and bridge as necessary

Add components

Connect to busses

Configure components and memory map placement.

Generate system

Test and Verify the system

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Cortex-M1 - CoreConsole Configuration

Select Debug InterfaceNone (Default)RealView JTAGFlashPro3

Select DieM1AFS600 (Default)M1A3P1000Future Project-Wide Setting

Other Options Inactive

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Stitching an SOC Together

CoreConsole enables components to be stitched to the AHB and APB bussesComponents ‘advertise’ the interfaces they have availableAuto-Stitching supportedto accelerate this taskUser can add and remove individual connectionsAd-Hoc connections are selected from drop down configuration boxes

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Adhoc Signal Connections To connect

Right Click on component and click configure Or click

Label the connectionSelect ‘From’ component and pinSelect ‘To’ component and pinClick connectObserve the connection label added to schematic

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Rapid SOC GenerationItems to be Generated are Selected in This Tab

Output Folder Tree is C:\CoreConsole\LiberoExport\<MyDesign>

Details of the Files Output are Communicated to Libero in an XML File

Libero uses this to import a design

All the Files Generated by CoreConsole Can Be Located on the Disk And Manually Edited

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• Easy to use GUI
















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Libero IDELibero Project Manager

Manages design flow and files

Design Creation/VerificationHDL, SmartGen Cores, SchematicOptimizationTest BenchVerification

Design ImplementationFloor planning & physical constraints Place & RouteTiming constraints & analysisPower analysisProgram file generation

Programming and Debug FlashPro3 supports Programming for all Fusion devices

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Libero IDE

Design Hierarchy

View

Catalog:- Configurable Cores- HDL Templates- Macros- Bus Interfaces

Interactive Design Flow

Management Tools

Log File

Design Entry Tools

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Libero IDE - Project Manager

File Manager

View

Catalog:- HDL Templates

- Simple click to insert into HDL code

- Proven/tested

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Libero IDE Design EntryDesigner Block Flow

Create Fully Optimized Functional Blocks Through LayoutPreserves placement and timingPublish to design repositorySupports Design & Re-use goalsPublished Block Fully Compatible with Libero Design Flow

SmartDesignTraditional

Design Entry OptionsCoreConsole Processor Subsystems CoreConsole Configured Direct CoresUser Created HDL ModulesLibero Created “Designer Blocks”ViewDraw SchematicMixed HDL DesignsMixed Schematic/HDL DesignsSmartGen Configured CoresPartner Created Companion CoresSmartDesign Components/Modules

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Synthesize with Synplicity’s Synplify AESynplify AE

Leading edge synthesis from the market leaderClose OEM partnership provides optimal benefit to Actel users Integration with Libero IDE ensures seamless operation Optimized performance and area utilization for all Actel FPGAsAvailable in Free Libero Gold

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Mentor Graphics ModelSim HDL SimulatorHDL simulation in VHDL or Verilog

Pre-synthesis simulationPost-synthesis simulationPost-layout simulation

Simulate

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Libero IDE - Designer User Interface

Physical Implementation

Tools

Constraint & Analysis Tools

Log & Device Information

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Libero IDE- “Designer” Physical Implementation

Designer FunctionsImport Netlist, Compile, and Design Rule CheckFloor planning and physical constraintsTiming driven Place and RouteBack annotated timing for full timing simulationSmartTime setup of Timing Constraints and Timing AnalysisSmartPower analysis of power consumption Generate bitstream or STAPL programming filesComprehensive log file and reports

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Libero IDE - SmartTime Timing Constraints

Visual Dialogs simplify constraint entryView scope of timing pathsSelect portsSet Clock EdgeEnter Timing Requirements

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Libero IDE - Program File GenerationProgram File Generation for ProASIC3/E

ProgramSecurity Settings

Security LevelPass KeyAES Key

FPGA ArrayFlashROM

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Device Programming and DebugProgramming Software

FlashProIn System Programming (ISP) for Actel Flash devices

Supports all FlashPro hardware programmersIncludes ChainBuilder

Generates a merged STAPL file for programming Actel FLASH devices in a mixed IC environment

Silicon SculptorSupports all Actel devices

Use with Silicon Sculptor hardware programmers Launch from Libero Project Manager or stand alone

Device DebuggingSynplicity Identify Debugger

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SoftConsole - Processor SW DevelopmentSoftware development environment

Eclipse-based IDE - easy user interfaceSupports Cortex-M1, CoreMP7, Core8051/sCan be downloaded from www.actel.com

C/C++ programming and debugCodeSourcery G++ ARM toolsSDCC 8051 compilerProgramming and debug with Actel’s FlashPro3

Can import existing codeOpen platform for application development

Support for RTOS and stacksuC/OC, uClinuxTCP/IP, USB, IPMI

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SoftConsole GNU C/C++ CompilerExtensive intelligent ARM optimization

Built from CodeSourcery G++ GNU/GDB

Includes many features useful for embedded systemsPowerful inline assembly syntaxComprehensive linker script language permitting exact placement of code and data

Large developer base results in tool stability

ISO C and C++ language supportComplete runtime librariesAggressive code usage analysis and syntax warningsSupports ARM EABI for better portability

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SoftConsole GDB DebuggerSupport for source- and assembly-level debugging

Live debugging of new codeIn an FPGA or in the GDB ARM simulator

Breakpoints can occur when certain conditions are met

Intelligent access to hardwareRegister banks and memory rangesHover over a variable to read its current value Changes in value are obvious for any variable, memory or registerCurrent stack frame displayed while debugging

Evaluation of expressions at runtime

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On-Chip Debugging via FlashPro3Download and debug executable programs to development boards using FlashPro3

Can program and debug processor memory and FPGA fabric with FlashPro3Reduces pin-count – Utilizes dedicated FPGA JTAG pins via UJTAG versus GPIO RVI-ME configuration (10-pins)

Full debugging of code on remote targetView internal registers, memory locations, variables, etc.

Uses the same interface as Instruction Set Simulator

Only one tool to learn

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Porting software from ARM7 to Cortex-M1Cortex M Processors More User-friendly than ARM7

Less Need for Assembler Code

Main Differences from Software Porting Perspective:

PSR (Banked Registers)xPSR (Stacked Registers)System Status

IRQ and FIQ InputsExternal Interrupt Controller

Integrated NVIC, up to 32 Interrupts

Interrupts

UnstructuredStructured (Architecture-defined)

Memory Map

ARM or ThumbThumb-2 OnlyExecution State

CoreMP7Cortex-M1Feature

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ARM7TDMI overview32/16-bit RISC Architecture (ARM v4T - Thumb)

32-bit ARM Instruction Set

16-bit Thumb Instruction Set

32-bit ALU

3-stage Pipeline

Unified 32-bit Bus Interface

Fully-static Operation

Extensive Debug FacilitiesEmbedded Real-time Debugging BlockJTAG InterfaceSupport for Trace

TDMI Stands for:Thumb Debug Support Multiplier (64-bit Result) In-Circuit Emulator Interface

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Cortex-M1 vs. ARM7

Simple Interrupt Support (Two Interrupts –IRQ and FIQ)No Auto State Saving or RestoreLong, Non-deterministic, Interrupt Latency FIQ Has Priority over IRQ – Fixed

Sophisticated Interrupt Support1 – 32 Interrupts Automatic Processor State Saving and RestorationDeterministic, Short Interrupt Latency4 Levels of Interrupt Priority – Set by User

Bigger, Slower in FPGAs6083 Tiles, 28 MHz without Debug

Smaller 2/3 Size, 2.5 x Faster4435 Tiles, 69.9 MHz without Debug

Industry-standard ProcessorWell-established and Recognized in ASIC Market (around for >15 Years) Initially Custom Design (Only Later Made Available as Synthesizable RTL

New ProcessorDesigned Specifically for FPGAImplementation

ARM7 (CoreMP7)Cortex-M1

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Cortex-M1 vs. ARM7 (cont.)

Unstructured Memory Map(Exception Vectors from Address 0 Onwards, No Further Restrictions)

Defined Memory Map

External Interface Is Native ARM7 – Not AMBA Requires Bridge to AMBA

Connects Directly to AMBAExternal Interface is AMBA AHB-Lite

Memory Accesses over AMBAEach Instruction Access Is at Least Two Clock Cyclesvon Neumann Architecture – Shared Instruction and Data Interface

Separate Memory Interface from AMBA1 Clock Cycle per Instruction AccessHarvard Architecture – Separate Instruction and Data InterfacesTightly-coupled Memories (TCM) up to 1MB

Normally Executes ARM Instructions Can also Execute 16-bit Thumb Instructions but Must Change State to Do This

Only Supports Thumb Instructions (All 16-bit Thumb Instructions and Some Thumb-2 32-bit Instructions)Does Not Execute ARM Instructions

ARM7 (CoreMP7)Cortex-M1

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Cortex-M1 - Instruction SetARMv6-M ISA (Subset of Thumb-2)

All 16-bit Thumb Instructions and Some 32-bit Thumb-2 Instructions

Ideal C Compiler TargetReduces Time to Market and Improves Code QualityInterrupt Service Routines Can Be Coded Directly as C Functions

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Cortex-M1 - Registers17 Registers

13 General-Purpose Registers

Stack PointerLink RegisterProgram Counter

Cortex-M1 register file is same as ARM7 register file

Low Registers –Accessible by All Instructions

High Registers –Accessible by SOME 16-bit Instructions

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Porting software from ARM7 to Cortex-M1Components of Embedded Software System

Application Code (Typically C/C++)Should Remain Largely Unchanged

May Need Minor ModificationsRe-compile Source Code with Cortex-M1 as Target

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Porting software from ARM7 to Cortex-M1System Code (C and Assembler Code)

Porting System Code – the Crux of the MatterC Code – Modify to Suit Different Resource Locations (e.g., Interrupt Controller) and Re-compile, Targeting Cortex-M1

e.g., Enabling/Disabling InterruptsMust Be Manually Ported

Access to System Features

Automatic State Saving and Restoration Makes Exception Handling Easier for Cortex-M1Exception Handlers May Be Written in C

Exception (Interrupt) Handlers

Simpler for Cortex-M1 – Vector Table Composed of Addresses rather than ARM InstructionsMay Be Possible to Completely Avoid Assembler Code for This

Start-up Code and Vector Table

Tips for Porting to Cortex-M1CoreMP7 (ARM7) Assembler Code

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Actel M1 Development Boards M1-SYSMGMT-DEV-KIT

M1AFS600 deviceSystem Mgmt GUI Demonstration designsFull PCI interfaceAlso available with FP3

M1 SOC BoardsPowered by USB or wall supply1M SRAM, 4M Flash memoryFP3 programmer built into boardExpansion connectors

M1A3P-DEV-KIT-SCSM1A3P1000 device

M1AFS-DEV-KIT-SCSM1AFS600 device

M1AGL-DEV-KIT-SCS M1AGL600 device

M1A3P1000

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Where to Go for More Information Cortex-M1 on the Web

http://www.arm.com/products/CPUs/ARM_Cortex-M1.htmlhttp://www.actel.com/products/mpu/CortexM1/

Key DocumentsCortex-M1 Handbook (Actel)ARM v6-M Architecture Reference Manual (ARM)Cortex-M1 Technical Reference Manual (ARM)

Registration on ARM’s Website Required for Some Documents

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Summary

Cortex-M1 allows designers to benefit from hassle-free, industry-standard ARM architecture

Optimized for use in M1 devices (ProASIC3, IGLOO, Fusion)

Actel FPGA tools offer seamless development flowCoreConsole, Libero, dev kit hardware development toolsSoftConsole with GNU software development toolsThird-party ecosystem support

Brings flexibility and fast time to market to system-level designs