2009 International Conference on Engineering Education (lCEED 2009), December 7-8, 2009, Kuala Lumpur, Malaysia

Design Based Tutorials for System-on-Chip Teachings

Mouna Nakkar Electrical and Computer Engineering Dept.

University of Sharjah Sharjah, UAE

Abstract-Universities are recently updating their digital design education offerings to include the recent System-on-Chip (SoC) design approaches. This paper presents two design based tutorials aimed at providing a smooth transition in the current traditional education for universities. The design tutorials are implemented on the Altera DE2 board. The first tutorial provides an implementation of a basic microprocessor model and is designed for junior and senior Electrical and Computer Engineering students. The second tutorial is an implementation of Least Frequently Used algorithm and is designed for sophomore students. The assessment of these tutorials shows an increase in students' knowledge on FPGA, embedded systems, SoC, and software-hardware co-design. Further, some students showed a great interest in using FPGA boards in their senior design project, while others expressed interest in taking a full 2-3 hour laboratory course to increase their knowledge on SoC. The design database and tutorial documents are available for public and can be downloaded from the University's website.

Keywords-FPGA tutorial; SoC; SoPC; Altera DE2 Board; Embedded Systems; Reconfigurable Computing.

I. INTRODUCTION

A. Tutorial Incentive

Due to the revolutionary change in the traditional digital

design approaches, the Faculty of Computer Engineering at

different universities is updating the computer engineering curriculum to reflect this change. One of the proposals is to

introduce modem System on Chip (SoC) design approach at an early stage of the engineering curriculum. For this purpose,

the author created two sets of design based tutorials to be

given to students at different levels to start this shift smoothly. One tutorial is to be given to sophomore students concurrent

with Digital Logic Design course. The other tutorial is to be given to junior/senior students concurrent with Computer

System Architecture course. These tutorials are project based,

i.e. a solved project introduced followed by small design exercises based in the solved design.

B. SoC Revolution

The revolution of SoC is global. The last ten years

witnessed a major shift in the traditional design of VLSI to a

more modem approach which is SoC; i.e. a board with

978-1-4244-4844-9/09/$25.00 ©2009 IEEE 117

reconfigurable hardware (FPGA), memory chips, and 110

features. As an example, the Altera DE2 board [1] and Xilinx Virtex II Pro [2].

A good support to this claim is a watch in the market of reconfigurable hardware and embedded systems. Embedded

processors account for 98% of the $50 billion processors

market [3], [4]. Currently, the market for SoC is a $2 billion industry and is expected to grow more in the next few years.

C. Integrating SoC in Engineering Curriculum

Teaching embedded systems and FPGAs becomes a

necessary offering in the electrical and computer engineering

curriculum. In 2003 Grant Martin [5] (formally of Cadence, San Jose, CA, now chief scientist at Tensilica, Santa Clara, CA) suggested that few universities are updating their design education to reflect this change:

"However, all evidence points to an SoC design revolution

having taken place, and to the continued substitution of embedded software for much custom and ASIC design. Design education must change to reflect this evolution, yet we

do not see a complete evidence for this, especially at the undergraduate level." Since then, universities started to change

their design and provide the necessary training for their engineer students. Here at the University of Sharjah, computer

engineering faculty are trying to follow this trend and update

the computer engineering curriculum to provide highly qualified and trained engineers.

D. Teaching Embedded/SoCIFPGA design

The teaching of SoC and embedded systems is not simple.

This due to the fact that implementing a design requires

implementing a complete system with all the interfaces of the

peripherals. The student must understand a wide range of

peripherals and their interfaces. For example, implementing a system or project that uses memory and VGA display requires

an understanding of the basics of memory subsystems, VGA

image displays, and their interface models. In addition, the student has to learn and deal with a wide range of complicated

software.

2009 International Conference on Engineering Education (ICEED 2009), December 7-8, 2009, Kuala Lumpur, Malaysia

E. Tutorials Hardware and Software Platform

The tutorials presented in this paper are based on the Altera

Development and Educational 2 (DE2) FPGA SoC [1] board.

This is because of its low coast and wide futures. DE2 board shown in Fig. I has Cyclone II FPGA with 512 KB of SRAM,

8MB SDRAM, and 4MB of Flash and full range of I/O

interfaces. The large Cyclone II FPGA has 33,216 Logical Elements and on-chip memory of 105 4K RAM blocks. These

are used for internal storage and configuration. The EDA tool which comes with this chip is Quartus II 6.1 software. It is

provided with the DE2 board kit. The board is designed for

senior/graduate and small research projects.

usa usa IS Ea.oIl "DN:t"'*u..t.v..�_ .... "'" Perl Po'! • .. cu .. .... PwI RS-m ....

.!=� t t t II1I t t

Figure. l. A picture of the A1tera DE2 Board.

The Hardware Description Language used is Verilog. In

previous tutorials [6], the author used VHDL, and found from

students' volunteer that is not easy for beginners. Verilog is much simpler and close to C or C++ than VHDL.

F. Literature Review

The SoC boards are used in undergraduate courses and

projects, and there are tutorials and books provided for these boards [7-9]. For example, Tyson and Hall [10-11] provided

several reference designs and complete projects database

which are very helpful. Loomis [12] also provided rich databases for Altera DE2 board, but not a step-by-step tutorial.

Most of the offered designs are for advanced students who

have some experience with HDL and/or SoC boards. There are also some courses that focus on embedded systems and SoC

[13-17] which gives guidelines to teaching embedded systems.

This paper provides a project for students at

sophomore/junior/senior level who want to specialize in

embedded systems. The tutorials provide a reference for instructors in how to have a smooth shift in SoC education.

The tutorials are guided step-by-step approach which focuses

on design, interface, and test.

II. TUTORIAL SET 1

This tutorial is an implementation of the basic

118

microprocessor described in Computer System Architecture by Morris Mano [18]. This is widely used textbook which

explains the basic elements of microprocessors, and provide an educational computer architecture model for students. Fig.

2 shows a block diagram of the data-path and external

memory for this basic processor.

A. Processor Registers and Main Memory

The processor is a 16-bit based processor with three types of registers: address registers, data registers, and I/O registers.

The sizes of these registers are 16-bits, 12-bits, and 8-bits,

respectively. There is a one 16-bit Instruction Register (IR) which carries the next instruction to be executed. There are three 16-bit data register: Data Register (DR), Temporary Register (TR), and the Accumulator (AC). There is an 8-bit

Input Register (INPR) and an 8-bit Output Register (OUTR).

There are two address registers: an Address Register (AR) which carries the address of the instruction or data and a

Program Counter (PC) which has the address of the next

instruction. The main memory is only 4096 X 16 bits and has only one

read and one write port. There is only one addressing mode for

direct and indirect memory addressing. To access memory, the

microprocessor uses the Address Register to store its address

and Data Register to store the data contents.

B. Instructions and Instruction Format

The instruction word is 16-bits which carries three

different types of operations: Memory Instructions, Registers

Instructions, and Input/Output Instructions as shown in Fig. 3.

The are three bits dedicated for the opcode, and one bit for the addressing mode. With three bits for the opcode, it may seem

that the computer is restricted to eight operations only. However, the Register and I/O operations use the remaining

12 bits as part of the instruction as shown in Fig. 3. In fact,

there are 7 memory instructions, 12 register instructions, and 6 110 instructions which add up to 25 instructions.

In memory instructions, one of the operands is obtained from main memory and the other obtained from AC. The

destination is also in AC, for example AC + AC + M[AR].

Register operations, on the other hand, are Accumulator based which means that the operand and destination are always in

the Accumulator. The input and output operations have

special 8-bit INPR and OUTR registers.

C. Timing and Control

The timing for all operations in the basic microprocessor is controlled by a master clock. The timing step for the controller

is generated from a sequence counter and a 4 X 16 decoder as shown in Fig. 4. The instruction is partitioned into three parts:

IR[15] (Addressing Mode), IR[14-12] (opcode), and bits

IR[II-0] (memory address or register instruction type). All of

2009 International Conference on Engineering Education (ICEED 2009), December 7-8, 2009, Kuala Lumpur, Malaysia

these bits are inputs to the Control Logic Unit (CU). The CU generates all the register and memory control lines shown in

Fig. 2. The ALU control signals are also generated cu.

Read

Clock

� = C) 8 8 C) u

� ....

Figure 2. Basic microprocessor data-path and external memory

15 14 12 11

I���I Opcode I 15 I. 12 11

I 0 1 1 1 I 15 I. 12 11

I 1 1 1 1 I

Address Memory Operation

Register Operation Register Operation

I/O Operation Input/Output Operation

Figure 3. Basic microprocessor instruction format.

D. Instruction Cycle

The basic computer described has three cycles: Fetch, Decode, and Execute. The Fetch operation takes two cycles

where the CPU finds the instruction from main memory and

writes it into the IR. The CPU at this cycle increments the PC to point to the next instruction. The Decode operation takes

only one cycle where the CPU determines the opcode of the instruction. In Execute operation the CPU executes the actual

instructions. It varies in cycles for the memory type

instructions. Some instructions take two cycles while others take three cycles. The Execute operation for register and 110

operations takes only one cycle.

119

The tutorial is sectioned into six different parts: Implementation of Datapath, Implementation of Counters and

Bus Control, Implementation of Other Control Logic, Implementation of Arithmetic Logic Unit (ALU),

Implementation of Control Unit (CU), and Implementation of

Central Processing Unit (CPU).

Instruction Register (JR) 1 Control Inputs

'--__ ..... r--

4 x 16 decoder

TO

TIS

Increment(INC)

4-bit sequence Clear (CLR)

counter (SC) Clock

I Control Outputs

Figure 4. Control Unit of basic computer processor.

III. ASSESSMENT OF TUTORIAL SET 1

The design tutorial was tested on a group of 11

junior/senior students. The students were taking a Computer

System Architecture course with Mano's textbook [18], so

they all were familiar with the CPU architecture. Almost all of

the students didn't have any previous knowledge of Verilog HDL, FPGA, or SoC boards. The students were given a one

hour introductory lecture on Verilog implementation on Altera

DE2 board.

At the time of the assessment, the students had a very good knowledge of the microprocessor architecture they were

implementing and all its operations. Despite the fact, the

implementation was not simple. This due to the fact that implementation of microprocessor is challenging and requires

focusing on small details. Further, the actual implementation

requires more attention to details than theoretical knowledge.

The students took the tutorial alone without the instructors' help. However, there were some discussions and several questions from the students to try to understand what they

were doing, and not just "blindly" follow the instructions and write the code. Further, some students were motivated enough

to fmd different implementations of some control logic

2009 International Conference on Engineering Education (lCEED 2009), December 7-8, 2009, Kuala Lumpur, Malaysia

circuits other than what is provided in the tutorial.

Overall, all students fmished the tutorial within 6-8 hours. The assessment for this tutorial was only in the informal

feedback student and an anonymous survey. The assessment

focused on three parts: increasing the knowledge of FGPA design and embedded systems, presenting the tutorial in

organized and interesting way, and moderate time spent on the

tutorial.

Table I shows the results of students' assessment regarding this tutorial.

TABLE I QUALITATIVE EVALUATION OF THE BASIC MANO PROCESSOR

Questions to be answered Average* 1 How would describe the language in this 4.0

tutorial? 2 How would describe the flow of the tutorial? 5.0 3 How would you describe the organization of this 4.1

tutorial? 4 Would you recommend this tutorial to others? 4.6

... on a scale 01 to 5 (where 1 - Weak and 5 - Excellent)

From the informal feedback, I gathered that they wanted

small exercises and perhaps design problem after each section of the tutorial to help them with the fmal implementation.

Also, some students expressed interest in having a two hour

lab course specifically for learning Embedded Systems and SoC boards such as the Altera DE2 board. Some student

expressed interests in using the board for their senior design

project.

IV. TUTORIAL SET 2

After the successful experience of Mano processor tutorial

and VHDL project based tutorial [6], and as the department is

shifting towards incorporating more embedded systems and SoC education, the author wrote a similar tutorial for

sophomore students. The style of the tutorial is similar to the previous two tutorials where an introduction of basic

implementation is given then scaled-up design which focuses on hardware/software co-design and memory interface. The

students were asked to implement a Least Frequently Used

(LFU) algorithm on hardware. The implementation focuses on: understanding the design problem, building a Finite State

Machine (FSM) or the controller, and accessing memory. The

tutorial is composed of three sections: Introductory tutorial,

sequential circuit tutorial, and memory interfacing and

implementation of LFU algorithm. After each section, the student is given a small design exercise to match their level.

A. Two Introductory Lectures

The students were given two introductory lectures to the

concept of FPGA and embedded systems. They were also

taught the basics of Verilog HDL and were shown a way how

120

to implement basic gates with Verilog and configure the DE2 board. They also were taught the basics implementation of

sequential circuits. After each session, they were given a small exercise on this session.

B. Interfacing with On-board Memory Tutorial

The students in this section of the tutorial implemented a read/write access to the on-board memory. The memory used

in this exercise is the 512KB SRAM. The students learned how to read, write, and display memory contents. The student

also implemented Least Frequently Used (LFU) algorithm on

a small section of SRAM memory.

V. ASSESSMENT OF TUTORIAL SET 2

The design tutorial was tested on a group of 20 volunteer

students. The students took this tutorial as an optional task at the end of Digital Logic Design course. Almost all of the

students didn't have any previous knowledge of Verilog HDL, FPGA, or SoPC chips. The students were very eager to learn

about embedded systems and FPGA. All of the students

completed the three sections of the tutorial.

Overall, all students fmished the tutorial within 6-8 hours.

The assessment for this tutorial was given in two parts: small exercises at the end of each session, and a survey given to the

students at the end of the course. The assessment survey focused on three parts: increasing the knowledge of FGPA

design and embedded systems, presenting the tutorial in

organized and interesting way, and the time spent on the tutorial.

Table II shows the results of students' assessment regarding this tutorial.

1

2

3

4

TABLE II ASSESSMENT OF LFU TUTORIAL Questions to be answered

Did this tutorial increase your knowledge of embedded systems?

Did this tutorial increase your knowledge of FPGA?

Would you like to implement your senior project with embedded systems and/or on Altera

DE2 board? Overall evaluation of this tutorial

Average'" 3.8

3.8

3.3

4.1 * on a scale 0 1 to 5 (where 1 = Weak and 5 = Excellent)

The students had a very good experience with this tutorial.

The verbal feedback of this tutorial is to have it in a two hour lab course specifically for embedded systems.

VI. CREATING A NEW LAB COURSE

The result of the students' discussion who took the tutorial is encouraging. Almost all of them were interested in taking

2009 International Conference on Engineering Education (lCEED 2009), December 7-8, 2009, Kuala Lumpur, Malaysia

an embedded laboratory course which focuses on SoC, FPGA, and SoPC courses. The laboratory course can be a 2-3 hour

elective course where both tutorials can be turned into lab exercises with additional experiments focusing on board

interfaces. The author is currently preparing an elective course

with the support of the department.

VII. CONCLUSION

Two sets of tutorial were presented. The first set is based on a basic model for the basic computer architecture systems

introduced in a popular textbook, "Computer System Architecture by Morris Mano." The students were able to

design and implement a complete computer system. The

tutorial is ideal for junior/senior students who are taking a Computer Architecture Course. The second tutorial is based

on its style on the first tutorial, but designed for sophomore students. The students implemented a Least Frequently Used

Algorithm which is familiar to them. The assessment of this

tutorial shows students significantly improved their knowledge on FGPA, SoC, and embedded systems. Overall,

the students were very interested in Embedded Systems and

Design with HDL tools.

REFERENCES

[1] Altera Corporation, San Jose, CA [Online]. Available: http://www.altera.com.

[2] Xilinx Inc, San Jose, CA [Online]. Available: http://www.xilinx.com. [3] D. 1. Jackson and P. Caspi, "Embedded systems education: future

directions, initiatives, and cooperation," SIOBED Rev., vol. 2, no. 4, pp. 1-4,2005.

[4] J. Truly, The Two Percent Solution, Embedded Systems Programming, Dec. 2002.

[5] G. Martin, "Industry needs and expectations of SOC design education," in Proc. Int. Corif. Microelectronics Systems Education, Anaheim, CA, Jun. 2003, pp. 146-147.

[6] M. Nakkar, "VHDL project tutorial on Altera DE2 board," in the 2009 Annual conference and exposition, Austin, TX, Jun. 2009.

[7] R. B. Foist, C. S. Grecu, A. Ivanov, and R. F.B. Turner, "An FPGA design project: creating a PowerPC subsystem plus user logic," IEEE Trans. Education, vol. 51, no. 3, 2008.

[8] J.O. Hamblen, T.S. Hall, and M. Furman, Rapid Prototyping of Digital Quartus II edition, Springer, August 2005.

[9] P. R. Willson, Design Recipes for FPGAs, Elsevier, UK, 2007. [10] T. S. Hall and J.O. Hamblen, "Using and FPGA processor core and

embedded linux for senior design projects," in Int. Corif. Microelectronic Systems Education, Jun. 2007, pp. 33-34.

[11] T.S. Hall and J.O Hamblem, "Engaging undergraduate student with robotic design projects," in Sec. IEEE Int. Electronic Design, Test and Applications, Jan. 2004, pp. 140-145.

[12] J. Loomis, Digital Labs with Altera DE2 board, www.johnloomis.org. [13] K. G. Ricks, D. J. Jackson, W. A. Stapleton, "An embedded systems

curriculurn based on the IEEE/ACM model curriculum," IEEE Trans. Education, vol. 51, no. 2, pp. 262-270, May 2008.

[14] T. S. Hall and J. O. Hamblen, "System-on-a-programmable-chip development platforms in the classroom," IEEE Trans. Education, vol. 47, no. 4, pp. 502-507, Nov. 2004.

[15] A. Bindal, S. Mann, B. N. Aluned, and L.A. Raimundo, "An undergraduate system-on-chip (SoC) course for Computer Engineering students," IEEE Trans. Education, vol. 48, no. 2, May 2005.

[16] V. Sklyarov and I. Skiarova, "Teaching reconfigurable systems: methods, tools, tutorials, and projects," IEEE Trans. Education, vol. 48, no. 2, May 2005.

121

[17] J.O. Hamblen, "Using low-coast SoC computer and a commercial RTOS in an embedded systems design course," in the IEEE Trans. Education, vol. 51, no. 3, August 2008.

[18] M.M. Mano, Computer System Architecture 3rd edition, Prentice-Hall, 1993, August 2005.