honor seminar ece 494 final report

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  1. 1. Spring 2014 Honor Seminar ECE 494.016 Final Report Modeling, Simulation and Implementation of Memristors Juan J Faria Briceno Center for High Technology Materials The University of New Mexico Advisor: Dr. Marek Osinski May 13, 2013
  2. 2. Table of Contents 1-Introduction Since three semesters ago, a deep investigation on Memristors has been done with the objective of having a better understanding. This same purpose has been crucial of finding new data on what Memristors are. In this report we will focus in different article that cover the simulation, modeling, and implementation that other researcher have done in order to see this device working properly.
  3. 3. Memristors have been defined as a circuit in different ways. While some researchers use amplifier, resistors, capacitors and current source to simulate them, other researcher have built then using digital and analog circuit mixed. Also, other researchers have use just analog technology to create a circuit that can simulate them. Some facts and data that we can consider in order to evaluate them would be I-V curves, Memristance, output voltage- time, input current time, and memristance- input voltage. These facts will be used to compare all three different configurations to provide an analysis of how they benefit or affect the final goal. In this final report we will cover, Soft 3D Retinal Implants with Diamond electrode a way for focal stimulation, article of new technology of retinal implants that have been developed in France. In previous semester we have research it, but this has been involving not just the retinal. This new implants, also, involve the connection with the optic nerve which will open new doors in the science of the Memristors. Also in this report, we will cover the benefits of the different circuits develop for Memristors and how they can benefit other researcher to implement them with real simulation. Some circuits can create be harder to simulate due to the structure that now in these days we do not use in our software. Finally, we will analyze all the information explains. The analysis will cover the overall information investigated and will conclude with the personal comments of how Memristors can be futuristic or not in reality. 2- Emulator for Memristors Circuit Applications The first research paper use to be analyzed is written by Hyongsuk Kim, Maheshwar, Chang ju Yang n Seongik Cho at all which title is Memristors Emulator for Memristors Circuit Applications. This paper covers the emulator and result from the real
  4. 4. fabrication of a Memristors and simulation PSPICE. First, they created a basic structure of a Memristors by using two resistors and one OPAMP, which is: Figure #1: Describe the basic input resistance of the Memristors Emulator and the equivalent circuit. Then they defined the incremental and decremental Memristors with the only difference of the analog inverter in the end of the multiplier. Figure #2: Represent the incremental Figure #3: Represent the decremental Memristors and the circuit symbol. Memristors and the circuit Symbol. They perform one simulation and creation of one complete decremental Memristors by circuit using: 4 n type MOSFET transistors, 4 p type MOSFET transistors, 4 OPAMP, One Analog Multiplier, Capacitor, Resistors and tact switch. This decremental Memristors emulator with expandable nonvolatile architecture is:
  5. 5. Figure #4: A full schematic of the decremental Memristors emulator with nonvolatile architecture. The result gotten from the circuit creates were Oscilloscope I-V, different measures in different nodes of the circuit and Memristance. This circuit is integrated by many interesting parts. First the currents mirrors create with the transistors PMOS and NMOS. Both of them need to be on in order to on indoor to the Multiplexer to come and execute an action. The multiplexer is really interesting due to the fact that the output is equal to 0. Therefore, the signal coming from both of the capacitor and the resistors have to be negative. The parts presented in this box are the parts that are used in the
  6. 6. previous circuit (figure 4). These part have some interesting properties that make the circuit work. In continuation, I will explain each of the parts used in order to have an idea of their parameters. First, I will start with the N type and P Type Metal Oxide Semiconductor Field Effect Transistors. The Model as shown in the box used is ALD116 and ALD1117. There are designed for precision analog applications. They have high input impedance and negative current temperature coefficient. The voltage that this transistors rage is between +2V and +12V systems where low input bias current, low input capacitance and fast switching speed desired (ALD 1). One interesting property is that they offer very large current gain in low frequency. Obviously, both of them are designed to be used in really precise analog circuits. Both of them range in a threshold voltage of (-) 0.4 V to (-) 0.7 with a max of 1.0 V. The IDS(on) is (-) 1.3 A. and all this values are in a temperature of 25 C. The total volume of the chip will be around 27 mm3 . Figure 5: 8 pin plastic package of the ALD1116 and ALD1117, N type and P type transistors. In the other hand we have the OPAMP (TL082CP) that we will explain. It is an operational amplifier that has been designed to offer a wider selection of operations. There are JFET types and they incorporate, well matched, high voltage JFET and bipolar transistors in a monolithic integrated circuit. The device feature high slew rates, low input bias and offset currents, and low offset-voltage temperature coefficient. Offset adjustment and external compensation options [] (Texas Instrument Data sheet 2). Figure #6: Top view of the OPAMP TL082CP
  7. 7. Figure #7: Structural picture of the package with sizes of top view, lateral view, and bottom view. The approximate volume of the chip is around 10.72 mm3 . The last part explained in detail form the circuit will be the analog multiplier. This analog multiplier is a 4 quadrant, low cost, 8 lead package. According to the Analog Devices Data Sheet, The AD633 is a functionally complete, four quadrants, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedances swimming input (Z) (1). Also, the output voltage is a nominal 10 V full scale (low impedance output). It is really accurate device that is calibrated by laser. Its accuracy is around 2% of full scale which makes this device good to use in precise analog devices. This is a simple device at a low cost. The chip does not require any kind of calibration and power supply voltage can range between (-) 8 V to (-) 18 V. The overall transfer function of this multiplier is This device can be well use with application that are related to modulation and demodulation, automatic gain control, power measures, voltage amplifiers, and frequency doublers.
  8. 8. Figure #8 & 9: Represent the basic multiplier connection schematic for the 8-lead AD633 multiplier. The rest of the electronic devices used are well known in the market and does not have anything that can identify them as different that the regular used in the market. However, all of them are represented by a max power of 0.25 W. The result simulated from this circuit created from Kim at all are provided in the following pictures and figures: Figure 10: Picture of the Oscilloscope hysteresis loop of the Memristors Emulator at 100 Hz.
  9. 9. Figure 11: Picture of voltages measure in different points of the circuit. Also, they create expandable model of Memristors Emulators which can connect in series, in parallel, and hybrid connections. In all of three different expandable models, they use the same configuration of the Memristors simple emulator. In series configuration, according to Kim, The voltage of the Memristors when they are connected in series is sum of each of the Memristors (2425), which formula is written as: Formula #1 represents the voltage addition of the Memristors in series where Vm k and vm k are voltage corresponding to the fixed part (Kim 2425). Figure 12: Incremental configuration of Figure 13: Decremental configuration of The expandable Memristors. The expandable Memristors In parallel connection configuration, Kim explained the configuration in parallel with opposite polarities which currents are defined by the formulas: Formula #2: represent the formula of the current in parallel where the M1 and M2 are the values of the meristance. Figure #9: Parrallel connection of two Memristors with opposite polarities
  10. 10. The result shown due to the simulation of the Single, parallel and series configuration of the Memristors in the research document written by Kim are: Figure #14: Representation of the hysteresis loops of the Memristors in a single, serial, parrallel connections when a voltage of Vpp= 2V and the frecuency is equal to 100Hz. Rs= 16KOhms, C=0.1uF, Rt= 4kohms. Figure #15: Simulation Values of the Memristance in all three different cases of single, series, and parallel configurations. Figure #16: different values of the Memristance when the value of the input voltage is changed to 0.1 V amplitude and 5ms width in a single, serial, and parallel configuration. Figure #17: Voltage- current cure of two Memristors circuit connected in series, or in parallel with opposite polarities.
  11. 11. 3- Modeling and Implementing of Oxide Memristors In this document Ting Chang, Patrick Sheridan and Wei Lu at all, which title is modeling and Implementation of Oxide Memristors for Neuromorphic Application, report fabrication, model and implement Memristors devices for neuromorphic applications. They used PSPICE modeling which help them to accurately find data like short term memory and memory enhancement in the device. According to Ting, Memristors are two terminals solid sta