Logic Controllers 1

Logical control Examples of equipments for logical control

Contacts Relay

A relay is a switch which is operated electrically. Many relays use a coil as an electromagnet to act

a switching mechanism. Normally-open contacts connect the circuit when the relay is activated; and disconnect when the relays is deactivated.

Types of logic :

• combinational logic • sequential logic.

1 Boolean algebra

George Boole, (1815-1864), Irish mathematician, Analysis of Logic).: Two values of logical variables: true / false, logical 1 / logical 0, high / low. A logical function is

as follows

( ),...,, cbafy =

where a, b, c are independent variables and y is a dependent variable Diagram describing three logical functions of the three independent variables

2 Definition of logical functions

• Verbal description • Truth tables • Karnaugh maps • Boolean expressions

Let k be a number of logical variables then the number of the possible combinations of values between them, and there are N = 2k ways of assigning an output value to each of these k-input values

CL

Combinational logic a b c

y1 y2 y3

coil

relay contacts

coil

contacts armature

yoke

A coil of wire is wrapped around a soft iron core,

normally open contact

normally closed contact

push button

A simple ON-OFF switch with two terminals

Truth table (for 3 variables there are 8 ways of assigning the output value of y to the input values of the 3 independent variables)

Index Independent variable Dependent variable

a b c y

1 0 0 0 1

2 0 0 1 1

3 0 1 0 0

4 0 1 1 1

5 1 0 0 0

6 1 0 1 0

7 1 1 0 1

8 1 1 1 0

Karnaugh maps

3 variables: 4 variables:

a

b c

b

c d

a

5 variables:

b

c

e a

d

a

y=1

y=0 a=1

a=0

a

y=1

y=0

a=1 b=0

a=0 b=0

y=1

y=1

a=0 b=1

a=1 b=1

b 1 variable: 2 variables:

Logic Controllers 3

3 Basic logical operations (elementary functions)

Not function NOT operation Operator: (see examples below) Formula: ay = ( xyay ¬== ,NOT ) Truth table:

a y

0 1

1 0

Logical disjunction OR operation logical add (join) Operator: +, ∪ Formula: bay += ( bay OR= ) Truth table:

a b y

0 0 0

0 1 1

1 0 1

1 1 1

Logical conjunction AND operation logical multiply Operator: • , ∩ Formula: bay •= ( bay AND= ) Truth table:

a b y

0 0 0

0 1 0

1 0 0

1 1 1

Exclusive OR XOR operation only one out of n Operator: ⊕ Formula: bay ⊕= Truth table:

a b y

0 0 0

0 1 1

1 0 1

1 1 0

Sheffer function (AND-NOT operation) NAND Sheffer stroke operation Formula: bay •= ( bay NAND= ) Truth table:

a b y

0 0 1

0 1 1

1 0 1

1 1 0

Pierce function (OR-NOT operation) NOR Formula: bay += ( bay NOR= ) Truth table:

a b y

0 0 1

0 1 0

1 0 0

1 1 0

Equivalence EQ Formula: bay EQ= Truth table:

a b y

0 0 1

0 1 0

1 0 0

1 1 1

Non-equivalence NEQ Formula: bay NEQ= Truth table:

a b y

0 0 0

0 1 1

1 0 1

1 1 0

Implication belongs to the logical elementary functions. Operator→ , formula babay +=→=

Gates of the rectangular shape NOT (invertor) AND gate OR gate XOR gate

NAND gate NOR gate EQ gate

Distinctive shape NOT (invertor) AND gate OR gate XOR gate

NAND gate NOR gate

A Venn diagram or set diagram is a diagram that shows all possible logical relations between a

finite collection of sets (aggregation of things).

a b

bay += a b

bay •=

a ay =

a b

a b

bay += a b

bay •= a

ay =

= a b

bay EQ= & a b

bay •= a

ay = 1

=1 a b

bay ⊕= 1≤ a b

bay += & a b

bay •=a

ay = 1

1≤ a b

bay +=

Logic Controllers 5

4 Laws and theorems of Boolean algebra

Commutative law

abba +=+ , abba •=• ,

Associative law

( ) ( ) cbacba ++=++ , ( ) ( ) cbacba ••=••

Distributive law

( )cbacaba +•=•+• , ( ) ( ) cbacaba •+=+•+ .

Involution law

aa = .

Duality laws and theorems

http://dictionary.reference.com/ explains duality in math as a symmetry within a mathematical system such that a theorem remains valid if certain objects, relations, or operations are interchanged.

The dual form of a law and a theorem can be obtained by replacement of logical 0 by logical 1 and vice versa and simultaneously by replacement of disjunction by conjunction and vice versa. The logical 1 is the dual value of the logical 0 and disjunction is the dual operation of conjunction:

•↔+↔ and10

Dual forms of laws and theorems Name Logical disjunction Logical conjunction

Laws of complementary 1=+ aa 0=• aa

Operation with 0 and 1 aa =+ 0 aa =•1

Operation with 0 and 1 11=+a 00 =•a

Idempotent law aaa =+ aaa =•

Simplification Theorem abaa =•+ ( ) abaa =+•

babaa +=•+ ( ) babaa •=+•

DeMorgan’s law baba •=+ baba +=•

=•=+ baba baba +=•

Prove of laws and theorems A) Algebraically B) Using the truth table

De Morgan law

a b a b ba + ba + ba • ba • ba • ba +

0 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 0 0 1 1

1 0 0 1 1 0 0 0 1 1

1 1 0 0 1 0 0 1 0 0 De Morgan equivalents

5 Canonical form of logical functions

In Boolean algebra, any boolean function can be expressed in a canonical form using the dual concepts of minterms (minimal terms) and maxterms. Minterms are called products because they are the AND of a set of variables, and maxterms are called sums because they are the OR of a set of variables. The set of variables differs from each other in a subset of variables, which are inverted by the NOT function. We can say that the minterm is a product term in which each of the variables appears once (in either its complemented or uncomplemented form). Thus, a minterm is a logical expression of n variables that employs only the complement operator and the conjunction operator.

For three variables (n = 3) all the minterms are as follows ,cba •• ,cba •• ,cba •• ,cba •• ,cba •• ,cba •• ,cba •• cba •• .

These concepts are called duals because of their complementary-symmetry relationship as expressed by De Morgan's laws, which state that

( ) ( ),...,,NOR,...,,AND zyxzyx = and

( ) ( ),...,,NAND,...,,OR zyxzyx = . Note: ( ) yxyx •=,AND , ( ) yxyx •=,NAND , ( ) yxyx +=,OR and ( ) yxyx +=,NOR . The dual canonical forms of any boolean function are a "sum of minterms" and a "product of

maxterms." The term "Sum of Products" or "SoP" is widely used for the canonical (in simplest or standard) form that is a disjunction (OR) of minterms. Its De Morgan dual is a "Product of Sums" or "PoS" for the canonical form that is a conjunction (AND) of maxterms. These forms allow for greater analysis into the simplification of these functions, which is of great importance in the minimization or other optimization of digital circuits.

Let a truth table be given

a b c y

... ... ... ...

1 1 0 1

1 1 1 0

Logic Controllers 7

A) The formula is composed as a sum of logical products (minterms), which are composed of 3 variables in the form, resulting in the logical 1

...... +••+= cbay

See that 0,1,1 === cba contributes to the sum function value of the logical 1. B) The formula is composed as a product of logical sums (maxterms), which are composed of 3 variables, resulting in the logical 0

( ) ( ) ( )............ ••++••= cbay

See that 1,1,1 === cba contributes to the product function value of the logical 0.

Example:

a b c y

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

A) Sum of conjunctions (SoP) cbacbacbacbacbacbay ••+••+••+••+••+••=

B) Product of disjunctions (PoS) ( ) ( )cbacbay ++•++=

Proof that both the results give the same result Ad A)

( )( )( ) cabbcacbacba

baccbacbacbabaccbacbacba

•=+••=••+••

•=+••=••+•••=+••=••+••

cacaacababay +=•+=•+•+•= Ad B)

( )( ) ( )( ) cabbcabcabcay +=•++=++•++=

6 The use of Karnaugh maps to creation a logical function

A Karnaugh map is a graphical way of minimizing a Boolean expression based on the rule of complementation. It works well if there are 2, 3, or 4 variables, but gets messy or impossible to use for expressions with more variables than that.

A Karnaugh map uses a new term called a minterm. For a boolean function of n variables x1, x2, …, xn, the minterm is a product term in which each of the n variables appears once (in either its complemented or uncomplemented form). Thus, a minterm is a logical expression of n variables that employs only the complement operator and the conjunction operator.

The idea behind a Karnaugh map (Karnaugh, 1953) is to draw an expression’s truth table as

matrixes in such a way that each row and each column of the matrix puts minterms that differ in the value of a single variable adjacent to each other. Then, by grouping adjacent cells of the matrix, you can identify product terms that eliminate all complemented literals, resulting in a minimized version of the expression.

The Karnaugh map is used to produce a minimal sum of products implementation of an expression by drawing rectangles around groups of adjacent minterms in the map; each rectangle will correspond to one product term, and the full expression will be constructed as the OR (sum) of all the product

terms. The goal is to have as few product terms as possible, which implies that each product term will account for as many minterms as possible.

Example

Let a truth table be specifying the logical function of the form

cbacbacbacbay ••+••+••+••= The Karnaugh map can be created on the base of this function. Now the solution of the problem starts. It is required to design the minimal form of this function

using the Karnaugh map.

1: ( ) cabbcacbacba •=+••=••+•• 2: ( ) baccbacbacba •=+••=••+•• 3: ( ) cbaacbcbacba •=+••=••+••

Notice that two minterms composed of 3 variables gives one minterm composed of 2 variables,

which simplified considerably the resulting formula. The final minimized formula is as follows

cbbacay •+•+•=

Here are the rules for location the circles enclosing a part of the Karnaugh map of the rectangle shape:

• Every minterm must be inside at least one circle, but there must not be any zeros inside any circle.

• Every rectangle has to be as large as possible.

• Circles may wrap around to include cells in both the leftmost and rightmost columns. likewise for the top and bottom rows.

• The number of minterms enclosed in a circle must be a power of two (1, 2, 4, 8, or 16 minterms for 4-variable maps).

• Some functions have "don’t care" conditions, which are combinations of inputs that will never occur, resulting in cases where it doesn’t matter whether the output is a zero or a one. Where these don’t care conditions appear in a Karnaugh Map (usually indicated by X’s instead of ones or zeros), they may be included inside circles or not depending on what will make the circles as few and as large as possible.

.

a

b c

Pairs

a

b c

1 1 1 1

1 2

3

Logic Controllers 9

There are combinations of the possible values of the independent variables, which cannot exist in the real world (for instance the lift cab cannot be simultaneously in two different floors). In this case the output value is substituted by X. The dependent value is replaced by the value, which is profitable for minimizing the resulting formula.

7 Design of the logical control systems

• Relay • Integrated circuits • Program code.

Relay logic

Logical functions ay = and ay =

Logical functions bay •= and bay +=

a

y = a+b a +V

+V

0V

0V

b

b

y = a a

y = a a

+V

+V

0V

0V

contact(s) relay coil

a

b c

1

1 X

b

c d

a b

c d

a b

c d

a

1 1 1 1

1 1

1 1

1 1

1 1 db •

b

c d

a

1 1

1

1

dc •db •da •

y = ba •

Example

bacay •+•=

Ladder diagram

Function Block diagrams

Integrated circuits (IC)

NAND gate with 2 inputs

SN 7400N

NAND and NOR logical gates are the two pillars of logic, in that all other types of Boolean logical gates (i.e., AND, OR, NOT, XOR, XNOR) can be created from a suitable network of just NAND or just NOR gate(s). They can be built from relays or transistors, or any other technology that can create an inverter and a two-input AND or OR gate. Hence the NAND and NOR gates are called the universal gates.

Main tricks The design of the logical AND using only NAND gates

( )bababay •=•=•=

The design of the logical OR using only NAND gates

bababay •=+=+=

The design of the logical AND using only NOR gates

bababay +=•=•=

The design of the logical OR using only NOR gates

( )bababay +=+=+=

output

+5V

0V

input T1 T2

T3

K

E

v1

+

another gates

y a

+V 0V

b

c

a

Logic Controllers 11

NOT AND OR

NA

ND

NO

R

Integrated monolithic circuits on the market are produced with the certain number of inputs, for

example 2, 4, 8. The design of the logical circuit has to respect this fact. The important part of a task to be solved is

the number of the gate inputs. In the other word it is needed to design the control system flowchart by using only gates with a given number of inputs.

The design of the control system flowchart for the logical disjunction or conjunction composed of 3 variables by using NAND gates with only 2 inputs

( ) ( ) ( ) ( ) ( )( ) 63534321 HHHHHHHH

cbacbacbacbacbacbay

=•=•=••=

=••=••=+•=++=++=++=

( ) ( ) ( ) ( )( ) ( ) ( ) 4321 HHcHcHcbacbacbacbay ==•=•=

••=••=••=••=

The symbol Hn designates a gate, indexed by n, with 2 inputs. When the chart for the logical product of 3 variables (a, b, c) is drawn, you should start at the gate H4 having as an input the output of the gate H3, and then you should continue by connecting the output of the gate H2 and the variable c to the input of the gate H3. …

The design of the control system flowchart for the logical disjunction or conjunction composed of 3 variables by using NORD gates with only 2 inputs

( ) ( ) ( ) ( )( ) ( ) ( ) 4321 HHcHcHcbacbacbacbay ==+=+=

++=++=++=++=

( ) ( ) ( ) ( ) ( )( ) 63534321 HHHHHHHH

cbacbacbacbacbacbay

=+=+=++=

=++=++=•+=••=••=••=

yH =4 & c

H2

3H&

4H 3H

bay += a b

1≤

1≤

ba +bay •=a

b

a

b

1≤

1≤

1≤

a 1≤

a

bay +=

&

a &

b &

a

b

bay •= & a

b

ba • & a & a

Programmable Logic Controllers - PLC Computer tools supporting the design of logic control systems are based on

• Ladder Diagram – LAD, Kontaktplan – KOP in German • Control System Flowchart – CSF, Funktions plan – FUP in German • Statement list – STL, Anweisungsliste – AWL in German • Structured Text (ST)

8 Example

The first part of the truth table

The second part of the truth table

a b c d y A b c d y Karnaugh map

0 0 0 0 0 1 0 0 0 0

0 0 0 1 1 0 0 1 1

0 0 1 0 0 1 0 1 0 0

0 0 1 1 1 1 0 1 1 1

0 1 0 0 0 1 1 0 0

0 1 0 1 0 1 1 0 1 1

0 1 1 0 0 1 1 1 0 0

0 1 1 1 0 1 1 1 1 0 The minimized form of the logical formula

cbadby ••+•=

Ladder diagram

To create a block diagram the formula has to be adapted to the gates which are employed

For NAND gates

( )cbadbcbadbcbadby ••••=••+•=••+•=

b

&

&

b &

( )cba ••cb • & cb • &

y

& c

c

a&

b

dcba

db • d

y b

+V 0V

b

d

a c

c d

a 1

1

1 1

b X

X 1

Logic Controllers 13

For NOR gates

( ) ( ) ( ) cbadbcbadbcbadbcbadby ++++=+•++=••+•=••+•=

9 Sequential logic

Let a logical function be defined by a formula

( ),...,,, cbayfy P=

where yP is the past value of the boolean variable y

Example of a liquid level control system based on a logical controller

Controlled system

Valves are considered to be either fully opened (y = 1 or z = 1) or completely closed (y = 0 or z = 0). The drain valve is controlled independently of the inlet (fill) valve. The liquid level gauge provides a logical signal 1 if the liquid level is above a certain level or a logical signal 0 if the level is below mentioned level.

The Karnaugh map for the output logical variable y of the logical control system.

yP

h1 h2

1 1 1 X

y

X 0 0 0

A tank which is filled with a conductive liquid

h1 h2 ON-OFF sensors based on electrical conductivity

y

z

h1 – high level

h2 – low level

Fill valve

Valve for draining

Tank Two liquid level gauges

CL a b y3P

y1 y2 y3

Memory

Clock

b

b y

d

b

dcba

c

1≤

aa 1≤ ba +1≤

1≤

1≤

cba ++

d 1≤ 1≤

db +

1≤

1≤

Logical function for the combinational logic

12 hyhy P •+=

Adapting for using NAND gates

1212 hyhhyhy PP ••=•+=

10 Flip-flops ;

A flip-flop or latch is a circuit that has two stable states and can be used to store state information. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices are described as flip-flops. Logic circuits are divided into synchronous and asynchronous types. In synchronous sequential circuits, the state changes only at discrete times in response to a clock signal. In asynchronous circuits the state of the device can change at any time in response to changing inputs. Mechanical flip-flop

RS type which changes its state asynchronously

Timing diagram

Truth table Karnaugh map for the output logical variable Q

S R Q

0 0 Previous output

0 1 0

1 0 1

X X ?

PQRSQ •+=

Where QP is the past value of Q

The logical function for design a Ladder Diagram

( )SQRRSRQQ PP +•=•+•=

The output is energized even when the input ceases. This is called a latch circuits.

Q S

+V 0V

R QP

QP

S R

0 0 1 1

Q

1 X X 0

S

R Q

Q

Q

S

R

time

set

reset

output H - high L - low

1h&

1hyP •

&

&

y

1h

2h

Logic Controllers 15

The use of the NOR and NAND gates to build the flip-flops of the RS type

Gates NOR: ( ) ( )SQRSQRQ PP ++=+•= Gates NAND: ( ) SQRSQRQ PP ••=+•=

D type which change its state synchronously with a clock signal The D flip-flop can be viewed as a memory cell, which is set or reset synchronously with a clock signal

JK type which change its state synchronously with a clock signal

Truth table: J K 1+nQ

0 0 nQ

0 1 0

1 0 1

1 1 nQ

11 Using flip-flop circuits in sequential circuits

The use of the RS type flip-flops The problem is to design two logical function

generating the set and reset signals:

( )( )21

21

,,hhfRhhfS

R

S

==

A liquid level control system based on a

logical controller

Function for setting the set input of the RS flip-flops

2hS =

Function for setting the reset input of the RS flip-flops

1hR =

h1

h2 0

1 X

R

0

h1

h2 1

0 X

S

0

S

R Q

Q

S

R

y

h1 h2

Sf

Rf

Q

Q Clock

JKCRS

Synchr.

Asynchr.

Q

Q

Q

Clock

D

time

D

Clock

Timing diagram

& Q

&

&

Q

R

& SS

R Q

Q 1≤

1≤

Contactors A contactor is an electrically controlled switch used for switching a power circuit. The contactor is

similar to a relay except with higher allowed current ratings to control an equipment of the high power level. A contactor is controlled by a circuit which has a much lower power level than the switched circuit.

Contactor

The contactors are used to control electric motors, lighting, heating, capacitor banks, and other electrical loads.

Pushbuttons are often color-coded to associate them with their function. Commonly used colors are

red for stopping the machine or process and green for starting the machine or process. The use of JK flip-flop type for counting pulses Hexadecimal counter for 15,,0 =N

It is assumed that if the J and K inputs are not connected to the other outputs of gates or flip-flops

or are not grounded then J = 1 and K = 1 0

01

12

23

3 2222 QQQQN +++=

S

R Q

Q

Reset

C S

R Q

Q C

S

R Q

Q C

S

R Q

Q C

Input pulses T

Q0 Q1 Q2 Q3 Output 0 Output 1 Output 2 Output 3

Q

S

R QP

Relay coil

Main contacts

Auxiliary contact Lights

220V~ 0V~

Red button

Green button

Con

tact

or c

oil

Main contacts

Auxilary contacts

Logic Controllers 17

Timing diagram

Binary-coded decimal counter

Seven-segment display

DP … decimal point

12 IEC 1131 Sequential Function Charts

Sequential function charts are based on • Steps with associated actions • Transitions with associated logical conditions • Directed links between steps and transitions

SFC Sequential configuration

s1, s2, … internal logical variables Transition is enabled if the condition reaches a logical value equal to logical 1 One of steps on the left diagram is active while the others are inactive.

s2

s3 action 2

action 1

s1

condition 2

condition 1

initial step

transition 1

transition 2

step 2

step 3

CL

Decoder Q0 Q1 Q2

yA yB

Q3

yG

Reset

Input pulses T

Q0 Q1 Q2 Q3

≤ 1 Hexadecimal counter &

0123 QQQQy •••= y

Q1

T

Q0

time

Q2

Q3

1

1

0

1

0

0

1

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1 0 3 15 2 ….

SFC Simultaneous Branch In a simultaneous branch, all branches are executed until the transition becomes active.

SFC Selection Branch In a selection branch, only one branch is executed depending on which transition is active.

Program code State variables s1, s2, …, transition conditions for transition p1, p2, … and actions a1, a2, …, The initial value of inic after power ON is zero

Example of sequential function chart for the RS type flip-flops

.

S

R Q

Q START

STOP

1a

1a s2 a1 = 1

s1

Button STOP

Button START Switch OFF

Switch ON

1

...

...

1

32

21

43223

32112

211

==

==

•+•=

•+•=

+•+•=

−

inicsa

sasa

sspsssspss

inicsspss

nn

nn

Assignment of the outputs

Cyclic changing of states

0=inic

Divergent and convergent OR

Divergent and convergent AND

Logic Controllers 19

Functional diagram of a technological process

Sequential function chart

t1 ………… temperature sensor with binary output h1, …, h6 … sensors of liquid level with binary output SFC Action Qualifiers

N Non-stored Terminate when the step becomes inactive. S Set (stored) Continue after the step is deactivated, until the action is reset. R Reset Terminate the execution of an action previously started with the S, SD, SL,

or DS qualifier. L Time Limited Start when step becomes active and continue until the step goes inactive or a

set time passes. D Time Delayed Start a delay timer when the step becomes active. If the step is still active

after the time delay, the action starts and continues until deactivated. P Pulse Start when the step becomes Active/Deactive and execute the action only

once. SD Stored and

Time Delayed Stored and time Delayed Action starts after time delay, continues until reset.

DS Delayed & Stored

If step is still active, action starts after time delay, continues until reset.

SL Stored & Time Limited

Action starts when step becomes active, continues for a set time or until reset.

sn R

Qualifier

Action 1 S Action 2

Description

a1 a2

Variable

s3

s1

h1

Start Initial step

Waiting for finishing heating the tank 2

v1 = 1 s2

s5

v2 = 1 s4

p1 = 1

s6

s8

v3 = 1 v4 = 1 s7

v5 = 1

h3

t1

1 - always fulfills condition

542 hhh +•

6h

Waiting for finishing filling up the tank 1

v1

v3

h1

h2

tank

1

v2

v4

h3

h4 t1

p1

h5

h6

v5

tank 2

tank 3

heating

valve 1 valve 2

valve 5

13 PLC programming

Language Standards IEC 1131 is an international standard for PLCs formulated by the International Electrotechnical

Commission (IEC). As regards PLC programming, it specifies the syntax, semantics and graphics symbols for the following PLC programming languages: • Ladder diagram (LD) • Sequential Function Charts (SFC) • Function Block Diagram (FBD) • Structured Text (ST) • Instruction List (IL) Ladder diagrams Equivalency between a ladder diagram and an electrical circuit

North American style of programming, US-type of electrical drawing standard A rung of the ladder diagram looks like as follows

The end rung of the ladder diagram has to be clearly denoted

Internal relays do not exist as real-world switching devices but are only bits in the PLC memory

that behave in the same way as relays. To distinguish internal relay outputs from external relay outputs, they are given different types of addresses. Different manufacturers tend to use different terms for internal relays and different ways of expressing their addresses.

ay =

internal relays

ay =

end rung

End

ay =

an alternative of drawing the normal output

a ay =

ay =

ay =

normal output ay =

normally closed contact

ay =

a ay =

ay =

ay =

normal output ay =

normally open contact

Inputs: Contacts Outputs: Coils Ladder Rung 0

Rung 1

Rung 2

Right hand power rail connection

Left hand power rail connection

Lamp

COM 24 V

Pressed button

+ -

The electrical circuit is closed

An electrical equivalent of

the rung 1

Battery

Power flow

End End rung

Logic Controllers 21

Conventions which are adopted for drawing a ladder diagram 1 The vertical lines of the diagram represent the power rails between which circuits are connected.

2 Each rung on the ladder defines one operation in the control process.

3 A ladder diagram is executed from left to right and from top to bottom. When the PLC is in its run mode, it goes through the entire ladder program to the end, the end rung of the program being clearly denoted, and then promptly resumes at the start. This procedure of going through all the rungs of the program is called a scan.

4 Each rung must start with an input or inputs and must end with at least one output. The term input is used for a control action, such as closing the contacts of a switch, used as an input to the PLC. The term output is used for a device connected to the output of a PLC, e.g. a motor.

5 Electrical devices are shown in their normal condition. Thus a switch which is normally open until some object closes it, is shown as open on the ladder diagram. A switch that is normally closed is shown closed.

6 A particular device can appear in more than one rung of a ladder. For example, we might have a relay which switches on one or more devices. The same letters and/or numbers are used to label the, device in each situation.

7 The inputs and outputs are all identified by their addresses, the notation used depending on the PLC manufacturer.

(W. Bolton: Instrumentation and control systems, 2004 Elsevier) The ladder diagram for control of the liquid level in the tank The liquid level control system can be described by the ladder diagram. Both the level contacts are normally (above the level of a liquid) closed. Energizing the fill valve activates the contact designated by “Fill valve”. Timer

In many control tasks it is necessary to delay the connection or disconnection of a contact for a specified time interval. For example, a motor or a pump might need to be controlled to operate for a particular interval of time, or be switched on after some time interval. PLCs are equipped by built-in timers. Timers count fractions of seconds or seconds using the internal CPU clock. Ladder program with a delay-on timer

The Timer as an internal output switches on the Timer as an internal relay after a delay. Reactivation of the Timer is inefficient unless a preset delay has not been reached.

Scanning Process • Read Inputs to Input RAM • Execute Program • Diagnostics and Communication tasks • Update Outputs from Output RAM • Repeat scan

Input Timer

Timer Output

On

Off

Output

Time 0

Low level High level

Fill valve

Fill valve

Modes of operation • Run mode (the processor begins the scanning process as previously described) • Program mode (the processor stops scanning the ladder program and (typically) all the outputs are

turned off) • Test mode (this mode is identical to the RUN mode, except all outputs are disabled (held in their

off state)) Sequential Function Charts and ladder diagrams The Ladder Diagram logic for a typical step

Once the Step/Transition logic has been completed then the actions can written to Outputs. In a

simple system outputs can be driven directly from the states

„Step 1“ „Output 1“

„Step 3“

„Step 5“

sn

sn-1

Trans pn Step n-1

Step n

„Step n-1“ „Trans pn“ „Step n“

„Step n-1“ S

R

Previous step Transition condition Current step

Previous step

All input Terminals

Input Image Table

All output Terminals

Output Image Table

Controlled process

Execute program by solving the ladder diagram

Logic Controllers 23

14 Programmable Logic Controllers

Galvanic separation of PLC internal circuits and external circuits Relay and opto-isolator devices

Using relays

Using optrons

Programmable logic controller

Allen-Bradley PLC installed in a control panel PLC SIMATIC S7-300

Jiří Tůma 16.2.2013

Inpu

t uni

t

Out

put u

nit

Syst

em m

emor

y

Ope

ratio

nal m

emor

y

Mic

ropr

oces

sor

Prog

ram

mem

ory

bus

External circuits amplifier LED + phototransistor

PLC

PLC

External circuits

RC filter optron External circuits PLC

outp

ut

External circuits

inpu

t

Programable Logic Controller

+24V

relays valves lamps, lights

Input binary signals

PLC acts as an electric switchboard which is a device that directs electricity from one source to another.

Output binary signals

E