Hitachi Hardware Architecture:

Hitachi USP/USP-V/USP-VM architecture is based on Hi-Star/Hierarchical Star/Universal Star Architecture.

USP/USP-V/USP-VM architecture comprises of Shared memory Cache Memory Non-blocking cache switches. Total Cache bandwidth – 68GB/S Total bandwidth – 81GB/S

USP/USP-V/USP-VM Architecture Components:

CHA – Channel Adapter or FED (Front End Director): CHA or FED Controls the Flow of data transfer between the hosts and the cache

memory. CHA is a PCB board that contains the FEDs. FED is also called the CHA. FED ports can be FC/FICON. 2 ports are controlled by 1 processor. There can be 192 FC ports in USP/USP-V/USP-VM – Data transfer speeds of up to

4Gbps/400MBPS. FC ports can be 16 or 32 ports per pair of CHA. FC ports support both long and short wavelengths to connect to hosts, arrays or switches.

There can be 96 FICON ports in USP/USP-V/USP-VM – Data transfer speeds of up to 2Gbps/200MBPS. FICON can have 8 or 16 ports per pair of FICON CHA. FICON ports can be short or long wavelengths.

In USP100 – Max 2 FEDs In USP600 - Max of 4 or 6 FEDs In USP1100 – Max of 4 or 6 FEDs

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DKA – Disk Adapter or BED (Back End Director): DKA or BED is a component of the DKC that Controls the flow of data transfer between

the drive and cache memory. The Disk drives are connected to the DKA pairs by Fibre cables using an arbitrated loop

FC-AL technology. Each DKA has 8 independent fibre back end paths controlled by 8 back-end directors

(micro-processors). Max of 8 DKAs, hence 64 backend paths. Bandwidth of FC path = 2Gbps or 200MBPS In USP the number of Ports per DKA pair is 8 and each port is controlled by a

Microprocessor (MP. The USP V can be configured with up to 8 BED pairs, providing up to 64 concurrent data

transfers to and from the data drives. The USP VM is configured with 1 BED pair, which provides 8 concurrent data transfers to

and from the data drives. In USP100- Max of 4 BEDs In USP600 – Max of 4 BEDs

SM – Shared Memory This is the memory that stores the configuration information and the information and

status for controlling the Cache, Disk Drives and Logical devices, the path group arrays also reside in the SM

Size of the shared memory is determined by the A. Total Cache Size, B. Number of LDEVs, C. Replication Software in use.

Non-Volatile Shared Memory contains the cache directory and configuration information of the USP/USP-V/USP-VM

SM is duplexed and each side of the duplex resides on the first two shared memory cards, which are in cluster 1 and 2.

In the event of power failure the SM data is protected for up to 36 hours of battery back-up in USP-V and USP-VM.

In the event of power failure the SM data on the USP is protected for up to 7 days. USP can be configured up to 3 GB from 2 cards or 6 GB from 4 cards. USP-V can be configured up to 32 GB of Shared memory USP-VM can be configured up to 16 GB of shared Memory.

CM – Cache Memory This is the memory that stores the user data in order to perform I/O ops asynchronously

with the reading and writing to a disk drive. USP can be configured with up to 128GB of cache memory in increments of 4GB for

USP100and 600 or 8GB for USP1100 and with 48hours of battery Backup USP-V can be configured with up to 512GB of cache memory USP-VM can be configured with up to 128GB of cache memory. USP V and USP VM, both have a cache back up of power for 36 hours. The cache is divided into 2 equal areas called cache A and cache B on separate cards. Cache A is on cluster1 and Cache B is on Cluster2 All USP models place the read and write data in the cache. Write data is written to both the cache A and B, so the data is duplexed across both the

logic and power boundaries. In USP, the cache access models are:

1. Standard Cache Access model – 2 cache boards. The second set of boards is added once the 64GB of cache is utilized.

2. High Performance Cache access model – 4 cache boards.

ALGORITHMS For Cache Control:1. Hitachi Data systems intelligent learning Algorithm

It identifies random and sequential data access patterns and selects the amount of data to be staged.The amount of data can be a record, partial track, full track or even multiple tracks depending on the access pattern.

2. LRU – Least Recently used AlgorithmWhen a read hit or write I/O occurs in a non-sequential operation, the LRU marks the cache segment as most recently used and promotes it to the top of the appropriate LRU list

3. Sequential pre-fetch AlgorithmUp to one full RAID stripe of 24 tracks of cache is staged.

Cache de-staging process Back up mode – provide power to cache until power resumes. Destaging Mode – Destage to disk all write I/O in cache

CSW – Cache SwitchThis switch provides multiple data paths between CHA/DKA and cache memory

SVP – Service processorExclusive PC for performing all HW and SW maintenance functions

Power Supplies Batteries

USP Features:1. 100% data availability guarantee with no single point of failure.2. Highly resilient, multi-path fibre channel architecture3. Fully redundant, hot swappable components4. Non-disruptive micro-code updates5. Non-disruptive expansion6. Global Dynamic Hot Sparing7. Duplexed Cache with Battery Back-up8. Multiple point-to-point, data and control paths.9. Up to 1152 high throughput Fibre-Channel, dual-active disks10. Supports all open systems and mainframes11. FC, FICON and ESCON connectivity12. Fibre-Channel switched, arbitrated loop and point-to-point configurations.

USP Components:

The DKC consists of 1. Disk Controller – 128 disks can be installed. Each side 64. Front 64+Rear 64. Total=128. The USP

DKC is capable of controlling 1152 disks ( 256 on each DKU – 4 max DKUs = 1024 + 128 DKC disks = 1152 disks)

2. Disk Array Frame – 256 disks can be installed – 64 on top, 64 below on the front and 64 on top and 64 below on the rear – totaling 256 disks.

3. DKC contains: CHA/FEDs DKA/BEDs Cache Memories Shared memories CSWs HDU boxes containing disk drives Power supplies Battery Box

4. The DKC unit is connected to a Service processor SVP, which is used to service the storage sub-system, monitor its running condition and analyze faults.

5. The DKU consists of HDU - Each HDU box containing 64 disks. Cooling Fans AC power supply

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VSP - Virtual storage Platform Architecture Components:

1. Based on SAS Architecture.2. Can be configured in many ways

Small One Rack to large 6 rack with 2 DKC chassis Up to 2048 HDD or 256 SSD 512 GB of total cache

3. Has 1 or 2 Engine. Each Engine is one DKC4. DKC/Controller Chassis Components: FEDs –

Min of 2 and Max of 8, 16 when the BED slots are also used Contains an internal processor and 128 bytes of buffer memory

Front End Directors. Has DAs BED - 4

Back End Directors. Has Das Min of 2 and Max of 4. Contains DRR – Data Recovery and Reconstruct Contains a Parity generator circuit Supports 8 Fibre paths and 32bytes of buffer/path

DCA – 512GB (256GB in 1 module 3 rack system and 512 GB in case of 2 module 6 Rack system. Data Cache Adapter is the equivalent of Cache Memory on the USP. It Contains the Backup copy of the VSD. Min of 64GB and Max of 256GB in case of 1 module 3 rack systems Min of 128GB and Max of 512GB in case of 2 module 6 rack systems. The Data in the cache is non-volatile and is protected against power loss for 36 hours by

cache backup batteries Shared memory:

Shared memory unlike previous models, is not a separate component, but instead an integral component of the cache memory and first 16GB of the cache memory is used as the shared memory

If COW is used, then the next 16GB is also used. GSW – Grid Switches

Full duplex switches Min of 2 switches to a maximum of 4 Provides interconnection between the FEDs, BEDs and the CMs. They also connect the control signals between the virtual storage directors (MPs) and

the CM boards. Micro-Processor:

Min 2 to Max 4 Quad Core, 2.33 GHz MPs, independent of CHAs and DKAs and can be shared across

BEDs and FEDs VSD

This is the Shared/Control Memory component of the VSP, called the Virtual Storage Directors. DA – Data Accelerator

SAS Controller Port Expanders SVPs – 2 – Both SVPs mounted Controller Chassis 0 Power Supplies – 4 Ten Dual Fan assemblies.

5. DKU – Drive Chassis

Contains HDD or SDD drives

8 SAS switches

Two Types of Drive Chassis: 80 disks capable 3.5” HDDs 128 Disks capable 2.5” HDDs or SSDs

Max number of 3.5” HDDs – 1280 Max number of 2.5” HDDs - 20486. Minimum Configuration:

1 single rack containing one controller chassis in a disk less configuration 1 single rack containing one controller chassis and 1 or 2 drive chassis 1 to 3 racks containing one controller chassis and up to 8 drive chassis.

7. Maximum Configuration: 6 Rack twin version of the minimum configuration, containing 2 controller chassis, up to

16 drive chassis The total space of the highest configuration is 2.5 PB

8. Maximum number of Volumes supported – 64K9. Maximum Bandwidth in Cache path = 128GB/s10. Maximum Bandwidth in Control path = 64GB/S11. Maximum Size of creatable volume = 4TB