2003 Micron Technology, Inc. All rights reserved. Information is subject to change without notice.2003 Micron Technology, Inc. All rights reserved. Information is subject to change without notice.

High Performance Next Generation Memory

Technology and Beyond

Dean Klein, Vice President of Market Development

Micron Technology, Inc.

Data Transfer Rate TrendsPC Main Memory

DRAM bandwidth requirements are doubling approximately every 3 years

SDRAM

DDR

DDR2

DDR3

0133267400533667800933

10671200133314671600

1995 2000 2005 2010Year

Data

Rate

(M

tps)

Predicted

256Mb DDR2 Preferred Memory Solution for 512MB

Dual Channel Systems

Signal integrity limits bus loading at higher transfer rates. No longer able to put 4 DIMMs on one memory channel

Memory Controller

5 1 2 M B

D I M M

Memory Controller

2 5 6 M B

DI M M

2 5 6 M B

D I M M

Dual channel provides 2X the bandwidth

4.26 GB/s4.26 GB/s

Total 4.26 GB/s for DDR533

Total 8.52 GB/s for DDR533

4.26 GB/s

2 5 6M B

D I MM

5 1 2M B

D I MM

2 5 6M B

D I MM

GDDR3 Graphics memory will lead

I/O definition for desktop and server main memory

GDDR3 features

■ 8 Meg x 32 configuration

■ Up to 800 MHz (1600 Mb/s)

■ 1.8V VDD/VDDQ

■ Four internal banks

■ 4n prefetch

■ ODT

■ Calibrated output drive

0

1000

2000

3000

4000

1999 2004

Year

Devic

e D

ata

Rate

(M

b\s

per

Pin

)

2000 2001 2002 2003 2005 2006 2007 2008

DDR3

GDDR4

GDDR3

DDR2

Memory per Pin Data Rate Trends

PC

Graphics

DDR3 Signaling DDR3 requirement is 800 MT/s-1600 MT/s

Migration can leverage from GDDR3 GDDR3 is designed for operation at

1000 MT/s-1500 MT/s DQs on GDDR3 are point to point DQs utilize VDDQ terminated push-pull driversTypical 128 bit Bus/Dual

Load Graphics System

DDR3 PC Data Bus

RCVR

System Controller

RCVR

Term Term

Module 1

Rank 1 Rank 2

Single DIMM in point to

point configuration

On die termination

simulations with two loads

at 1066 MT/s data rate

■ Improved signal

integrity

0.00 0.38 0.75 1.13 1.50 1.88

1.61

1.39

1.16

0.94

0.71

0.49Sig

nal V

olt

ag

e (

V)

Time (nanoseconds)

Reads

0.00 0.38 0.75 1.13 1.50 1.88

1.65

1.41

1.17

0.93

0.69

0.45Sig

nal V

olt

ag

e (

V)

Time (nanoseconds)

Writes

0.00 0.25 0.50 0.75 1.00 1.25

1.80

1.50

1.20

0.90

0.60

0.300.00 0.25 0.50 0.75 1.00 1.25

1.80

1.50

1.20

0.90

0.60

0.30

DDR3 Server Data Bus

RCVR

System Controller

RCVR

Term Term

Module 1 Module 2

RCVR

DRVR

Rank 1 Rank 2

On-die termination

simulations with

two loads at 1600

MT/s data rate

Hubs added to DIMM

drive DRAMs and allow

multiple DIMMs per DQ

BusData Buffer

DRVR

RCVRRCVR

Term Term

RCVR

DRVR

Rank 1 Rank 2

Data Buffer

DRVR

More

DIMMs

High Speed System Bus

Sig

nal V

olt

ag

e (

V)

Time (nanoseconds)

Reads

Sig

nal V

olt

ag

e (

V)

Time (nanoseconds)

Writes