hdl programming fundamentals unit 8: synthesis basics 10.1 highlights of synthesis facts synthesis...

HDL Programming Fundamentals

UNIT 8: Synthesis Basics

10.1 Highlights of SYNTHESISFactsSynthesis is mapping between the simulation (software) domain and the hardware domain.

Synthesis, in this Chapter, can be viewed as Reverse Engineering. The user is provided with the behavioral code and is asked to develop the logic diagram.

Not all HDL statements can be mapped into the hardware domain. The hardware domain is limited to signals that can take zeros, ones, or left open. The hardware domain can not differentiate, for example, between signals and variables as does the simulation (software) domain.

To successfully synthesize the behavior code onto a certain electronic chips, the mapping has to conform to the requirements and constrains imposed by the vendor of the electronic chip.

Several synthesis packages are available on the market. These packages can take the behavior code, map it, and produce net list . In this Chapter we focus on learning how to synthesize the code manually rather than on how to use the synthesizers.

Two synthesizers may synthesize the same code using different number of same gates. This is due to the different approaches these two synthesizers took to map the code. Consider, for example, the VHDL statement y := 2x. One synthesizer approaches this statement as a shift to the left of x; another may approach it as a multiplication and may use a multiplier which usually results in more number of gates than the mere shift.


Formulate a flowchart of the system

Use the flow chart to write a behavioral HDL description

Simulate the behavioral module and verify that the simulation correctly describes the

system

Map the behavioral statements into components and logic gates. See Chapter

10, “Synthesis Basics”.

Verify that the mapping is correct by writing a structural description to simulate the mapped

components and logic gates.

Use CAD tools to download the components and logic gates onto an electronic chip such

as FPGAs

Test the electronic chip to verify the download.


10.2 Synthesis Information from Entity (VHDL) and Module (Verilog)

10.2.1 Synthesis Information from Entity (VHDL)

Listings 10.1-11

10.2.2 Verilog Synthesis Information from Module Inputs/Outputs

Listings 10.12-15


module array1v( start ,grtst );parameter N = 4;parameter M = 3;input start;output [3:0] grtst;reg [M:0] a[0:N];..............endmodule

10.3 Mapping process (VHDL) and always (Verilog)


10.3.1 Mapping the Signal Assignment Statement to Gate-Level Listing 10.16library ieee;use ieee.std_logic_1164.all;entity SIGNA_ASSN isport ( X : in bit; Y: out bit);end SIGNA_ASSN;architecture BEHAVIOR of SIGNA_ASSN isbegin P1: process(X) begin Y <= X; end process P1;end BEHAVIOR;

b) Verilog descriptionmodule SIGNA_ASSN (X, Y);input X;output Y;reg y;always @ (X) begin

Y = X;end

endmodule

X Y


module sign_assn2( X,Y);input [1:0] X;output [3:0] Y;reg [3:0] Y;always @ (X) begin

Y = 2*X + 3; endendmodule X(0)

X(1)

Y(1)

Y(2)

Y(3)

Y(0)1

Verify the synthesis by writing structuraldescription and then simulate

Listing 10.17 Verilog


10.3.2 Mapping Variable Assignment Statement to Gate-Level Synthesis

library ieee;use ieee.std_logic_1164.all; entity parity_even is port ( x: in std_logic_vector(3 downto 0); C: out std_logic);end parity_even;architecture behav_prti of parity_even isbegin P1: process(x)variable c1: std_logic; begin c1 := (x(0) xor x(1)) xor (x(2) xor x(3)); C <= c1; end process P1;end behav_prti;

X(0)X(1)

X(2)X(3)

C

(b)

Listing 10.19


10.3.3 Mapping of Logical Operators

Logical Operator Gate-Level MappingVHDL VerilogAnd & ANDOr | ORNot ~ INVERTERXor ^ XOR


Listing 10.20


10.3.4 Mapping of IF Statement

process (a, x)beginif (a = '1') thenY <= X;elseY <= '0';end if;end process;

Listing 10.21


Listing 10.22 Verilogalways @ (a, X, X1)beginif (a == 1'b1)Y = X;elseY = X1;end

X

Y

X1

a


Listing 10.23 Verilogmodule IF_st(a,Y);input [2:0] a;output Y;reg Y;always @ (a)beginif (a < 3'b101)Y = 1'b1; elseY = 1'b0;endendmodule


Listing 10.24

library IEEE; use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL; entity elseif isport (BP: in natural range 0 to 7; ADH : out natural range 0 to 15); end;

architecture elseif of elseif is begin ADHP: process(BP) variable resADH : natural := 0; begin if BP <= 2 then resADH := 15; elsif BP >= 5 then resADH := 0; else resADH := BP * (-5) + 25; end if ; ADH <= resADH; end process ADHP; end elseif;


Listing 10.25

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity If_store isport (a,X: in std_logic; Y: out std_logic);end If_store;architecture If_store of If_store isbegin process (a, X)

beginif (a = '1') thenY <= X;

end if;end process;

end If_store;

D

clk

Q

Q

a

YX

To reduce the number of components in the hardwareDomain try, if possible, not to write incomplete if statement as in the above example. If possible assignA value to Y as :

else Y <= ‘0’;


Listing 10.26 else if Statement with Gate-Level Logic


10.3.5 Mapping of case Statement

Listing 10.27module case_nostr ( a, b, ct,d);input [3:0] a, b;input ct;output [4:0] d;reg [4:0] d;always @ (a,b,ct)begincase (ct) 1'b0: d = a + b;1'b1: d = a-b;endcaseendendmodule

4

b

ct

4

Adder/subtractor

4

a

5

d


D

clk

Q

Q

ct

d5a

b

4-bit adder

5D flip flops

4

5

4

5

Listing 10.28 case statement with storagemodule case_str ( a, b, ct,d);input [3:0] a, b;input ct;output [4:0] d;reg [4:0] d;always @ (a,b,ct)begincase (ct) 1'b0: d = a + b;1'b1: ;endcaseendendmodule


Listing 10.30 Example of Case with Storagelibrary IEEE;use IEEE.STD_LOGIC_1164.all;package types istype states is (state0, state1, state2, state3);end;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use work.types.all;entity state_machine is port ( A, clk: in std_logic; pres_st: buffer states; Z: out std_logic);end state_machine;architecture st_behavioral of state_machine isbeginFM: process (clk, pres_st, A)variable present : states := state0;beginif (clk = '1' and clk'event )thencase pres_st is

when state0 => if A ='1' thenpresent := state1; Z <= '0';elsepresent := state0;Z <= '1';end if;


when state1 => if A ='1' thenpresent := state2; Z <= '0';elsepresent := state3; Z <= '0';end if;

……..


10.3.6 Mapping of loop Statement Listing 10.32

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity listing10_32 isport (a: in std_logic_vector (3 downto 0);

c: in integer range 0 to 15;b: out std_logic_vector(3 downto 0)); end listing10_32; architecture listing10_32 of listing10_32 is begin shfl: process(a,c) variable result, j: integer;

variable temp: std_logic_vector (3 downto 0); begin

result := 0; lop1: for i in 0 to 3 loop if a(i) = '1' then result := result + 2**i; end if; end loop;

This loop has no Mapping to hardware domain. “result” and“a” are identical in the hardwareDomain.

To limit the number of bits allocated to an integer,always specify its range


if result > c then lop2: for i in 0 to 3 loop

j := (i + 2)mod 4; temp (j) := a (i);

end loop; else lop3:for i in 0 to 3 loop

j := (i + 1)mod 4; temp (j) := a (i); end loop;

end if;

b <= temp; end process shfl;


10.3.7 Mapping of Procedure or task

Listing 10.33 An Example of Taskmodule example_task(a1,b1,d1);input a1,b1;output d1;reg d1;always @ (a1,b1)beginxor_synth( d1,a1,b1);endtask xor_synth;output d;input a, b;begind = a ^ b;endendtaskendmodule


Listing 10.34 An Example of a Procedure


10.3.8 Mapping of Function Statement

Listing 10.35 Example of a functionmodule Func_synth(a1,b1,d1);input a1,b1;output d1;reg d1; always @(a1, b1)begind1 = andopr (a1, b1);endfunction andopr ; input a,b;beginandopr = a ^ b; endendfunctionendmodule


Listing 10.36 Example of a Function


Summary

Steps of Synthesizing any system can be summarized as follows: formulate the flowchart of the system; write the behavioral code of the system; simulate the behavioral code to verify the code; map the behavioral statements into hardware components and gates; write a structural code for the components and gates; simulate the structural code and compare between this simulation and that of the behavioral to verify the mapping; download the components and gates into an electronic chip; test the chip to verify that the download represents the system

The hardware domain is very limited in comparison with the simulation domain. In hardware domain, for example, we can not distinguish between VHDL variables and signals

hdl programming fundamentals unit 8: synthesis basics 10.1 highlights of synthesis facts synthesis...

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hardware domain

verilog synthesis information

synthesis basics

i end loop end

behavior code

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hdl statements