harish krishnaswamy and hossein hashemi€¦ · harish krishnaswamy and hossein hashemi university...

A Fully Integrated 24 GHz 4-Channel Phased-Array Transceiver in 0.13μm

CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture

Harish Krishnaswamy and Hossein HashemiUniversity of Southern CaliforniaLos Angeles, CA

Presentation Summary

• Introduction

• Variable Phase Ring Oscillator-PLL Phased Array

• A 4-Channel 24 GHz CMOS Phased Array Transceiver

• Array Measurement Results

Introduction to Phased Arrays

τ

τ

Controlling the time delay between the N channels “steers”

the EM beam electronically....

Introduction to Phased Arrays

Controlling the time delay between the N channels “steers”

the EM beam electronically.

Phased Array Benefits

• Spatial interference cancellation

• 10log(N) improvement in RX SNR (for active arrays)

• 20log(N) improvement in TX EIRP

θtr

θtr=sin-1(ωΔτ/π)

NΔτ

Δτ

...

24 GHz Frequency Allocations

Industrial, Scientific, Medical Applications

- High Speed Point to Point Wireless Communication

- 250 MHz → 1 Gbps with 16-QAM (assuming 4 b/s/Hz)

UWB Vehicular Radar Applications- Parking Aid, Collision Avoidance, Blind Spot Detection

- 7 GHz BW → 2 cm range resolution

24 G 24.25 G22 G 29 GFrequency (Hz)


• Introduction




Conventional Phased Array Topologies+ Mixer dynamic range eased due to interference cancellation.

- Compact, low-loss, linear RF phase shifters are a challenge on silicon.

+ Versatility

- Mixer and ADC dynamic range must allow for interferers.

- ADCs and DSP are power-hungry.

+ Phase shifters out of the signal path and hence do not affect system performance.

- Mixer dynamic range must allow for interferers.

500

Variable Phase Ring Oscillator (VPRO)

Tunable boundary phase shifter allows for controllable phase progression for beam steering.

0o

Node Voltages (V)

Time (ps)

1.5

-1.5

01000

500

Variable Phase Ring Oscillator (VPRO)

Tunable boundary phase shifter allows for controllable phase progression for beam steering.

-NΔφ

ΔφNode

Voltages (V)

Time (ps)

1.5

-1.5

01000

Transmit Operation

• Each node is routed to a separate antenna signal path.

• PLL ensures 24 GHz operation for all steering angles.

-100

-50

0

50

100

21 24 27 30

ωosc

RLC Phase Shift (deg)

Frequency (GHz)

0o

Transmit Operation

• Each node is routed to a separate antenna signal path.

• PLL ensures 24 GHz operation for all steering angles.

-100

-50

0

50

100

21 24 27 30


Frequency (GHz)

-NΔφ

ωosc

Transmitter Architecture

• Mixers, power splitters, and phase shifters are eliminated.

• VCO pulling is not a concern as VPRO is modulated.

VPRO Injection Locking Properties

Injection Locking Range of a free-running VPRO shows phased array spatial selectivity.

Δθ

Phased Array Factor

Injection Phase Progression Δθ (deg)

Δφ =30o

Locking Range (MHz)

2lock osc

inj

Nsin (Δθ-Δ )Δω ω R(1+tan Δ ) 2= (Δθ-Δ )I A(2Q+tanΔ ) Nsin2

φφφφ

30o 100 200-200 -100

108

64

2

-80-60-40-20

020406080

100

21 24 27 30

VPRO-PLL Response to Injection

At vctrl, the PLL down-converts the injected signals.

ωinj-ωPLL


Frequency (GHz)

ωosc

Receive Operation

lock d VCOctrl

vco div d VCO

Δω K K F(s)v = x K sN +K K F(s)

Spatial Selectivity Frequency Selectivity

Kvco : VPRO Gain, Kd : PFD Gain, Ndiv : Division ratio, F(s) : Loop Filter

Injection Phase Progression (deg) Frequency Offset (MHz)

Down-converted Signal at Vctrl (mV)

-200 -100 0 100 200

Down-converted Signal at Vctrl (mV)

-200 -100 0 100 200

SimulationTheory

TheorySimulation

Receiver Demodulation Capability

+-

+-

+-

+-

+-

+-

+-

+-

Tri-statePFD

ChargePump

LoopFilter

Div. by128

Ref

oBaseband

Output

vctrl

LNA

System suitable for a variety of amplitude, phase and frequency modulation schemes such as QAM, OFDM, etc.

2ctrl osc d VCO

inj VCO div d VCO

Nsin (Δθ-Δ )v ω R(1+tan Δ ) K K F(s)2 x x(Δθ-Δ )P A(2Q+tanΔ )K sN +K K F(s)Nsin2

φφ∝

φφ

Noise Processes in the VPRO-PLL RX

• Noise injected into VPRO results in phase noise.

• PLL dynamics translate phase noise to baseband at vctrl.

Input Noise

Noise Figure of the VPRO-PLL RX Scheme

• Reference, divider, and PFD noise are neglected.

• NF improves with decreasing VPRO bias current.

sin θ : Impulse Sensitivity Function1

In : Noise Modulation Function

1 A. Hajimiri et al., “A general theory of phase noise in electrical oscillators,” JSSC, vol. 32, no. 2, Feb. 1998, pp. 179-194.

2.6

2.7

2.8

2.9

3

3.1

3.2

0 5 10 15

NF (theory)NF (Sim)

Bias Current (mA)

Noi

se F

igur

e (d

B)

4-element 1GHz VPRO and PLLNF (Theory)NF (Sim.)

2π2

n0

1 sin θI (Acosθ)dθ+kT/50NF=

kT/50π ∫

Linearity of the VPRO-PLL RXOscillator Bias Level Kvco Linearity

• Increase in VPRO element current improves linearity.

• Increase in Kvco linear tuning range improves linearity.

Vctrl

Oscillation Frequency

Linear Output Operating Range

π⇒ = bias

-1dB injIP I4

Ifund

IinjItotal

β βFrequency

Must lie in linear region

Phase Shift

System Design Trade-offs

Kvco ↑

Q ↑

Ibias ↑

highly linear for high P-1dB

sensitive to supply noise↓

↑_____↓

↑↑↓

LinearityNFDC Gain

π⇒ = bias

-1dB injIP I4

2π2

n0

1 kTsin θI (Acosθ)dθ+50

NF= kT50

π ∫2osc

VCO

ω R(1+tan Δ )GainA(2Q+tanΔ )K

φ∝

φ

These trade-offs are critical for system optimization.


• Introduction




24 GHz 0.13μm CMOS Phased Array TX+RX

2.35mm

2.15mm

Mixers, power splitters/combiners, and phase shifters are eliminated.

On-chip High Frequency Routing

Substrate-shielded Coplanar Stripline1

• Floating metal strips reduce substrate loss.

• Attenuation constant = 0.28 dB/mm at 24 GHz.

W=10 μm S=13 μm

5 μm5 μm

10 μm

3 μm

2 T.S.D. Cheung et al., “On-chip interconnect for mm-wave applications using an all-copper technology and wavelength reduction,” in ISSCC Dig. Tech. papers, Feb. 2003, pp. 396-501.

On-chip High Frequency Routing

Substrate-shielded Coplanar Stripline1

• Floating metal strips reduce substrate loss.

• Attenuation constant = 0.28 dB/mm at 24 GHz.

W=10 μm S=13 μm

5 μm5 μm

10 μm

3 μm

2 T.S.D. Cheung et al., “On-chip interconnect for mm-wave applications using an all-copper technology and wavelength reduction,” in ISSCC Dig. Tech. papers, Feb. 2003, pp. 396-501.

Frequency (GHz)

S21 (dB)

0 3 6 9 12 15 180

-0.05-0.10-0.15-0.20-0.25-0.30-0.35-0.40

24 GHz VPRO

Phase shifter implemented using 4 more identical tuned stages for symmetry.

-NΔφ

24 GHz VPRO

Phase shifter implemented using 4 more identical tuned stages for symmetry.

29QL

110 pHL

7.5 mAIbias per stage

-NΔφ

Low Noise Input Buffer and Output PA Driver

The VPRO is designed to account for the loading effect of the input buffer and PA driver.

Low Noise Input Buffer

Output PA Driver

6.7 dBNF<-10 dBS11

2.5 mAIbias per stage

1.75 dBmPout

<-10 dBS11

13 mAIbias per stage

Low Noise Input Buffer

Output PA Driver

......

Measured VPRO Performance

Frequency dependence is symmetric with respect to control voltage and phase control.

1k 10k 100k 1M 10M 100M

Frequency Offset (Hz)

-97 to -105 dBc/Hz @ 1MHz

Steer Extreme RightBroadsideSteer Extreme Left

-40

-60

-80

-100

-120

-140Phas

e N

oise

(dB

c/H

z)phase control (V)

Frequency (GHz)

Vctrl (V)

24 GHz CMOS Power Amplifier

• PA is biased for Class AB operation.

• Matching is achieved through spiral inductors and MIMs.

Ibias=78 mA

Measured 24 GHz CMOS PA Performance

• Saturated output power is 12.9 dBm.

• Peak drain efficiency is 19%.

Frequency (GHz)

Gai

n (d

B)

Ref

lect

ion

Coe

ff. (d

B)

Input Power (dBm)

Gai

n (d

B),

Effic

ienc

y (%

)

Out

put P

ower

(dB

m)

24 GHz CMOS Low Noise Amplifier

• Two stage inductor-degenerated design (Ibias=25 mA).

• Input designed for optimal noise performance given power matching requirements.

24 GHz CMOS LNA Measurement Results

Frequency (GHz)

Gain (dB)NF (dB)

Frequency (GHz)

Minimum NF < 6 dB is achieved at 23 GHz.

15

10

55

0

-5-10

109

78

654

19 21 23 25 -25

-20

-15

-10

-5S22 (dB)

-15

-10

-5

0S11 (dB)

24 GHz Integer-N Synthesizer

Synthesizer is designed for a loop BW of 10 MHz, which governs RX frequency selectivity.

Frequency (GHz)

lock d VCOctrl

VCO div d VCO

Δω K K F(s)v = x K sN +K K F(s)

Zoomed In

30 dB

23.7 23.8 23.9 24 24.1 24.2

0 -10-20-30-40-50-60-70-80-90

-100Mea

sure

d Sp

ectr

um (d

Bm

)

Single Channel Receiver Transfer Function

• High selectivity is a function of PLL design parameters.

• Inferred array gain is 42 dB.

Offset Frequency (MHz)

Rec

eive

r Gai

n (d

B)


• Introduction




4-path Array Pattern Measurement Setup

Variable delay elements emulate wave propagation in space.

TX1

TX2 TX3

TX4

4-path Array Pattern Measurements

2-path RX patterns

4-path TX patterns

Patterns are not calibrated and include packaging mismatches.

Performance Summary

>19 %Peak PA Drain Efficiency>24.9 dBm4-element EIRP>12.9 dBmMaximum PA Output Power*

6 dBLNA Noise Figure6 dBSNR Improvement (Ideal)

42 dBTotal Array Gain30 dBReceiver Gain

-97 to -105 dBc/HzVPRO Free-running Phase Noise @ 1MHz10 MHzSynthesizer Loop BW

Transmitter Performance

Receiver Performance

LO Path Performance

2.15 x 2.35 mm2Chip Area0.13 μm CMOSProcess

Technology

*limited by measurement equipment.

Comparison with Prior Works

24 GHz24 GHz24 GHzFrequencyTX+RXTXRXFunctionality

6 dBN/A5 dB (sim.)Front End NF>12.3 %6.5 %N/APA Peak PAE

448No. of Channels

5.1 mm214.28 mm211.6 mm2Area

RX: 0.52 WTX: 0.98 W

1.97 W0.91 WPower Consumption

>24.9 dBm26 dBmN/AEIRP0.13 μm CMOS0.18 μm SiGe0.18 μm SiGeTechnology

This workISSCC’052ISSCC’041

1 H. Hashemi et al., “A fully integrated 24GHz 8-path phased array receiver in silicon,” in ISSCC Dig. Tech. papers, Feb. 2004, pp. 390-534.2 A. Natarajan et al., “A 24GHz phased-array transmitter in 0.18μm CMOS,” in ISSCC Dig. Tech. papers, Feb. 2005, pp. 212-594.

Conclusion

• A VPRO-PLL phased array transceiver architecture is demonstrated that achieves full phased array functionality while eliminating key building blocks such as mixers, phase-shifters and power splitters and combiners.

• Rigorous analysis of this new architecture reveals the capability to handle various phase, frequency, and amplitude modulation schemes (QAM, OFDM).

• A 24 GHz CMOS implementation validates the theoretical claims.

Acknowledgements

This work was partially supported by

• Charles Lee Powell Foundation

• USC Viterbi School of Engineering

Our thanks to

• Arun Natarajan from Caltech

• Mahmood Bagheri and Andrew Stapleton from USC

• Ta-shun Chu, Ankush Goel and the rest of our research group at USC for support and assistance

harish krishnaswamy and hossein hashemi€¦ · harish krishnaswamy and hossein hashemi university...

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