GPS Waypoint NavigationGPS Waypoint NavigationTeam M-2:Team M-2:

Charles Norman (M2-1)Charles Norman (M2-1)Julio Segundo (M2-2)Julio Segundo (M2-2)

Nan Li (M2-3)Nan Li (M2-3)Shanshan Ma (M2-4)Shanshan Ma (M2-4)

Design ManagerDesign Manager: Zack Menegakis : Zack Menegakis

Presentation 4: Gate Level DesignFebruary 13, 2006

Overall Project Objective:Design a chip that navigates an aircraft to pre-determined waypoints.

StatusStatus Design ProposalDesign Proposal

Project chosenProject chosen Architecture ProposalArchitecture Proposal

MATLAB simulatedMATLAB simulated Behavioral Verilog writtenBehavioral Verilog written Behavioral Verilog simulatedBehavioral Verilog simulated

FloorplanFloorplan Structural Verilog writtenStructural Verilog written Structural Verilog simulatedStructural Verilog simulated Floorplan and more accurate transistor countFloorplan and more accurate transistor count

Schematic DesignSchematic Design LayoutLayout SimulationsSimulations

Design DecisionsDesign Decisions AccuracyAccuracy

– Input in decimal format instead of SexgasimalInput in decimal format instead of Sexgasimal

– GPS ~105 feet to 1 footGPS ~105 feet to 1 foot

– Removed Sexgasimal moduleRemoved Sexgasimal module

PowerPower– On/Off Power Control for Logic ModulesOn/Off Power Control for Logic Modules

Clock SpeedClock Speed– Lowest Support Speed: 50 KnotsLowest Support Speed: 50 Knots

– Highest Support Speed: 510 KnotsHighest Support Speed: 510 Knots

– Average Crusting Speed: 70 – 100 KnotsAverage Crusting Speed: 70 – 100 Knots

– 6 different clock speed6 different clock speed

Ripple carry adder   Ripple carry adder   – Consume 60,000 less static power than dynamic power at 1.8VConsume 60,000 less static power than dynamic power at 1.8V

– Smallest in sizeSmallest in size

– 14 transistors half adder 14 transistors half adder

– 16 transistors full adder16 transistors full adder

Clock SpeedClock Speed

Input    Input        –61.44 kHz for input        –61.44 kHz for input        –Reading series => 2048 Hz (61.44kHz/30)    –Reading series => 2048 Hz (61.44kHz/30)

HeadingHeading    –8hz for clock before heading module    –8hz for clock before heading module    –To observe change in both longitude and latitude instead of only     –To observe change in both longitude and latitude instead of only one of one of themthem    –Gives accurate direction and speed    –Gives accurate direction and speed

Output to Black boxOutput to Black box    –5 outputs in series/3 different size => 3 different clocks    –5 outputs in series/3 different size => 3 different clocks    –80hz for output from heading    –80hz for output from heading    –160hz for output from distance    –160hz for output from distance    –240hz for output from waypoint comparator     –240hz for output from waypoint comparator

Design DecisionsDesign Decisions Inputs Inputs

– Latitude & Longitude Coordinates : 1 bit eachLatitude & Longitude Coordinates : 1 bit each– Speed :1 bit Speed :1 bit – Altitude : 1bit Altitude : 1bit – Mode : 2-bit unsignedMode : 2-bit unsigned

Input to Black box Input to Black box – Atan2 Calculator(2) : 2 bits each / 4 bits totalAtan2 Calculator(2) : 2 bits each / 4 bits total– Square Root Calculator: 1Square Root Calculator: 1

Output from Black boxOutput from Black box– Atan2 Calculator(2) : 9 bits each / 18 bits totalAtan2 Calculator(2) : 9 bits each / 18 bits total– Square Root Calculator: 9 bitsSquare Root Calculator: 9 bits

Output Output – Angle Correction : 9-bit 2’s complementAngle Correction : 9-bit 2’s complement– Speed Correction : 10-bit 2’s complementSpeed Correction : 10-bit 2’s complement– Altitude Correction : 16-bit 2’s complementAltitude Correction : 16-bit 2’s complement

TotalTotal– 72 bits72 bits

Overflow CaseOverflow Case

Problem : Flying over the border +180 to -180

Solution : if either longitude is negative and it’s close to the border, add 360 to the negative value

Block Level System DiagramBlock Level System Diagram

Transistor EstimatesTransistor EstimatesComponentComponent Last CountLast Count Recent CountRecent Count

FSMFSM 214214 214214

SRAMSRAM 22202220 25402540

Registers/BuffersRegisters/Buffers 18121812 61006100

Speed Comparator Speed Comparator

Angle ComparatorAngle Comparator

Altitude ComparatorAltitude Comparator

Waypoint ComparatorWaypoint Comparator

360360

396396

630630

25002500

380380

470470

750750

29002900

Heading CalculatorHeading Calculator 13041304 26002600

Distance CalculatorDistance Calculator 20122012 30203020

Speed CalculatorSpeed Calculator 778778 10701070

(2)Sexgasimal (2)Sexgasimal 26582658 00

TotalTotal 17,54217,542 2010020100

Behavior VerilogBehavior Verilog /* Clock converter from 61.44KHz to 160Hz *//* Clock converter from 61.44KHz to 160Hz */ module mclkmodule mclk (output clkm,(output clkm, input clock);input clock); reg [8:0] s384;reg [8:0] s384; always @(posedge clock) beginalways @(posedge clock) begin if(s384 < 383)if(s384 < 383) s384 <= s384 + 1;s384 <= s384 + 1; elseelse s384 <= 0;s384 <= 0; endend

assign clkm = (s384 == 383);assign clkm = (s384 == 383); endmoduleendmodule

/* Clock converter from 240Hz to 80Hz *//* Clock converter from 240Hz to 80Hz */ module lclkmodule lclk (output clkl,(output clkl, input clock);input clock); reg [9:0] s3;reg [9:0] s3; always @(posedge clock) beginalways @(posedge clock) begin if(s3 < 767)if(s3 < 767) s3 <= s3 + 1;s3 <= s3 + 1; elseelse s3 <= 0;s3 <= 0; endend

assign clkl = (s3 == 767);assign clkl = (s3 == 767); endmoduleendmodule

/* Current Latitude Register *//* Current Latitude Register */module curlat_regmodule curlat_reg (output reg [29:0] curlat,(output reg [29:0] curlat, input lat,input lat, input [4:0] num,input [4:0] num, input clock);input clock); always @(posedge clock) beginalways @(posedge clock) begin curlat[num] <= lat; curlat[num] <= lat; endendendmodule // curlat_regendmodule // curlat_reg

/* All inner registers *//* All inner registers */module inputsmodule inputs (output reg [29:0] curlatrg, curlonrg, prelat, prelon,(output reg [29:0] curlatrg, curlonrg, prelat, prelon, output reg [14:0] curaltrg,output reg [14:0] curaltrg, output reg [8:0] curspdrg,output reg [8:0] curspdrg, output clk,output clk, input [29:0] curlat, curlon,input [29:0] curlat, curlon, input [14:0] curalt,input [14:0] curalt, input [8:0] curspd,input [8:0] curspd, input [4:0] num);input [4:0] num);

assign clk = (num[4]&num[3]&num[2]&num[1]);assign clk = (num[4]&num[3]&num[2]&num[1]);

always @(posedge clk) beginalways @(posedge clk) begin curlatrg <= curlat;curlatrg <= curlat; curlonrg <= curlon;curlonrg <= curlon; prelat <= curlatrg;prelat <= curlatrg; prelon <= curlonrg;prelon <= curlonrg; curaltrg <= curalt;curaltrg <= curalt; curspdrg <= curspd;curspdrg <= curspd; endendendmoduleendmodule

Structural VerilogStructural Verilogmodule wp_comp( output result, output [29:0] lon_change, lat_change, input [29:0] curlonin, curlatin, wplatin, wplonin, input control);

wire [29:0] rcurlat, rcurlon, rprelat, rprelon, lat, lon, curlat, curlon, prelat, prelon, wplat, wplon, preresult; wire [29:0] S, S2, S3, S4; wire w1, w2, w3, w4, w5, w6, w7; and c1[29:0](curlat[29:0], curlatin[29:0], control);and c2[29:0](curlon[29:0], curlonin[29:0], control);and c3[29:0](wplat[29:0], wplatin[29:0], control);and c4[29:0](wplon[29:0], wplonin[29:0], control); and g1(w1, curlon[29], curlon[28], curlon[26]), g2(w2, ~curlon[27], ~curlon[25]), g3(w3, ~wplon[29], ~wplon[28], ~wplon[26]), g4(w4, wplon[27], wplon[25]), g5(w5, w1, w2), g6(w6, w3, w4), g7(w7, w5, w6);//if w7 is high, our current long is neg and g8(w8, ~curlon[29], ~curlon[28], ~curlon[26]), g9(w9, curlon[27], curlon[25]), g10(w10, wplon[29], wplon[28], wplon[26]), g11(w11, ~wplon[27], ~wplon[25]), g12(w12, w8, w9), g13(w13, w10, w11), g14(w14, w12, w13);//if w14 is high, our previous longitude is neg

TwosCompAdder a(30'b010101011101010010101000000000, curlon, 1'b0, S), b(30'b010101011101010010101000000000, wplon, 1'b0, S2);

//this can be OPTIMIZED by ANDing the select line with the 360 right before it is added to the number thirtybitmux2to1 p(curlon, S,w7,rcurlon), q(wplon, S2, w14, rprelon);

TwosCompAdder c(wplat, curlat, 1'b1, lat_change); TwosCompAdder d(rprelon, rcurlon, 1'b1, lon_change); //This logic checks to see if the change in lat and lon are both zero (if we are at waypoint, 'result' is high) nor n1[29:0](preresult[29:0], lat_change[29:0], lon_change[29:0]); and a1(ppreresult0, preresult[3], preresult[2], preresult[1], preresult[0]), a2(ppreresult1, preresult[7], preresult[6], preresult[5], preresult[4]), a3(ppreresult2, preresult[11], preresult[10], preresult[9], preresult[8]), a4(ppreresult3, preresult[15], preresult[14], preresult[13], preresult[12]), a5(ppreresult4, preresult[19], preresult[18], preresult[17], preresult[16]), a6(ppreresult5, preresult[23], preresult[22], preresult[21], preresult[20]), a7(ppreresult6, preresult[27], preresult[26], preresult[25], preresult[24]), a8(ppreresult7, preresult[29], preresult[28]), a9(ppreresult8, ppreresult0, ppreresult1, ppreresult2, ppreresult3), a10(ppreresult9, ppreresult4, ppreresult5, ppreresult6, ppreresult7), a11(result, ppreresult8, ppreresult9); // assign result= ( (lat_change == 0) && (lon_change == 0));

endmodule // wp_comp

SRAM SchematicSRAM Schematic

Metal DirectionsMetal Directions

Vdd, Gnd, Local InterconnectMetal 1: HorizontalMetal 2: Vertical

Clk, Global InterconnectMetal 3: HorizontalMetal 4: Vertical

ProblemsProblems Pins -> buffers -> clock -> transistor counts Pins -> buffers -> clock -> transistor counts

increased!!increased!! Over flow cases = transistor counts BOOM!Over flow cases = transistor counts BOOM!

What’s Next…What’s Next…

Here’s what’s on our agenda for next Here’s what’s on our agenda for next week…week…

Finish Module SchematicsFinish Module Schematics Creating Module LayoutCreating Module Layout

Questions?Questions?Comments?Comments?

Ideas?Ideas?