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Further System Fundamentals Section 6

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Page 1: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Further System Fundamentals

Section 6

Page 2: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Diagram of CPU including control unit, ALU, address bus and memory (RAM)

Machine instruction cycle: fetch, decode, execute and store

Definitions: Word, Register, Address. Be able to use these words in descriptions of the machine instruction cycle

You do not need to know specific registers

Stuff you need to know for SL

Page 3: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Stuff you need to know for SL

Control Unit

Arithmetic Logic Unit

(ALU)

CPU

Memory (RAM)

Address bus

Data bus

Fetch, decode, execute and store…Word: A group of bits that can be addressed, transferred and manipulated as a single unit by the central processing unit.Register: A part of internal storage that has a specified storage capacity and is usually intended for a specific purpose.Address bus: Pathway from memory to processing unit that carries the address in memory to and from which data is transferred.Data bus: The pathway between the memory or peripheral and processing unit that carries data for processing or data that has been processed. ALU: Arithmetic Logic Unit. A part of the computer that performs arithmetic operations, logic operations and related operations.

Page 4: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Processor diagramDescribe the functions of these registers in

the fetch-execute cycle:AccumulatorInstruction RegisterProgram Counter

Describe the function of an interrupt registerDescribe how buses are used to link the CPU,

RAM, ROM and cache

Stuff you need to know for HL

Page 5: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Processor diagramAccumulator: A group of storage registers in the ALU that hold data temporarily while it is processed and before it is transferred to memory.Instruction Register: the part of a CPU's control unit that stores the instruction currently being executed or decoded.Program Counter: A register that holds the address of the next instruction to be fetched in the fetch execute cycle.Interrupt: A suspension of a process, such as the execution of a computer program, caused by an external event, performed in such a way that the process can be resumed. (An example might be a printer running out of paper. When this happens an interrupt is triggered which tells the CPU to stop what it's doing to alert the user about the printer problem.)

Page 6: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Address bus: Pathway from memory to processing unit that carries the address in memory to and from which data is transferred.

Data bus: The pathway between the memory or peripheral and processing unit that carries data for processing or data that has been processed.

Control bus: The bus that carries commands to the CPU such as read/write.

Buses

Page 7: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

On your own, decide in what order the following play their role in the fetch-execute cycleAccumulatorData busALUInstruction RegisterProgram CounterAddress busRAM

In pairs, take it in turns to describe the events that make up the machine instruction cycle, with reference to the above

Task

Page 8: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Past paperquestionanswer

Page 9: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Past paper questionMay 2011 HL Paper 1

Page 10: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Past paper question answer

Page 11: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

This is an interactive simulation of the fetch-execute cycle http://homepages.feis.herts.ac.uk/~msc_ice/fe2

Wikipedia’s take http://en.wikipedia.org/wiki/Fetch-execute_cycle

Resources

Page 12: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Magnetic Disk Storage

Section 6.2

Page 13: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

The disk drive

(You don’t need to know this, but it provides a little context.)

Page 14: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A. TrackB. Geometrical

Sector (or “Zone”)

C. SectorD. Cluster

The disk

Page 15: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Each sector is used to store a block of data. A block of data is typically 512 bytes, and a block represents the smallest unit that can be independently read from or written to.

When trying to access a particular block, Access Time = Latency + Seek Time + Transfer TimeLatency (rotational delay) – the time taken for

the disk to spin round to the right sectorSeek time – the time taken for the read head

to be moved to the correct trackTransfer Time – the time taken for the data to

be read off the disk

Data Access

Page 16: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Transfer rate can be influenced by fragmentation and the layout of the files. Defragmentation is a procedure used to minimize delay in retrieving data by moving related items to physically proximate areas on the disk.

In stark contrast to hard disk drives, flash memory-based solid state drives do not need defragmentation. The nature of recording information on flash memory wears it out over time, so any unnecessary writes to the SSD are bad. Since the data is accessed differently (solid state electronics compared to physical sectors on a disk) defragmentation is neither necessary nor desirable.

A word on fragmentation

Page 17: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

From memory, draw a plan view diagram of a magnetic disk, showing:TrackSectorActuator armRead head

Annotate your drawing, providing definitions for the terms:BlockLatencySeek timeTransfer time

Task

Page 18: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A good article from Wikipedia on disk drive performance http://en.wikipedia.org/wiki/Disk_drive_performance_characteristics

Resources

Page 19: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Operating Systems

Section 6.3

Page 20: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Define Operating SystemExplain the function of operating systemsOutline the functions of linker, loader and

library manager

Operating System: Software that controls the execution of programs and that may provide services such as resource allocation, scheduling, input/output control, and data management.

How many operating systems can you name?

You need to be able to…

Windows, Mac, Linux, Unix, OS/2, JavaOS, etc, etc

Page 21: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A collection of programsInput/Output (IO) controlFile managementSoftware/hardware

interfaceMemory managementUser interfaceSchedulingProgram execution controlSecurity

Functions of Operating Systems

Page 22: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

User management: login with passwordSystem of privileges, determining which user

or process can do what, eg delete files, shut down the system, etc

Permissions for files and directories, eg read-only

Memory management: keeping one process’s memory space separate from another’s

Built-in firewall

Security features provided by operating sytems

Page 23: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Multi-tasking environment: keeping the memory space of each process safe from other running processes

Multi-user environment: keeping the memory space (primary and secondary) of each user safe from other users

Allocating and deallocating memory for each process

Paging: Dividing virtual memory up into equal-sized blocks (pages)

Paging allows OSs to allocate non-contiguous chunks of memory to the same process, thus reducing fragmentation problems

Memory Management

Page 24: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Virtual memory: The use of secondary memory as if it were primary memory

The OS make it easier for programs to reference memory because they don’t need to worry about the complications of the underlying physical structure of memory and disk

Memory Mangement: Virtual Memory

Page 25: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A linker is a utility program that brings together the object modules, operating system routines and other utility software to produce a complete, executable program.

A loader is program that copies an object program held in memory into the memory area designated by the operating system for execution.

Many programming languages permit user-defined functions to be stored centrally and re-used in various programs. This central storage is called a “library”. A library manager is a utility program that catalogues, pre-compiles and links library modules.

Linkers, Loaders and Library Managers

Page 26: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Further Network Fundamentals

Section 6.4

Page 27: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Review of SL Material

Page 28: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Network devices

Page 29: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Client–Server Architecture

Server1. A program that

provides services requested by client programs.

2. A computer that provides services to another computer connected over a network.

Client (IB’s awful definition)Desktop computer or terminal used to access a computer-based system.

Client-ServerA network architecture in which a system is divided between server tasks performed on the instructions received from clients, requesting information.Client (better

definition)A computer on a network that gains access to central data files, programs, and peripheral devices through a server.

Page 30: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Strictly, a server is a piece of software that listens for client requests on a particular set of ports and responds to those requests

Like with “firewall”, the word “server” can refer to the software, or the hardware on which the software is running

Almost always, a server is a dedicated machine that does nothing else

It’s just a computer with special modifications like extra processors, lots or RAM, huge storage capacity

It’s often big and flat so it can fit in a server rackThere are different types of server: file server, web

server, database server, etc

The Concept of a Server

Page 31: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Every computer linked to every other

No serverCan be faster than

client-server architecture, especially when special algorithms are used, e.g. torrenting

Less secure because services such as filtering, antivirus, firewalls are delegated to each peer

Peer-to-Peer

Page 32: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Port (IB definition): An access point for data entry or exit.

A port can either be hardware (the various sockets at the back of your PC, eg serial port, USB port), or it can be software, in which case it is a logical channel for data communication, identified by a number from 0-65536 (216)

Ports allow computers to decide which application should handle data received on a network, e.g. outgoing email runs on port 25, HTTP runs on port 80, FTP runs on port 20

The Concept of a Port

Page 33: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A firewall is a program that restricts data allowed into and out of a network, on the basis of a set of rules

One of the ways it does this is to close certain portsTry playing World of Warcraft using the school’s internet

connection. You will fail. Why? Because the WoW software uses certain port numbers but the school’s firewall blocks traffic on those ports

The word “firewall” can refer to the software itself, or the hardware on which the software runs. Sometimes a firewall is a dedicated machine that does nothing else

The Concept of a Firewall

Page 34: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

One of Facebook’s server rooms

Page 35: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Do-it-yourself serverimport java.net.Socket;import java.net.ServerSocket;public class EchoServer { public static void main(String[] args) throws Exception { // create socket int port = 4444; ServerSocket serverSocket = new ServerSocket(port); System.err.println("Started server on port " + port);

// repeatedly wait for connections, and process while (true) { // a "blocking" call which waits until a connection is requested Socket clientSocket = serverSocket.accept(); System.err.println("Accepted connection from client");

// open up IO streams In in = new In (clientSocket); Out out = new Out(clientSocket);

// waits for data and reads it in until connection dies // readLine() blocks until the server receives a new line from client String s; while ((s = in.readLine()) != null) { out.println(s); }

// close IO streams, then socket System.err.println("Closing connection with client"); out.close(); in.close(); clientSocket.close(); } }}

This is an echo server written in Java. It listens for connections on port 4444. When it receives something, it just sends the same thing straight back to where it came from.

Page 36: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Gateway (IB definition): A link between two computer systems that converts data passing through into the formats needed for each system.

Generally a gateway is the word for a machine that connects two different networks, most often it sits between an organizational LAN and the internet

A gateway often performs security functions such as content filtering (e.g. blocking Facebook), email spam filtering, virus checking, etc

The Concept of a Gateway

Page 37: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

A proxy is a machine that brokers the communication between two other machines

Only one machine in the school is connected to the internet: the web proxy

Test this by typing “What is my ip” in Google. You will get the same answer whatever school computer you use

When you request a web page, you in fact ask the proxy, and the proxy gets it from the web and gives it to you

Hence it can check you are not going to dodgy websites

A web proxy reduces the need for internet connections and allows security features, e.g. virus checking and content filtering, to be centralised for all users

The Concept of a Proxy

Page 38: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

LAN: Local Area Network. A network of computers within a limited area such as a school or office

WAN: Wide Area Network. A network of computers ranging over an extended area and connecting users in a variety of geographical locations. WANs use a variety of technologies all at the same time, including dedicated “leased lines”, the public telephone system, satellites, the mobile network, etc

LANs and WANs

Page 39: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Provider: Usually short for Internet Service Provider, a provider offers a number of internet-related services, such as: access to the internet email website hosting application/database hosting

There are different sizes of ISP and small ISPs will have their own, larger ISPs who provide them with services.

The biggest ISPs, who don't need their own ISP, are called Tier 1 Providers.

Providers offer different ways to connect to the internet depending on your speed and bandwidth requirements.

For remote customers, or customers where there is limited telephone system coverage, access may be offered by satellite.

Dial-up ISDN ADSL T1 Gigabit Ethernet Fibre OpticSlow ----------------------- Medium ---------------------------- Fast

The Role of Providers

Page 40: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

DirectionsSimplex: One-way, e.g. a radio broadcastHalf-duplex: Two-way, but not at the same time, e.g.

walkie-talkieFull-duplex: Two-way, and at the same time, e.g.

telephoneSpeed measure in bps (bits per second) not Bps

(bytes per second)Dial-up is slow at around 56 kbpsBroadband is faster – currently up to around 10 mbpsWiFi is wireless broadband but fairly short rangeWiMax is higher bandwidth and longer range

wirelessNice article here: Wikipedia – Internet Access

Data transmission

Page 41: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Asymmetric Digital Subscriber LineAsymmetric because you can download much faster than you

can uploadCarried over a normal telephone line but at such high

frequencies that it is separable from voiceHence ADSL can be used at the same time as voice, unlike a

dial-up connect, which hogs the line It uses the POTS (Plain Old Telephone System) to carry a

digital signal, unlike an dial-up modem, which is analogueSo it's a myth that the telephone system is analogue – it can

carry analogue (voice) and digital (data) at the same time, just like the TV signal, which used to be analogue and is now digital

Analogue signals are created by smoothly varying voltages; digital signals are created by abrupt step-changes in voltage. Same medium, different signals.

ADSL

Page 42: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Packet switched communicationData broken into small packets (e.g. 64kb

maximum for IP) Packets may take totally different routes to

their destinationPackets reassembled and sequenced at

destination into coherent dataExample: InternetCircuit switched communicationDedicated channel established between both

partiesData sent in one go, in order, and received

likewise

Packet Switching vs Circuit Switching

Page 43: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Full use of available bandwidth. In a telephone call (circuit switched) even if both parties are saying nothing, the channel is still established and nobody else can use the available bandwidth. With packet switching, the instant my data has been sent, the bandwidth is free to be used by other parties. (Imagine chatting on Facebook: It may seem like messages are going backwards and forwards constantly, but in fact your computer is spending 99.9% of its time waiting for you to finish typing, and only 0.1% of it's time actually sending your messages.)

More secure, because it's difficult to intercept packets that are taking different routes across the network.

Devices of different speeds can communicate easily. In circuit-switched networks both parties have to agree to communicate at the speed of the slower party.

Resilient to communications hardware failure. If one channel goes down, packets will just take a different route. In circuit-switched networks, loss of a channel can mean no communication is possible at all.

Nice link here.

Advantages of Packet Switching

Page 44: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Protocol: An internationally agreed set of rules to ensure transfer of data between devices. A standard protocol is one that is recognized as the standard for a specific type of transfer.

Data is just a huge sequence of 1's and 0's – a protocol is an agreed way of deciding what it all means

For example, the first 32 bits might encode the address of the sender, the next 32 bits encode the address of the receiver, etc

Examples are:HTTP (Hypertext Transfer Protocol): for sending and

receiving web pagesTCP (Transmission Control Protocol): for making sure that

data packets get received and sequenced properly IP (Internet Protocol): for making sure that data sent across

a network gets to the right host (computer)

Protocols

Page 45: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

ASCII is an example of an extremely simple protocolBits are interpreted in groups of 8 and each group

corresponds to a character, e.g. 01000001 = “A” and 00111111 = “?”

A protocol error occurs when the receiver interprets data using the wrong protocol and ends up with total nonsense

You are now ready to cause your own protocol error:Open up Windows notepadChoose File, Open (select All Files)Open up an image file (gif, jpeg, png, etc)

Notepad will dutifully interpret the file as text, and you will end up with meaningless junk

This is essentially a protocol error

Causing a Protocol Error

Page 46: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Structure of an IP Packet

Page 47: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Handshaking (IB definition): The exchange of predetermined signals when a connection is established between two devices or components.

The process of by which two devices on a network agree upon which protocol they are going to use for their communication.

A good example is dial-up modems, which have to decide what rate data will be sent at, what checks will be done, etc. Have you ever heard the “squealing” an acoustic modem makes when it first connects? That is in fact the handshaking procedure.

Handshaking

Page 48: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Usernames identify, passwords authenticateOther authentication methods: fingerprints,

retinal scanAccess control: read, write, delete, etc –

different user types with different privilegesAntivirusBack-upFirewallPhysical measures, e.g. walls, doors, locks

Network Security

Page 49: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Communication with Peripherals

Section 6.5

Page 50: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Peripheral device: Any device that can communicate with a particular computer, for example: modems, hard drives, printers.

The issue with hardware peripherals is this: How does the peripheral get the CPU's attention when it's done what it's supposed to have done? There are three answers:(Hardware) InterruptPollingDMA (Direct Memory Access)

Issues with Peripherals

Page 51: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Hardware is slow. Let's look at the example of a printer. Assume, it takes 15 seconds to print your document. Once you press print, the CPU has two options:• Stop working till the print job finishes

(known as "busy waiting")• Do something else in the mean time

For a process that takes 15 seconds, it is clearly better for the CPU to do something else in the mean time. But how does it know when the print job is finished?

There are two ways it can find out: hardware interrupts or polling.

Hardware Interrupts and Polling

Page 52: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

An interrupt is a signal that stops the CPU and forces it to do something else immediately. The interrupt does this without waiting for the current program to finish. It is unconditional and immediate which is why it is called an interrupt. The whole point of a interrupt is that the main program can perform a task without worrying about an external event.

Programs cause these interrupts constantly. These are called software interrupts.

Some hardware can interrupt the CPU in this way. This is called a hardware interrupt.

Hardware Interrupts

Page 53: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

If the piece of hardware cannot interrupt the CPU, then the CPU has to keep checking with the hardware, to see if it is finished.

Polling

Page 54: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Interrupts save CPU time because the CPU doesn’t have to

keep checking. But too many interrupts can slow the CPU down.

Polling is easy to implement because the hardware doesn’t

need to be able to do anything special. Polling gives the CPU more control over what does. Polling wastes CPU time.

Verdict: Almost all hardware devices use interrupts where possible.

Interrupts vs Polling

Page 55: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Think of a normal household telephone.Think of what happens when someone

calls.How do you find out that someone wants

to talk?Is this analogous to an interrupt or

polling?Once you have decided which strategy

this is analogous to, interrupt or polling, describe what a telephone would be like if it used the other strategy.

Task

Page 56: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Past paper questionMay 2007 HL Paper 1

Page 57: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Because sending and receiving data to and from hardware peripherals is slow, the CPU often has to waste its time either: polling the device to see if it wants to read from or write to RAM being interrupted by device whenever it wants to read from or

write to RAMA recent development, DMA, allows the hardware device to

bypass the CPU and access RAM directly, to save or retrieve the data it needs

Instead of the CPU having to be involved in the exchange of data, a DMA Controller (a bit like a mini-CPU dedicated to the task) coordinates the exchange

This frees up the CPU (An interrupt will still be used to notify the CPU that the

peripheral has finished its task, but no interrupts will have been necessary during data transfer.)

The third way: Direct Memory Access

Page 58: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

CPUs can process data much faster than hardware devices can

Imagine having a conversation with someone who only says one word per minute, and who can only listen to what you're saying if you say it at the same slow speed

Very quickly you will find that you are spending the vast majority of your time sitting waiting

You might decide it's easier if she writes down her message, on a piece of paper, very slowly, while you go off and do something else. You can then come back later, quickly read the message, quickly write a reply and then go off and do something else again, while she takes ages reading it and writing her reply

This is precisely what happens when the CPU talks to a hardware device….

Data transfer between the CPU and hardware devices

Page 59: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Data Transfer: Serial vs ParallelSerial port. Data flows one bit at a time. One pin for incoming data, one pin for outgoing data. Therefore full duplex. Most interfaces are now serial. Example: USB.

Parallel port. Data flows eight bits at a time. Eight pins for incoming and outgoing data. Therefore half duplex. It sounds like more data can be sent faster in parallel, but in fact the extra control required means it is now almost obsolete.

Page 60: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Serial Data flows one bit at a time Slower than parallel Full duplex Simple to implement Used to be used for mouse

and keyboard connections (PS/2)

Next generation has become USB

Data flows eight bits at a time

Faster than parallel Half duplex Difficult to implement

because of the large number of separate lines that need to run between devices

Still used in some hard drives (parallel ATA) and older printers

Serial vs ParallelParallel

In fact, USB has superseded both parallel and the old-style serial ports. USB (universal serial bus) aims to provide a simple serial interface. While its true that serial data transmission is slow, peripheral devices are normally much slower, and so serial transmission is perfectly adequate.

Page 61: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Past Paper Questions

Page 62: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

Nov 2011, May 2011

Page 63: Further System Fundamentals. Diagram of CPU including control unit, ALU, address bus and memory (RAM) Machine instruction cycle: fetch, decode, execute

May 2011

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May 2010