freescale powerpoint template - 恩智浦半导体 · pdf filefreescale, the freescale logo,...

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. © 2011 Freescale Semiconductor, Inc.

Rajeev Kumar

i.MX Product Line Manager

August 2011

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore

and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a

Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.

2

Weibo? Please use hashtag

#FTF2011#

Freescale on KaixinTag yourself in photos

and upload your own!

• i.MX 6 overview

• Core subsystem (Single, Dual, Quad)

• Triple Play Graphics subsystem

• Video, Display, Memory

• IO overview, Boot modes, Packaging

• Power Management

• SW, Development Platforms, Documentation

TM





3

• Power & Performance Leadership

− 1st Quad A9 + 64b memory, 1st Cortex CPU + integrated EPD

− Multi-core CPU, multi-core graphics, multi-stream video, console class 3D, rich interfaces

− i.MX53: 400mW SOC for 1080p, H.264 HP, XGA screen

• Smooth Scalability

− Quad, Dual and Single core CPU offerings

− Best in class flexibility/integration: Consumer, Auto, Industrial IO‘s + qualifications + BGA/POP offerings

GbE, PCIe, SATA, MIPI, USB, HDMI, LVDS, EPD, etc

Full PMIC integration (lower complexity & BOM)

LP-DDR2 / DDR3 (cost versus power options)

− Single SW investment, multiple devices in market

− Pin compatibility

• Trusted Technology

− Up to 15 year life cycle support

− Auto grade quality design practices

− Fully featured, market targeted reference designs

− Android, Microsoft, QNX, Linux, Ubuntu optimizations

Display centric devices are the fastest growing segment of the market

Freescale Target Markets

Over 150 million

processors shipped

Top 3 AP silicon vendor

MedicalSmartphones,

Smartbooks

& Tablets

Industrial

Automotive

eReaders

Connected

Displays





4TM

Multiple Markets;

Embedded

Leadership

Scalable

Platforms

Targeted

SWEase of Use

Secure

Solutions

Trusted

Partner

Competitors

Freescale

fast boot

SW/Pin

Compatibility

Ref Soln

Out of the

Box

Experience

Docs

PMIC

Channel

Partner

Program

Longevity

Support

$

BOM

http://http/www.cloudtweaks.com/http:/www.cloudtweaks.com/web/content/security-icon-big.gif

http://www.google.com/imgres?imgurl=http://www.top-maschinen.de/media/cd-software-symbol.jpg&imgrefurl=http://www.top-maschinen.de/werkzeugmaschinen/cnc-werkzeugmaschinen/cnc-software/cnc-software-ncdrive-meganc/index.htm&usg=__ft0OObxEWFQaRZNIPb7UObc2Hco=&h=199&w=200&sz=13&hl=en&start=8&zoom=1&um=1&itbs=1&tbnid=Vok3hTDoBuRWAM:&tbnh=103&tbnw=104&prev=/search?q=Software+symbol&um=1&hl=en&rlz=1T4ADFA_enUS427US428&tbm=isch&ei=pKEpTrHHHMjcgQeZ2dipCw

http://www.google.com/imgres?imgurl=http://www.mentor.com/embedded-software/multimedia/inflexionui-freescale/thumbnail/inflexion-freescale-sm.jpg&imgrefurl=http://www.mentor.com/embedded-software/resources/overview/fantastic-user-experience-on-set-top-box-with-inflexion-ui-7ea5715f-1592-42ba-b3db-4eaba10e76a8&usg=__3hmLwbSeRhUXsq9UpLxwEQAxYvs=&h=83&w=110&sz=5&hl=en&start=11&zoom=1&um=1&itbs=1&tbnid=7l88W2PJLOqcJM:&tbnh=64&tbnw=85&prev=/search?q=Freescale+Out+of+Box+experience&um=1&hl=en&rlz=1T4ADFA_enUS427US428&tbm=isch&ei=dxImTrj2H-L20gGnq5DyCg

http://www.genivi.org/

http://www.google.com/imgres?imgurl=http://www.futureelectronics.com/EN/TECHNOLOGIES/DEVELOPMENT-TOOLS/MICROCONTROLLER-MICROPROCESSOR/MULTIMEDIA/PUBLISHINGIMAGES/MCIMX53SMD - FSL - N/MCIMX53SMD-FSL-FNT-LRG.JPG&imgrefurl=http://www.futureelectronics.com/en/technologies/development-tools/microcontroller-microprocessor/multimedia/Pages/4005552-MCIMX53SMD.aspx&usg=__pG8prKpL-Fq26acAV-PO4iVYsgI=&h=400&w=441&sz=32&hl=en&start=2&zoom=1&um=1&itbs=1&tbnid=CAQhvfMtc8OoVM:&tbnh=115&tbnw=127&prev=/search?q=FSL+SABER+platform&um=1&hl=en&rlz=1T4ADFA_enUS427US428&tbm=isch&ei=1cguTtvNFoLHgAfOyNCwAQ

http://www.freescale.com/webapp/sps/site/overview.jsp?code=IMX6X_SERIES

http://www.google.com/imgres?imgurl=http://www.entrepreneurs-journey.com/images/articles/customer-service/smiling-support.jpg&imgrefurl=http://www.entrepreneurs-journey.com/934/how-to-find-a-good-customer-support/&usg=__xutlA1pRmpP_SalKHJoY4vTxB8M=&h=231&w=348&sz=15&hl=en&start=20&zoom=1&um=1&itbs=1&tbnid=6QV40Vs9lz1c1M:&tbnh=80&tbnw=120&prev=/images?q=customer+support&um=1&hl=en&rlz=1T4ADFA_enUS427US428&biw=1280&bih=550&tbm=isch&ei=4A4mTt39NePz0gGPtr3ACg

http://www.google.com/imgres?imgurl=http://cmcm.uni-kl.de/uploads/pics/Wafer_2_Zoll_bis_8_Zoll_01.jpg&imgrefurl=http://cmcm.uni-kl.de/en/research/system-on-chip-design/versys/&h=557&w=454&sz=84&tbnid=hFPmyupO_PJ1JM:&tbnh=133&tbnw=108&prev=/search?q=wafer&tbm=isch&tbo=u&zoom=1&q=wafer&usg=__2TlDC-5q9srclP9ni2N7yVW6ZrY=&sa=X&ei=dREmTpiYH8bn0QHvpvmuCg&ved=0CEEQ9QEwBg

http://images.google.com/imgres?imgurl=http://www.generation-nt.com/images/biblio/misc/000000012129.jpg&imgrefurl=http://www.generation-nt.com/actualites/17645/microsoft-windows-vista-xp-beta-test/&h=199&w=200&sz=7&hl=en&start=9&tbnid=OaNDty926qG8wM:&tbnh=103&tbnw=104&prev=/images?q=microsoft+ce+logo&svnum=10&hl=en&lr=&sa=N

http://johndayautomotivelectronics.com/wp-content/uploads/2010/11/QNXCorpLogo.gif

TM





5

• Clear market leader for eReader apps processors (IDC)

• No. 2 in Auto Infotainment (Strategy Analytics)

• No. 3 in Mobile Apps Processors (Linley 5/2011)

1995 2001 2003 2005 2009 2011

Dragonball 1st FSL Apps

Processor

i.MX3 SeriesARM11

GPU Integration

i.MX11st FSL ARM9

Apps Processor

i.MX2 Series90 nm LP

HW Video Accel

Analog Integration

i.MX5 Series65 nm LP/GP

ARM Cortex-A8

>1GHz

i.MX 6 Series 40 nm LP

ARM Cortex-A9

Multi-core family

50+ Products

>150M Units

TM





6

TM





7

i.MX 6Quad

i.MX53

i.MX 6Dual

i.MX51, i.MX50

i.MX 6Solo

i.MX28, i.MX233,

i.MX25, i.MX27,

i.MX31, i.MX35

Advanced

HMI

Luxury

Infotainment

NetbookMedia

Tablet

MedicalMainstream

Infotainment

Business

Tablet

Color

eReader

Smart

Energy

Meter

Connected

Radio

Single

Function

Tablet

Monochrome

eReader

Perf

orm

an

ce/ M

ult

imed

ia C

ap

ab

ilit

y

Co

nte

nt

Cre

ati

on

, Tech

no

log

y D

rive

r

Go

od

, B

ett

er,

Best

Dif

fere

nti

ati

on

NEW

NEW

NEW

http://www.pocket-lint.com/news-gallery/30781/audi-a8-2011-nvidia-tegra/1

TM





8

Industry‘s most scalable family of

multimedia applications processors

Easily build scalable product lines with the

i.MX 6 series—ultimate versatility with

compatible single, dual and quad core

devices

Best-in-Class Performance enabled by quad core

processing, low power consumption and bleeding-edge

multimedia and graphics

Optimized peripheral sets tailored to serve auto,

industrial and consumer markets

Fast development through simplified hardware design,

flexible interfaces and easy-to-use development kits





9TM

Breaking the Boundaries of User Experience

Freescale: The most powerful ARM yet?By Steve BushJanuary 5, 2011

Applications Processors

Scale From One to Four

CoresJanuary 6, 2011

The i.MX 6Quad is ideal for

netbooks and high end

tablets, offering more total

CPU performance than

any other application

processor, even Intel’s

Atom processors.- Linley Gwennap

Freescale ups ante for

tablets, phones with

quad-core i.MX 6January 3, 2011

Power. We need more. More for

streaming video, more for playing

games, and more just so that we

can say we have it. Freescale

hears us, and it's delivering ….By Darren Murph

February 4, 2011.

―With the i.MX 6 series,

Freescale offers the broadest

and highest performance

family of products …‖-Jim McGregor, chief technology

strategist at In-Stat.

Freescale Boosts Share

Of Tablet Processor

MarketBy Esther Shein

December 10, 2010





10TM

i.MX 6Soloi.MX 6Dual

i.MX 6Quad

• Dual ARM Cortex A9, 1/1.2GHz

• 1 MB L2 cache, Neon, VFPv3,

Trustzone

• 3D graphics with 4 shaders up to

200MT/s

• Dual stream 1080p/720p dec/enc

• External memory support up to 64-

bit DDR3 and 2-channel 32-bit

LPDDR2

• Integrated SATA-II

• Single ARM Cortex A9, 1 GHz

• 512KB L2 cache, Neon, VFPv3,

Trustzone

• Next generation video, 3D graphics

(6Solo only)

• External memory support up to

32bit DDR3 and LPDDR2

• Integrated EPD controller

• Quad ARM Cortex A9. 1/1.2GHz

• 1 MB L2 cache, Neon, VFPv3,

Trustzone

• 3D graphics with 4 shaders up to

200MT/s

• Dual stream 1080p/720p dec/enc

• External memory support up to 64-

bit DDR3 and 2-channel 32-bit

LPDDR2

• Integrated SATA-II

• ARM Cortex A9 based solutions up to 1.2GHz

• Dual HD 1080p decode, Dual 720p encode, single stream up to 1080p60, 50Mb/s

• 3D video playback in High definition

• Low power 1080p playback at 350mW Integrated IO‘s that include HDMI v1.4 w/PHY, LVDS display ports, MIPI CSI/DSI

for camera/Display, MIPI HSI, Gigabit Ethernet, multiple USB 2.0, PCI-Express, CAN controller, MLB bus

• Consumer, Industrial and Automotive temperature range qualifications

• POP, BGA packaging options using low layer count PCB design rules

• SW support: Google Android, Microsoft Windows Embedded CE, Ubuntu, QNX, Linux, Linaro, Adobe Flash, Skype

Common Features of the i.MX 6 Series Platform

TM





11

• Development under way on new PFUZE PMIC

family

− First product family using new Modular Development

Strategy (MDS)

• Family of products supports entire i.MX6x family

− Quad core

− Dual core

− Solo

• Various integration levels target different

applications

− PFUZE100: Embedded/ auto-infotainment

− PFUZE101: Single-cell applications

− PFUZE201: Solo low-cost single-cell applications

• PFUZE100 will be available in two versions:

− MCxxxxx – Consumer and Industrial applications (-40C to +85C)

− MCxxxxxA – Automotive Grade 3 applications (-40C to +85C)

TM





12

Mag PressureCap

Touch

Other Sensor Peripherals

MMA

9550

1

2

3

4

5

13

12

11

10

96 7 8

16 15 14

Up to 2MBps (Slave)

Up to 400KBps (Master)

Benefits:

Save System Power –

• Local control and power management of multiple

sensors

Save System Processing –

• Preprocessing of multiple sensor inputs

• Fusion of multiple sensors into higher level data

Algorithm Abstraction –

• Remove sensor specific algorithms from application

software build

Applications

processor

MMA9550:

• 32-bit CPU + 3-axis accelerometer

• Optimized Architecture for sensors

• 14-bit ADC

• SPI, I2C (2)

• 3x3x1mm LGA Package

2 optional

interruptsApplicationsProcessor

Drivers





13TM

Compass

Gyro

Accelerometer

Multi-Format

Radio

RF

RF

GPS Bluetooth®

i.MX 6

Applications

Processor

1.2Ghz

Dual 1080p Video

Triple Play Graphics

0.8mm BGA or 0.4mm POP

Audio

CODEC

WiFi

Sensors

LVDS

Dual MIC

SpeakersSDIO

UART

UART

USB ULPI

PFUZE100

Platform

Power

Management

IC

3G

Modem(if needed)

Flash

Memory

Dual LP-

DDR2 or

Dual DDR3

DRAMup to 2GB

SSI

ESAI

l2C

MIP

I

CS

Il2

CH

DM

I

SA

TA

SD

IO

US

B

SP

,

HS

I I

I2S 3D (Dual) Camera

Dual

Displays

Device Storage

and ConnectivityWireless

charging/docking

station

Watt Saver

AC adapterMCU

MCU

ZigBee RF4CE Home Wireless

l2C

Cap

Touch

Sensors





14TM

• Specifications

− CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS

− i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS

− Process: 40nm

− Core Voltage: 1.1V

− Package: 21x21 0.8mm Flip-chip BGA

− 12x12 PoP (LP-DDR2, NAND)

• Key Features and Advantages

− Multi-core architecture for high performance, 1MB L2 cache

− 64-bit LP-DDR2, DDR3 and raw / managed NAND

− S-ATA 3Gbps interface (SSD / HDD)

− Delivers rich graphics and UI in HW

OpenGL/ES 2.x 3D accelerator with OpenCL EP support

and OpenVG 1.1 acceleration

− Drives high resolution video in HW

Multi-format HD1080 video decode and encode

1080p60 decode, 720p60 encode

High quality video processing (resizing, de-interlacing, etc.)

− Flexible display support

Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI

Dual display up to WUXGA (1920x1200) and HD1080

− MIPI-CSI2 and HSI

− Increased analog integration simplifies system design and reduces

BOM

DC-DC converters and linear regulators supply cores

and all internal logic

Temperature monitor for smart performance control

− Expansion port support via PCIe 2.0

− Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with

IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control

Dual / Quad Cortex-A9

Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM

Graphics: OpenGL/ES 2.x,

OpenCL/EP, OpenVG 1.x

Smart DMA

1MB L2-cache + VFPv3

Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC

32KB I-cacheper core

32KB D-cacheper core

Video Codecs: 1080p30

Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO

USB2 OTG & PHYUSB2 Host & PHY

MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2

S-ATA & PHY 3GbpsPower Mgmt

Power Supplies

FlexCAN x2MLB150 + DTCP

eFuses

Ciphers

20-bit CSI

HDMI & PHY

MIPI DSI

LCD & Camera Interface

24-bit RGB, LVDS (x3-8)

MIPI CSI2

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad

Resizing & Blending

Inversion / Rotation

Image Enhancement

2x Imaging Processing Unit

TM





15

Freescale

PortfolioARM Cortex A5/A9

i.MX6QARM A9 – Quad Core

USB / MLB

i.MX6SARM A9 – Single core

USB / MLB

i.MX6DARM A9 – Dual Core

USB / MLB

High Tier

Mid Tier

Entry Tier

Pin Compatible

Software Compatible

Common IP

Common ARMV7

architecture

Pin

Com

patible





16TM

AXI 64-bit AXI 64-bit

AXI Fabric

AXI 64-bit AXI 64-bit

HW Components:

•System:• 2x/4x Cores in i.MX 6 Dual/Quad

• 32 KB L1 (I and D)

•1MB L2 Cache

•128 Interrupts

•Using 2x 64-bit AXI to L2C

• Per core•32 KB I and 32KB D L1 Cache

•Neon, VPU, Jazelle, Trustzone

L2 Cache Controller (PL310)

Cache-2-Cache

Transfers

Snoop

Filtering

Generalized

Interrupt Control

and Distribution

Snoop Control Unit (SCU)

Timers

Advanced Bus Interface Unit

Optional 2nd I/F with Address FilteringPrimary AMBA 3 64bit Interface

Accelerator

Coherence

Port

FPU/NEON

Cortex-A9 CPU

Instruction

Cache

Data

Cache

PTM

I/FFPU/NEON

Cortex-A9 CPU

Instruction

Cache

Data

Cache

PTM

I/FFPU/NEON

Cortex-A9 CPU

Instruction

Cache

Data

Cache

PTM

I/FFPU/NEON

Cortex-A9 CPU

Instruction

Cache

Data

Cache

PTM

I/F

ARM Coresight Multcore Debug and Trace Architecture





17TM

Game

Image Editing

Playback

Browsing

Productivity

Video Editing

Core1 Core2 Core3 Core4

Bioshock 35% 25% 27% 11%

Call of Duty 4 37% 27% 26% 10%

Crysis 39% 44% 14% 2%

Maya3D 41% 21% 5% 13%

Photoshop 59% 17% 6% 10%

Adobe Reader 36% 19% 5% 1%

Excel 40% 12% 2% 0%

Powerpoint 42% 16% 4% 1%

Streets & Trips 34% 20% 5% 2%

iTunes 9 45% 24% 6% 1%

Quicktime 7 39% 28% 23% 6%

Quicktime HD 26% 22% 22% 19%

Handbrake .9 88% 2% 10% 0%

Powerdrive v8 58% 19% 11% 8%

Firefox 3.5 42% 19% 9% 5%

Safari 4.0 35% 21% 12% 8%

% Utilization of 1.6GHz Quad

Processor*

The Bad News: Even 5 years after launch, Dual and Quad Core Desktop Processors are not fully utilized by popular desktop software applications. Software has not kept up with hardware

But: How consumers use Desktop/laptops is fundamentally different than mobile/auto.

So does Multicore make sense for mobile?

* Evolution of Thread-Level Parallelism in Desktop Applications, Blake, 2010





18TM

The Great News: i.MX 6Quad enables a richer experience across the board.Four cores means more services, richer ‗standard apps‘, faster response times,and headroom to expand and grow as the market evolves

Cortex A9 (1) Cortex A9 (2) Cortex A9 (3) Cortex A9 (4)

1-

2-

3-

4-

Richer ‘Standard’ Apps

+

+

+

+

+5- +

Full suite of Enhanced

Mobile Services





19TM

i.MX 6Quadi.MX 6Dual

Rich Game

VOIP

Power

1

.64P (vs Single)

1

P

1

.82P (v dual)

.44P (v single)

Playing rich3D game

andVOIP over

HDMIwith Rich

Web Browser on main screen

(requires 2GHz)

18 to 56% Lower Power

Hypothetical

Processor

Same Performance

2.4Ghz

Single A92.4Ghz

Dual A9

4.8Ghz

Quad A9

Single core must

double frequency

to do use case

Assumption Power impact Note

Frequency 2000 500 P .25P F linear scaling

2 vs 4 Cores 2 Core 4Cores 4* 0.25P 1P Quad Cores

Voltage 1.2Volt 1.0Volt .82@ P .82P V2 scaling factor


1 vs 4 Cores 1 Core 4Cores 4* 0.25P 1P Quad Cores

Voltage 1.5Volt 1.0Volt .44@ 1P .44P V2 scaling factor


1 vs 2Cores 1 Core 2 Core 2* .5P 1P Dual Cores

Voltage 1.5Volt 1.2Volt .64@ 1P .64P V2 scaling factor

36% Lower Power

Hypothetical single

core processor

at 2.4Ghz





20TM

• Actual results from processor X

− Goal: determine the correct CPU package size and the type of heat spreader (graphite or heatsink) to maximize power envelope of the processor without overheating the entire platform

− Results: recommended 5 cent graphite headspreader instead of $1.50 heat sink

• Assumptions:

− System Size: 127.6 x 78.4 x 15.7

− Outside ambient temperature at 40 C

− Processor usage power 2W continuous

− Processor is the only power source in the system

− System PCB is a 6 layer 1.2 mm thickness

CPU package size 2.19mm HFCBGA 1.7mm HFCBGA 1.7mm

FCBGA

1.2mm

FCBGA

1.2mm

TFBGA

Max pkg power without

heatsink (goal 2Watts)

2.3W 2.3W 1.8W 1.8W 1.7W

Max pkg power with graphite

heat spreader

5 cents (US) cost adder

4.6W 4.6W 3.6W 3.6W 3.4W

Max pkg power with heatsink

$1.50 (US) cost adder

5.5W 5.5W 4.5W 4.5W 4.2W

LCD

Board

127.65 mm 78.4

mm1

5.7

mm

MMP2Processor





21TM

0

2000

4000

6000

8000

10000

12000

14000

16000

2 2.5 3 3.5 4 4.5 5

Ma

x A

va

ila

ble

DM

IPs

CPU thermal budget, W

A9

A15

• Max Performance Comparison (Dual A15 and Quad A9)

− Assumes LVT cells used for A15 at 2Ghz vs 1.2Ghz Quad A9

− Assumes Tjunction temp of 125Deg C

− Equivalent to sustained performance of Cores running flat out

• Dual A15 @ 2Ghz outputs ~ 3.25Watts vs ~2.5W for Quad A9 at same max DMIPS

• Dual A15 @ 1.2Ghz will never provide equivalent performance of Quad A9

Dual A15 @ 2Ghz requires

3.2 Watts thermal budget

to equal 4 A9s @ 1.2Ghz

Better than A9

Better

than

A15

Dual Cortex A15’s

require ~1W more

to reach same

performance as

Quad Cortex A9’s

Using case study from previous example:• Up to ~1.7W with no heat

sink• Up to ~3.4W with graphite

heat spreader($0.05)• Up to ~4.2W with heat sink

($1.50)





22TM

Rich web site (100-250 Mhz)

–300+ Kb/s, Animated UI’s,

–Embedded media

Mobile ‘tabbed’ web (250-500Mhz+)

–5Mbit/s, 5+ rich websites open

–Frequent updates

Web Browsingover WIFI

i.MX 6Quad Dual A15Desktop class

(10 Mb/s)Desktop class

(10 Mb/s)

1. Incoming Web traffic 1 MB/s 1 MB/s

2. Display Frame buffer sent to LCD 93 MB/s 93 MB/s

3. OS Traffic, Audio, etc. 900 MB/s 900 MB/s

Total bandwidth Consumed 994 MB/s 994 MB/s

Raw available Bandwidth 8528 MB/s 8528 MB/s

Available Bandwidth (70% utilization) 5970 MB/s 5970 MB/s

% Available Bandwidth consumed 16% 16%

Apps Processor: Current + Leakage (125 Deg Tjunction)

540mA(740mW) 900mA (2100mW)

Main Memory 45 mA (164mW) 45 mA (164mW)

WIFI 45mA (162mW) 45mA (162mW)

PMIC 1.88 (6.8mW) 1.88 (6.8mW)

Display 47 mA (171mW) 47 mA (171mW)

Audio codec 1.4mA (5mW) 1.4mA (5mW)

Total Battery Power: (System) 680mA ( 1248mW) 1040mA (2608mW)

Battery life (6400mAh) 9.4 hrs 6 hrs

Subnote class browsing (1.7 Ghz)

–10 Mb/s, 5 rich sites open

–Lots of ‘always on’ content

Desktop class browsing (2.4Ghz)

–10 Mb/s, 5 rich sites open

–Lots of ‘always on’ content

Quad A9 @ 600Mhz/core provides 3.4 hours more

browsing time at >50% lower total current/power than

Dual A15 @ 800Mhz per core

(note assumes high DMIPS/Mhz of A15)





23TM

• Specifications


− i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000

DMIPS

− Process: 40nm



















− Increased analog integration simplifies system design and

reduces BOM






IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control


Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM



Smart DMA


Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC




Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO


MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2


Power Supplies


eFuses

Ciphers

20-bit CSI

HDMI & PHY

MIPI DSI



MIPI CSI2

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad

Resizing & Blending


Image Enhancement


TM





24

• Diverse markets and applications call for multiple GPUs:

• Accelerate existing windowing environments (Android™, X11, etc.) and base user interfaces with a low-power high-performance composition engine

• Providing compelling vector capabilities for high-quality fonts and automotive clusters in a manner that assures quality of service in performance

• Accelerate next-generation 3D and GPGPU applications with a feature-rich high-performing unified graphics processor

GC320

GC2000

GC355





25TM

Rig

htw

are

GP

U B

en

ch

mark

s

GL benchmark GPU Benchmarks

Leading 40 nm Application Processors

i.MX 6GC2000





26TM

“Vivante’s anti-aliased rendering of the complex shaders in the BaseMark ES 2.0 Hover test is

the best we have seen to date. I immediately asked for a video we can place on our web site”

- Teemu Uotila, Manager at RightWare

Smoke particle system

produces realistic plums

which must be present

Blinn-Phong shader

produces realistic colors

calculated from the

surrounding environment

Vivante applies multi-

sampling anti-aliasing by

rendering into larger textures

for ultra-high image quality

Hover 15-1110





27TM

Command System

ShaderProcessor

Core

TextureSystem& Cache

SystemInterface

VertexHandling

& Interpolation

PixelBackend

AXI

SystemInterface

Vector GraphicsPipeline M

MU

PixelBackend

TextureSystem& Cache

AXI

ShaderProcessor

Core

ShaderProcessor

Core

ShaderProcessor

Core

AHB

Command System

AHB

Texture+ Gradient

Unit& Cache

PixelBackend

AXI

SystemInterface

2D BLITEngine

MM

UCommand System

AHB

Texture& Cache

PixelBackend

AXI

Texture& Cache

PixelBackend

CompositionEngine

AXI

MM

UTessellation

Engine

GC2000

GC355

GC320





28TM

Benchmarks1024x768

iPad 1SGX535

(A4 - 40nm) (fps)

GC860(55nm)

(fps)

GC860vs

iPad 1

iPad 2SGX543MP2(A5 - 40nm)

(fps)

GC2000(40nm)

(fps)

GC2000vs

iPad 2

3DMark ES 2.0

Taiji Girl 3.25 11.29 3.70X 23.34 51.15 2.19X

Hoverjet 1.93 6.92 3.59X 15.5 32.67 2.11X

GLBench 2.0

Egypt 5.05 16.81 3.33X 42.26 76.6 1.80X

PRO 17.4 35.52 2.04X 57.58 98.42 1.71X

Apple A5

Application

Processor

GPU Area

(2X area GC2000)

SGX543

MP2

GC2000

GC2000

Power Controlled

Ultra-threaded

Architecture

Lower intrinsic power

from smaller gate

count





29TM

• Specifications− CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS


− Process: 40nm




• Key Features and Advantages− Multi-core architecture for high performance, 1MB L2 cache




OpenGL/ES 2.x 3D accelerator with OpenCL EP support and OpenVG 1.1 acceleration









− Increased analog integration simplifies system design and reduces BOM

DC-DC converters and linear regulators supply cores and all internal logic



− Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control


Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM



Smart DMA


Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC



Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO


MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2


Power Supplies


eFuses

Ciphers

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad


20-bit CSI

HDMI & PHY

MIPI DSI



MIPI CSI2

Resizing & Blending


Image Enhancement






30TM

• Embeds a flexible, powerful and low power hardware acceleration for HD video decoding in Blu-ray disk quality

• Note: in all cases, the HW CODEC meets or exceeds the bit-rate requirements specified in the standards

Feature Format Profile i.MX53 i.MX6 Series

Low-Power Audio Decode SW SW

Low-Power Video

Decode

MPEG-2 Main-High HW HW

H.264 BP/MP/HP HW HW

VC1 SP/MP/AP HW HW

RV10 8/9/10 HW HW

MPEG4/Xvid SP/ASP HW HW

DivX 3/4/5/6 HW HW

H.263 P0/P3 HW HW

Sorenson H.263 N/A HW HW

AVS Jizhun SW HW

On2 VP6/8 N/A SW HW

SVC HP SW HW/SW

MVC N/A SW/HW HW

MJPEG Baseline HW, 40MP/sec HW, 120MP/sec

Low-Power Video

Encode

H.264 Baseline HW HW* + 720p60

H.263 P0/P3 HW HW

MPEG4 Simple HW HW

MJPEG Baseline HW, 80MP/sec HW, 160MP/sec

Video Telephony (SiP, H323) – H.264 BP HW HW

Transcode (DLNA) – (M)DMS/(M)DMP HW HW

Video de-interlacing HW HW

Further Video Processing (deblocking, resizing, CSC) HW HW

1080p60

1080i/p30 (* - p only)

720p30 or 720p60

720p20

WVGA

D1 (PAL/NTSC)

TM





31

11 to 24 hours of HD playback

• 1080p30 fps or 720p60 fps h.264 High Profile

• Single Stream at 50Mbps

• 350mW decode power

7 to 15 hours of 3D video playback

• 1080p60 h.264 MVC

• Dual stream at 25Mbps each


8 hours of 3D video encode

• 720p60 h.264 MVC

• Dual stream at 25Mbps each


12 hours of 1080p video encode

• 1080p30fps H.264

• Single stream at 20Mbps

• 300mW encode power

i.MX 6Dual/ 6Quad

TM





32

• Functions: comprehensive support for the flow of data from

an image sensor and/or to a display device.

− Connectivity to relevant devices

− Related image processing and manipulation

− Synchronization and control capabilities

Memory

Interface

Sync &

Control

Camera

Interface

Display

Interface

Memory

IPU

Video

Sources

Displays

Op

tio

na

l In

teg

rate

d I

/F B

rid

ge

s

MCU

Processing

Including

Image

Enhancements

And

Conversions

GPU

TM





33

• Combining methods (in both cases)

− Color keying and/or alpha blending

− Alpha: global or per-pixel; interleaved with the pixels (upper plane) or as a separate input

External

Memory

ICIPUv3

Plane 2

Plane 1

DC

DI DP

DI

Plane 4

Plane 3

Combining in the Display Processor (DP)

Two planes

•One plane may have any size and location

•The other one must be ―full-screen‖ (cover the full output area)

Maximal rate: i.MX37/51 – 133 MP/sec, i.MX53 – 200 MP/sec, i.MX6 Series – 266

MP/sec

Combining in the Image Converter (IC)

Two planes; both ―full-screen‖ (cover the full output area)

Maximal rate: i.MX37/51 – 20 MP/sec , i.MX53 – 30 MP/sec, i.MX6 Series – 40

MP/sec

Note: This is the capability

of each of the two IPUs, so

the total capability of the

processor is doubled.





34TM

Note: Some planes may be a result of additional off-line combining of several planes. Such combining may be

performed either with IPUs or GPUs.

External

Memoryi.MX6 Dual/Quad

IC

IPUv3 - 1

Plane 8 (top)

DCDI DP

Plane 7

VDICPlane 5 (bottom)

Plane 6

External


IC

IPUv3 - 0

Plane 4 (top)

DCDI DP

Plane 3


Plane 2

External


IC

IPUv3 - 1

Plane 7 (top)

DCDI DP

Plane 6

VDICPlane 5

External


IC

IPUv3 - 0

Plane 4

DCDI DP

Plane 3


Plane 2

CSI

Example 1: 2x 4 planes Example 2: 1x 7 planes

External


ICIPUv3 - 1

Plane 7

Plane 8

DC

DI DP

DI

Plane 5 (bottom)

Plane 6

External


ICIPUv3 - 0

Plane 3

Plane 4

DC

DI DP

DI

Plane 1 (bottom)

Plane 2

Example 3: 4x 2 planes





35TM

Graphics

Content 1

NAV

Graphics

Content 2

Graphics

Content 3

Video

Content 1

Decode

Video

Content 2

Front Cam

Video

Content 3

Rear Cam

External

Memory

IPUv3

Frame

BufferDCDIDP VPU

GPU

External

Memory

IPUv3

DCDI

DPFrame

Buffer

ContentComposition

and Blending

Conversion

and output

Display





36TM

• Capabilities− Maximal display resolution: 4096x4096 pixels

− Maximal pixel rate: 266 MP/sec

• Display refresh rate− The maximal refresh rate is: 266M / (W * H * B)

W*H is the display resolution

B is a factor >1 reflecting blanking overhead, e.g. as specified by VESA, CEA-861-D, etc.

− The table provides the maximal refresh rates for some typical resolutions

− Usually, the refresh rate is required to be at least 60 Hz, to prevent blinking.

− The blanking overhead factor assumed for the calculation is 1.3.

The actual factor depends on the display and is often closer to 1, allowing higher resolutions @ 60 Hz (e.g. HD1440).

For example, for HD1080, the standard specifies B~1.2

− This is the capability of each of the two IPUs, so the total capability of the processor is doubled.

Name

Resolution Maximal

Refresh

Rate [Hz]Width x HeightTotal

[MP]

VGA 640 x 480 0.31 666

PAL 720 x 480 0.35 592

WVGA 800 x 480 0.38 533

NTSC 720 x 576 0.41 493

SVGA 800 x 600 0.48 426

WSVGA 1024 x 600 0.61 333

XGA 1024 x 768 0.79 260

HD720 1280 x 720 0.92 222

WXGA 1366 x 768 1.05 195

WXGA+ 1440 x 900 1.30 158

SXGA 1280 x 1024 1.31 156

SXGA+ 1400 x 1050 1.47 139

WSXGA+ 1680 x 1050 1.76 116

UXGA 1600 x 1200 1.92 107

HD1080 1920 x 1080 2.07 99

WUXGA 1920 x 1200 2.30 89

9VGA 1920 x 1440 2.76 74

4XGA 2048 x 1536 3.15 65

HD1440 2560 x 1440 3.69 56

4WXGA 2560 x 1600 4.10 50

4K x 2K 4096 x 2048 8.39 25

800 x 480 (WVGA)

~331 Hz

1280 x 720 (HD720) ~138 Hz

1024 x 768 (XGA) ~161 Hz

1920 x 1080 (HD1080) ~61 Hz

2048 x 1536 (4XGA) ~40 Hz





37TM

This is the capability of each of the two IPUs, so the total capability of the processor is doubled.

− The maximal pixel clock rate supported by the display ports

Each display: 220 MHz; Total: 240 MHz

− For a TV, the clock rate is fixed by the corresponding standards

− For other displays

The assumed screen refresh rate is 60 Hz

The blanking overhead – impacting the pixel clock rate – may vary between displays.The table refers – for concreteness – to the VESA CVT (Coordinated Video Timing) specification

• ―Full support‖: allowing full blanking (which is typically required for CRTs)

• ―Partial support‖: allowing only reduced blanking (which is still typically sufficient for digital displays, e.g. LCDs)

− The above table describes only the capabilities of the display ports to perform screen refresh. A full use case typically includes additional activities and to confirm its support with a given display configuration, additional aspects – video processing capabilities, capacity of the memory system, etc. – should be also analyzed carefully.

Second Display

First Display

SDTV480i30/576i25

(27 MHz)

WSVGA(1024x600)

(44-49 MHz)

HDTV720p60/1080i30

(74.25 MHz)

WXGA(1366x768)

(72-85 MHz)

WSXGA+(1680x1050)

(119-146 MHz)

HDTV1080p60

(148.5 MHz)

WXGA (1366x768 ~ 1.0 MP; 72-85 MHz) Full Full Full Full Full Full

SXGA (1280x1024 ~ 1.3 MP; 91-109 MHz) Full Full Full Full Partial Partial

SXGA+ (1400x1050 ~ 1.5 MP; 101-122 MHz) Full Full Full Full Partial

WSXGA+ (1680x1050 ~ 1.8 MP; 119-146 MHz) Full Full Full Full Partial

UXGA (1600x1200 ~ 1.9 MP; 130-161 MHz) Full Full Full Partial

WUXGA (1920x1200 ~ 2.3 MP; 154-193 MHz) Full Partial Partial

9VGA (1920x1440 ~ 2.8 MP; 185-234 MHz) Partial Partial

4XGA (2048x1536 ~ 3.2 MP; 209-267 MHz) Partial





38TM

• Specifications



− Process: 40nm



















− Increased analog integration simplifies system design and reduces

BOM






IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control


Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM



Smart DMA


Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC




Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO


MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2


Power Supplies


eFuses

Ciphers

20-bit CSI

HDMI & PHY

MIPI DSI



MIPI CSI2

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad

Resizing & Blending


Image Enhancement






39TM

Parameter i.MX6 Dual/Quad

LPDDR2 support Yes

DDR2 support No

DDR3/LVDDR3 support Yes

Bus width 1x32/64 DDR3;

2x32 (Dual channel) LPDDR2

Max memory size ~4GB

Address 16 + 3 (DDR3)

CA DDR bus (LPDDR2)

# of CS 2

Max.frequency 533MHz (1066Mb/s)

ODT Yes

Calibration Yes

• Support of Dynamic Frequency Scaling

• Software transparent, ensuring data integrity

• Self Refresh and Power Down support

• Support Real-Time priority via QoS,

e.g. for screen refresh

• Access Latency hiding

• Bank interleaving, Channel interleaving

• Consecutive read/write access optimizations

• Enabling access priority to open memory pages

• Deep queues for read and write requests

2Gb,

x32

2Gb,

x32CA [9:0], ChA

DQ [31:0] - ChA

CS1# - ChA

CS0# - ChA

2Gb,

x32

2Gb,

x32CA [9:0], ChB

DQ [31:0] - ChB

CS1# - ChB

CS0# - ChB

2Gb,

x16

2Gb,

x16

2Gb,

x16

2Gb,

x16A [15:0], BA [2:0]

DQ [31:0]

CS1#

CS0#

2Gb,

x162Gb,

x16

2Gb,

x16

2Gb,

x16

DQ [63:48] DQ [47:32] DQ [31:16] DQ [15:0]

MMDC: 2xCh 32-bit, 1GB LPDDR2

MMDC: 64-bit, 2GB LV-DDR3 / DDR3





40TM

Dual LPDDR2Single LPDDR2

Smartphone

with WVGA Display(854x480 resolution)

Tablet or Smartphone

with XGA Display (1024x768 resolution)

CapabilityDisplay

Configuration

MB/s1x LPDDR2 2x LPDDR2

200Mhz 400Mhz 533Mhz 400Mhz 533Mhz

max 1600 3200 4264 6400 8528

50% 800 1600 2132 3200 4264

Movie Decode (720p) WVGA LCD output 792

Video Record (720p) WVGA LCD output 918

Take Picture + Video Record

(720p) WVGA LCD output 1166

Movie Playback (1080p) WVGA LCD + output to TV 1194




3D Game (30MT/s) WVGA LCD + output to TV 1031

Movie Decode (720p) WXGA LCD output 1011

Video Record (720p) WXGA LCD output 1731

Take Picture + Video

Record (720p) WXGA LCD output 1881

Movie Playback (1080p) WXGA LCD + output to TV 2098



(1080p) WXGA LCD output 2681

3D Game (30MT/s) WXGA LCD + output to TV 1391

Insufficient

Minimal Headroom





41TM

Dual LPDDR2Single LPDDR2

Smartphone

with WVGA Display(854x480 resolution)

Tablet or Smartphone

with XGA Display (1024x768 resolution)

CapabilityDisplay

Configuration

1x LPDDR2 2x LPDDR2

200Mhz 400Mhz 533Mhz 400Mhz 533Mhz

max 1600 3200 4264 6400 8528

50% 640 1280 1705.6 2560 3411

Movie Decode (720p) WVGA LCD output 792




Movie Playback (1080p) WVGA LCD + output to TV 1194




3D Game (30MT/s) WVGA LCD + output to TV 1031

Movie Decode (720p) WXGA LCD output 1011


Take Picture + Video

Record (720p) WXGA LCD output 1881

Movie Playback (1080p) WXGA LCD + output to TV 2098



(1080p) WXGA LCD output 2681

3D Game (30MT/s) WXGA LCD + output to TV 1391





42TM

• Specifications



− Process: 40nm



















− Increased analog integration simplifies system design and

reduces BOM






IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control


Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM



Smart DMA


Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC




Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO


MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2


Power Supplies


eFuses

Ciphers

20-bit CSI

HDMI & PHY

MIPI DSI



MIPI CSI2

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad

Resizing & Blending


Image Enhancement






43TM

Feature i.MX53 i.MX6Dual/Quad

High Assurance Boot Authenticated Boot (HABv4)Authenticated Boot + Encrypted boot

(HABv4.1)

Secure Storage

On-chip zeroizable 4x4kB Secure RAM

Off-chip storage protected using unique HW

master key (AES-256)

(SCCv2)

On-chip zeroizable 4x4kB Secure RAM

Off-chip storage protected using unique HW

master key (AES-256)

(CAAM/SNVS)

Cryptographic Accelerators

Symmetric: AES-128, DES, 3DES, ARC4

Hash & HMAC: MD5, SHA-1, SHA-224, SHA-

256

HW Random Number Generator

(SAHARA)

Symmetric: AES-128/256, DES, 3DES, ARC4

Hash & HMAC: MD5, SHA-1, SHA-224, SHA-

256

HW Random Number Generator – follows

NIST/BSI recommendations > 2015

(CAAM)

Run-time Monitoring RTIC None

Secure Real Time Clock SRTC SNVS

Hardware FirewallsExternal memory (EMI Watermark)

On-chip peripherals (CSU)

External memory (TZASC)

On-chip peripherals (CSU)

Secure JTAG Full or Controlled Disable (3 modes) Full or Controlled Disable (3 modes)

Physical Tamper DetectionTamper Input GPIO

Tamper Response (SCCv2)

Tamper Input GPIO

Tamper Response (SNVS)

Device Configuration Open, Closed Open, Closed, Field Return

TrustZone Support

Peripheral DMA access control (CSU)

Memory DMA access control (EMI)

Interrupt separation (TZIC)

Secure storage separation (SCCv2)

Cryptographic separation (SAHARA)

Peripheral DMA access control (CSU)

Memory DMA access control (ARM TZASC)

Interrupt separation (ARM GIC)

Secure storage separation (CAAM/SNVS)

Cryptographic separation (CAAM)





44TM

• Specifications

• CPU: i.MX 6Quad 4x Cortex-A9 @1.2 GHz, 12000 DMIPS

• i.MX 6Dual 2x Cortex-A9 @1.2 GHz, 6000 DMIPS

• Process: 40nm

• Core Voltage: 1.1V

• Package: 21x21 0.8mm Flip-chip BGA

• 12x12 PoP (LP-DDR2, NAND)


• Multi-core architecture for high performance, 1MB L2 cache

• 64-bit LP-DDR2, DDR3 and raw / managed NAND

• S-ATA 3Gbps interface (SSD / HDD)

• Delivers rich graphics and UI in HW

• OpenGL/ES 2.x 3D accelerator with OpenCL EP support


• Drives high resolution video in HW

• Multi-format HD1080 video decode and encode

• 1080p60 decode, 720p60 encode

• High quality video processing (resizing, de-interlacing, etc.)

• Flexible display support

• Four simultaneous: 2x Parallel, 2x LVDS, MIPI-DSI, or HDMI

• Dual display up to WUXGA (1920x1200) and HD1080

• MIPI-CSI2 and HSI

• Increased analog integration simplifies system design and reduces

BOM

• DC-DC converters and linear regulators supply cores


• Temperature monitor for smart performance control

• Expansion port support via PCIe 2.0

• Car network: 2xCAN, MLB150 with DTCP, 1Gb Ethernet with

IEEE1588

Multimedia

i.MX 6Quad/6Dual

CPU Platform

System Control


Security

Secure JTAG

PLL, Osc

Clock & Reset

NEONper core

Watch Dog x2

Timer x3

PWM x4

Internal Memory

ROM

RAM



Smart DMA


Updated from i.MX53

RNG

TrustZone

Security Ctrl

Secure RTC




Connectivity

LP-DDR2,

DDR3 / LV-DDR3

x32/64, 533 MHz

MMC 4.4 / SD 3.0 x3

MMC 4.4 / SDXC

UART x5, 5Mbps

I2C x3, SPI x5

ESAI, I2S/SSI x3

3.3V GPIO


MIPI HSI

S/PDIF Tx/Rx

PCIe 2.0 (1-lane)

1Gb Ethernet

+ IEEE1588

NAND Ctrl (BCH40)

USB2 HSIC Host x2


Power Supplies


eFuses

Ciphers

20-bit CSI

HDMI & PHY

MIPI DSI



MIPI CSI2

IOMUX

Temp Monitor

Audio: ASRC

PTMper core

Keypad

Resizing & Blending


Image Enhancement


TM





45

• WEIM (SRAM, NOR, OneNAND):

• 8-/16-bit bus

• Up to 40 bit ECC support – was 16-bit in

i.MX53

• 1.65 … 3.6V supply range

• Boot able

• NAND:

• SATA• SATA 2.5 specification compliant and

AHCI 1.1 compliant Serial ATA Bus Adapter and internal 1 x PHY, up to 3Gbps operations

• Bootable

16-/32-bit A/D multiplexed mode 16-bit A/D demuxed Address up to 27 bit Up to 6 EIM CS (were 4 in iMX53) 1.65 … 3.6V IO supply range Bootable

i.MX6

Dual/Quad

OTG PHY

Host2HS

IC-USB

To OTG

connector

HUB

(USB2524)

x1 PCIe –

System extension port

Host1 PHY

PCIe

Root/Endpoint

PCIe

PHY

To external Memory Card Host2HS

IC-USB

To HDD/SSD SATA

Host

SATA

PHY

to Cellular, WLAN/WiFI/BT

or/and HUB

10/100/1000

Ethernet

IEEE1588

AVB

PHY

NAND

WEIM

SLC/MLC

SRAM, NOR, OneNAND

TM





46

• USB:

OTG – with internal HS/FS/LS PHY,

Host1- with HS/FS/LS PHY,

• Host2 and Host 3 - HS IC-USB (480 Mb/s)

• Ethernet Controller (FEC)

10/100/1000:

− Support SNI, MII, RMII and RGMII interfaces

to an external PHY.

− 1.65V … 3.6V voltage range and automated

selection

− IEEE1588 v2 and Supports Ethernet AVB

• PCIe 2.0

− 1 lane, 5 Gbps with integrated x1 PHY

i.MX6

Dual/Quad

OTG PHY

Host2HS

IC-USB

To OTG

connector

HUB

(USB2524)

x1 PCIe –

System extension port

Host1 PHY

PCIe

Root/Endpoint

PCIe

PHY

To external Memory Card Host2HS

IC-USB

To HDD/SSD SATA

Host

SATA

PHY

to Cellular, WLAN/WiFI/BT

or/and HUB

10/100/1000

Ethernet

IEEE1588

AVB

PHY

NAND

WEIM

SLC/MLC

SRAM, NOR, OneNAND

TM





47

SoC MMCVer/MHz/Vcc/Boot

SDVer/MHz/Vcc/Boot

SDXC (1)

Ver/MHz/Vcc/Boot

i.MX51 • v4.2 (v4.3 partially)

• 26/52 MHz

• 1.8V, 3.3V

• Bootable

• SD Phy Layer spec 2.0

• SDHC spec 2.0

• 12/25/50 MHz

• 1.8V, 3.3V

• Bootable

• SDXC

• 12/25/50 MHz

• 1.8V, 3.3V

• Non-bootable

i.MX53 • v4.4

• 26/52 MHz, DDR

• 1.8V, 3.3V

• Bootable

• SD spec 2.1

• 12/25/50 MHz

• 1.8V, 3.3V

• Bootable

• SDXC

• 12/25/50 MHz, DDR

• 1.8V, 3.3V

• Non-bootable

i.MX6Dual/Quad

• v4.4

• 26/52 MHz, DDR

• 1.8V, 3.3V

• Bootable

• SD spec 3.0

• 12/25/50 MHz

• 1.8V, 3.3V

• Bootable

• SDXC

• 12/25/50/100 MHz, DDR

• 1.8V, 3.3V

• Bootable





48TM

• eCSPI/CSPI – one CSPI and two eCSPI ports, same as in

i.MX53

• Keypad – almost same as in i.MX53. 8x8 matrix

supported. (6 x 6 – ―maim‖ configuration, but all pads are

shared with other interfaces). External keypad controller

considered for Netbook applications

• One-wire – same as in i.MX53 One wire EEPROM and

battery connection. Dallas DS2205 compatible.

• UART:

• High speed (up to 4MHz) – covers TIA/EIA-232-F

Standard

• 3 ports, one of them can operate as 8 pins full UART,

DCE and DTE modes. Other are four-wire

• IrDA 1.0

• SIR protocol support (115.2kbps or lower)

• 32 bytes FIFOs for transmitter and receiver,

autobaud.

• 9 bit mode supported

• RS-485 mode supported

• GPT - same as in i.MX53

• Two general purpose timers, each of them is a 32-bit

―free-running‖ or ―set and forget‖ mode timer.

o External/Internal clock selectable

o External/Internal event interval capturing

o Programmable output logic, external output

signal, ARM interrupt.

• PWM - same as in i.MX53

• Two pulse-width modulators (PWM): 16-bit

resolution and a 4x16 data FIFO

• SDMA - same as in i.MX53. Two external SDMA events

• Interrupts - same as in i.MX53.

• I2C –

• Three I2C ports compatible with I2C specifications

v2.1 (all up to 400Kb/s)

• GPIO:

• All multifunctional digital pads have the GPIO

functionality – Total number of GPIOs 224

• The GPIO supports up to 32 interrupts:

• programmable active interrupt edges/level

of external signal

• All of multifunctional (muxed) IOPADs are GPIO capable

and could be programmed independently

• Most of GPIO capable pads are of UHVIO type - 1.65 …

3.6 V operational range with automated voltage range

selection

• Default state for most of GPIO capable pads:

• GPIO

• Input

• Weak PU or PD

That was done to avoid on-board contentions in

default state after reset.

TM





49

• Flash Devices

− NOR flash (using WEIM)

− OneNand (using WEIM)

− NAND flash (using NFC)

• Serial ATA

• Expansion Devices

− SD/eSD/SDXC/MMC/eMMC

− I2C

− SPI

• Serial Downloader

− USB (using USB OTG)

• Plug-in mode

− For custom / user-defined boot

• Boot modes are set via eFuses

• For development purposes, there is

an option to set boot modes via

external pins

TM





50

Toshiba eMMC1 MByte

[ms]

Fast DDR 8-bit (1)(2) 66

Normal DDR 8-bit(1)(2) 90

Normal DDR 4-bit(1)(2) 90

Normal SDR 8-bit(1)(2) 90

Normal SDR 4-bit(1)(2) 103

NAND MLC, 8-bit1 MByte

[ms]

50MHz, SDR(1)(2) 63

100MHz, DDR, theoretical(1)(2) 34

Notes:

1. The boot time cannot be directly scaled to other code size as it includes

not scalable initialization part.

2. HAB: Add 30ms for 1MByte (11.9ms + 1MByte * 16.7us/KByte)

3. HAB: Add 46ms for 1Mbyte (18.9ms + 1MByte * 27.3us/KByte)

NOR, 16-bit1 MByte

[ms]

ASYNC/SYNC InPlace(1)(3) 4

SYNC DDR(1)(2) 110

50ms with HAB

TM





51

• OEM decides which parts of image will be encrypted. Some parts of image must be in plain text, e.g.

− IVT – Image Vector Table (flash header)

− DCD - Device Configuration Data

− CSF – Command Sequence File (authentication scripts)

• Two keys are used for encryption:

− OEM Key is used for program image encryption.

This enables using same program image for all devices.

− CAAM Key (per device) is used for OEM Key encryption.

The encrypted OEM Key is attached to image.

Post-production updates:

• If no change in OEM Key – just a regular update of image, without update of stored encrypted OEM Key.

• If OEM Key changes - update must be done using secure channel with OEM server, or in OEM Service Lab

TM





52

Part PackageBall

PitchApplication Comments

i.MX6 Quad 21x21 FC BGA 0.8mmAutomotive

Consumer• 25x25 ball matrix, fully populated

Pin

Co

mp

ati

ble

i.MX6 Dual 21x21 FC BGA 0.8mmAutomotive

Consumer• 25x25 ball matrix, fully populated

i.MX6 Dual 12x12 PoP FC BGA 0.4mm Consumer• LPDDR2 2xCh/1xCh 32-bit.

• 29x29 ball matrix, partially populated

TM





53

Description

• 12 by 12 by 0.80mm PoP

• Green BOM,

• Ultra Low Alpha BOM and assembled at ASE’s

Top

• 12x12mm JEDEC array,

• Dual channel LPDDR2 (0.5mm pitch)

• 216 balls

Bottom

• 12x12 mm by 1mm thick,

• 569 ball (0.4mm pitch)

– w/Vss on 4 balls @ each corner

– 1 ball depopulated for orientation

Max Total heights with Top memories

Tentative calculations (based on Micron POD’s):

- 2 die in PoP top – 1.45 max ( .350 top mold cap)

Requirements• Coplanarity <= 100um

• Warpage <= 70um

TM





54

Description• 21 by 21 FC TFBGA, 2.0mm zheight

• 0.8mm ball pitch

Package

Characteristics

• Green BOM,

• 624 ball

– 1 center ball depopulated for orientation

• .480 Mold Cap

• .66 Substrate Thickness

• 1.6 package thickness (minus balls)

• .38 NOM ball height

Requirements• Coplanarity <= 100um

• Warpage <= 70um

12 by 12 PoP at .4

607 + 25 Notes:

1. Note that the array is depopulated and has core PWR/GND balls located to minimize board routing complexity and cost,

2. Substrate thickness of 300um is worst case, but we want to evaluate warpage performance of all options before committing to thinner materials,





55TM

• Just two external power rails• Optional SRTC coin-cell rail

• Optional USB PHY rail

• Internal DVS and Power-Up

Sequence and Reset. No need

in ‘smart’ PMIC.

• All external supply rails could

be shared with system

components

• Lowest BoM – no multiple inductors, few external capacitors,

• System level: low cost PMIC or few discrete DCDC

• Maximal flexibility in power management system design

• Two stage power conversion:

external DCDC pre-regulation,

integrated LDOs (incl. DVS)

• Total system level power delivery

efficiency (including linear

regulators) is similar to typical

DCDC based PMU

• 90% or better in high power mode with

internally bypassed FET

• Better than 65% in low power modes

TM





56

―Encapsulating‖ power management system inside i.MX – no external dependencies:

− Power up sequence and defaults is ―closed‖ inside the chip

− System level power management – simple and cheap off-shelf components could be used for system design

− Simple and fast interface with external PMIC / discrete – on/off only

− HW dependent components of power management driver could be placed in ROM. Only standardized API could be exposed outside (to OS)

System complexity reduction

System BoM reduction - no multiple inductors, just few external (or on-package) capacitors

Expecting 3% power saving in high load applications, due to better IR Drop compensation and optimized power distribution

Power up / Power Down Sequencing: No special requirements!





57TM

Features i.MX 53 i.MX 6Dual/6Quad Software Impact (OS, BSP, Tools and Middleware)

Cores

Cortex A8. ARMv7,

Trustzone,

32KB I/D L1 cache.

256KB L2 cache.

Single Core

Dual/Quad core Cortex A9. ARMv7.

32KB I/D L1 cache

1MB L2 Cache

Kernel Enhancements, Low Level Initialization code

Performance Tuning for dual /Quad core. Updates to

drivers for multicore operation.

All is encapsulated within Freescale BSP.

Multithreaded applications will benefit the most from

multicore design.

L2 Cache 256K L2 Cache 1MB L2 Cache Minor changes to L2-$ flush routines.

General Purpose SIMD Neon, VFP Neon, VFP No changes

Internal SRAM 256KB SRAM 256KB SRAM Minor addressing changes for memory map.

Security MX5x Baseline Same + NIST-approved RNG, TZ ASC 380 Minor updates. Uses same block

SDRAM Memory InterfaceLPDDR2, DDR2, single

channel

Dual channel LPDDR2 and 64bit single

channel DDR3/LV-DDR3

Most updates are transparent to software or

encapsulated in freescale BSP. LPDDR2 controller

for example, automatically balances memory

storage between 2 channels with zero software

intervention or required knowledge.

NAND Controller BaselineSame NAND controller but adds 40-bit ECC

and additional CS

Minor changes to driver to account for higher ECC

bit correction

WEIM controller Baseline Same controller with additional chipselect Minor changes to account for additional chip select

System Memory Map BaselineMemory map updated for more SDRAM

space and new peripherals

OEMAddressTable in OAL or low level kernel.

Encapsulated in Freescale BSP

INTC Baseline New INTC for 2 to 4 processors Interrupt Handler changes. Will work seamlessly

with single core. Encapsulated in Freescale BSP

AXI Fabric AXI fabricSame AXI but use dual 64-bit AXI ports

from core complex and run at higher speedTransparent to OS

2D Graphics/3D Graphics

3D: AMD Z430 - 33 MTri/s,

200 Mpxl/s

OpenGL|ES 2.0|

2D: AMD Z160: 200 Mpxl/s,

OpenVG 1.1

3D: Vivante GC2000

200 MTri/s, 1000 Mpxl/s

OpenGL|ES 2.x, OpenCL|EP 1.1

2D: Vivante GC320: 600Mpxl/s, BLIT

VG: Vivante GC355: 300Mpxl/s, OpenVG

1.1

Freescale will provide drivers for OpenGL, OpenVG.

If software on i.MX53 is using OpenGL ES 2.0,

OpenVG, then no changes on customer’s part

LCD Single IPU with support for

LVDS, parallel display

Dual IPU (same version) with support for

dual LVDS, parallel, MIPI DSI and HMDI

v1.4

Same mechanism of accessing IPU. Changes to

display driver to handle communication to new LCD

interfaces like HDM I 1.4. Provided in Freescale

BSP. Customer can use dual IPU’s for more

enhanced layering of overlays vs i.MX53. Current

software will be the same.





58TM

Features i.MX 53 i.MX 6Dual/6Quad Software Impact (OS, BSP, Tools and Middleware)

VPUBaseline VPU with support for

1080p

Updated VPU from same IP provider with support for

1080p high profile, 3D video decode, VP8 codec

If using industry standard APIs then no real changes

at app level to communicate with the VPU. If new

codec implemented, need to Integrate with

DirectShow or GStreamer

Camera Interface and

Controller

Types: 2x 20-bit parallel

Two simultaneous inputs

Same Controller + MIPI-CSI-2 (4lanes) with three

simultaneous inputs.

No changes except selection option of using MIPI

CSI sensors. Driver for MIPI CSI encapsulated in

Freescale BSP

UART, I2C, I2S,

Watchdog, PWM, SPDIF,

Keypad, Timers,

SmartDMA and other APB

peripherals

UART, APB peripheral Same, units, no changes Freescale porting drivers with minimal changes

USBUSB 2.0 Host, USB 12 pin

ulpi, USB OTG 2.0Add USB HSIC

Adding USB HSIC physical layer driver to BSP

(encapsulated in Freescale BSP). HSIC seen as just

another USB Port by upper layers.

SD/MMC/SDIO

Four SD/SDIO/MM Card

Interfaces supporting mmc

4.1, SD 2.0

Add support for SDXC, MMC 4.4New Driver for SD 3.0/SDXC. Encapsulated in

Freescale BSP

GPIO and Peripheral

Devices Registers GPIO and ALT Functions Updated pin mux, alt functions

Minimal changes to underlying configuration code to

ensure proper pin mux chosen.

Audio Baseline Additional # of I2S ports + ESSAI peripheral

Updated drivers to take advantage of ESAI port . No

changes by customer since encapsulated in

Freescale BSP.

Performance Monitoring

Unit

Standard Cortex A8 PMU,

ASSP Registers, Events,

Interrupt based

Updated counters for Cortex A9 and multicore Encapsulated in Freescale BSP

Trust Boot Trusted Boot with Trustzone SameMinor changes due to new peripherals on tustzone

list

BootROMBootrom support for USB,

NAND, NOR , SD/MMC.Same + additional bootsource requirements.

Freescale will change this but it is just boot routines

used by customer.

AP – CP Interface USB, UART, SPI, SD IO. Same + MIPI HSI, USB HSICAdditional driver for HSI and HSIC but these are

provided by Freescale.

SATA, P-Sata P-SATA, SATA II – 1.5Gbps P-SATA dropped. SATA II at 3GbpsIf not using P-SATA then no change. SATA-II is same

IP but runs at 2X bandwidth than i.MX 53

Ethernet 10/100 Ethernet , IEEE 1588 Gigabit Ethernet, IEEE 1588

If not using ethernet, no changes. If using ethernet,

IP is same IP source but enhanced for Gigabit.

Encapsulated in Freescale driver.

TM





59

• SABRE Platform for rapid tablet development on i.MX 6Dual/6Quad

• 10.1‖ 3D enabled display for glassless 3Dviewing

• 1080p 3D video decode lets you experience hours of HD video playback in full 3D. 720p 3D video encode allows you to record your life in 3D. Full duplex video in HD (720p) provides a great video conferencing experience.

• Conserve battery life with hardware-accelerated Adobe Flash Player 10.x which leverages dedicated graphics and video engines to deliver an outstanding visual experience.

• Tri-core graphics solution gives you200MT/s 3D games, ultrafast mapping, crystal clear UI’s to reduce power consumption and improve graphics performance, giving you quicker response time and more realistic gaming.

• Smartly integrated i.MX 6Dual/6Quad offers more on chip including PMIC, LVDS and USB PHYs, passing on significant BOM cost savings.

Smart Application Blueprint for Rapid Engineering





60TM

Feature SABRE-I (i.MX53) SABRE-II (i.MX 6Series)

Enclosure Baseline Same as SABRE-I

LCD Enhanced viewing angle LCD

Battery 84W/H Same range

Ports 2x USB, 1x HDMI, 1x USB OTG,

Debug port, power adaptor,

volume, audio jacks, docking

connector, Full size SD

Same except removal of docking

connector and addition of 120-pin

expansion connector

Keys Standard Android capacitive keys Same

WIFI Atheros Same

ZigBee Freescale Same

Sensors Freescale Same + ‗Eve‘ sensor for

compass/accel

Memory Micron (1GB) Same + 2GB

SATA connector SATA –I with Sandisk 32GB card Same + SATA-II

3G Infineon 3G modem Same + Voice capable

GPS Atheros Same

Camera 5MP Omnivision 8MP Omnivision

TM





61

• i.MX 6Quad 1.2Ghz Cortex A9

• Other Freescale silicon

− Freescale PFUZE PMIC

− MMA8451Q 3-Axis Accelerometer

− MAG3112 Compass

− MC1323X Zigbee

• Memory

− 2GBs DDR3 (4GB support in 2012)

− 32GB Sandisk eMMC

• OS Support

− Android, Ubuntu, Linux, Windows Embedded

• User Interface

− 10.1‖ 1024x768 3D enabled display with capacitive multi-touch

− Stereoscopic 5MP cameras for 3D imaging/encode

− 8MP rear facing camera for picture taking

− Capacitive Buttons: Home, Menu, Back, Search

− Other Buttons: Power, Reset, Volume up/down

• Connectivity

− Atheros GM22 GPS Receiver

− Atheros AR6133 Wi-Fi/BT Module

− Infineon Amazon-1 3G Module

• I/O‘s:

− HDMI connector

− 1x Full size SD Card Slot

− 2x High-Speed USB Host, 1 x Micro-USB

− 1x SATA port, 1x LVDS display footprint

− Debug PCB with Ethernet 10/100/1000, JTAG, UART

− Stereo Speaker, Headphone/Microphone





62TM

i.MX SABRE for Automotive InfotainmentModular Reference Design Concept

• CPU Card

− Capable of stand-alone operation

− Processor, memory, power, USB,

Ethernet, SD-card slot, Display

− Attaches to Application Module for more

comprehensive system evaluation and

application benchmarking

− Industry standard MXM 3.0 connector

• Main Board

− Expanded connectivity options (CAN,

MOST, USB, dual displays, SDIO

− Connectors for Processor Module and

Wireless Modules

• Wireless Modules

− GPS Module

− Bluetooth/WiFi Module

− 3G Modem Module

− Radio Tuners

− IAP

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