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FPGAbasedimplementationofCORDICusingdifferentnumberformat

CONFERENCEPAPER·JANUARY2013

DOI:10.1109/TAEECE.2013.6557315

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BurcuKirSavaşKocaeliUniversity

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SuhapSahin

KocaeliUniversity

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FPGA Based Implementation of

CORDIC using different number format

Bureu KIR Computer Engineering Dept.

Mehmet Ali AL TUNCU Computer Engineering Dept.

Suhap �AHiN Computer Engineering Dept.

Kocaeli University Kocaeli,Turkey

suhapsah in@kocaeli.edu.tr

Kocaeli University Kocaeli, Turkey

burcu.kir@kocaeli.edu.tr

Kocaeli University Kocaeli, Turkey

mehmetali. altuncu@kocaeli.edu.tr

Abstract- In modern computer systems (communication systems, military systems, medical applications, etc.) are sophisticated mathematical operations and trigonometric calculations widely used. CORDIC (Coordinate Rotation DIgital Computer) architecture should be used on digital computers to implement complex mathematical operations and trigonometric calculations.

In this study, two architectures called FP-CORDIC and IQ­CORDIC have been devised to implement CORDIC algorithm. These architectures have been realised with IEEE-754 and IQ­Math in order. Also they have been compared according to execution time, process accuracy and hardware performance criteria on FPGA.

Keywords- FPGA, CORDlC, 1EEE-754, 1Q-Math

I. [NTRODUCTION

At present, the success of DSP algorithms makes a strong impression thanks to FPGAs that have high-performance and quite capability. This success provided the realization of many DSP algorithms on FPGA over the last decade [1, 2, 3 and 4].

[n 1956, CORDIC (COordinate Rotation D[gital Computer) algorithm, discovered by Voider [5], was computed in many calculations such as trigonometric, hyperbolic, logarithmic and linear functions. Today, the main application areas of the CORDIC algorithm are the followings: filtering, digital signal processing, matrix algebra, image processing etc.

CORDIC algorithm works as a cycle with the shift and add operations method [6]. Due to the algorithm's using only shift and add methods, this algorithm does not cover much space on the hardware. Thus, it provides very fast operation [7, 8].

CORDIC architecture, implemented easily in today's computer, can not be used effectively due to that the computers are not able to operate collaterally. FPGA's, having the capability of operating in parallel, being frequently used in applications enabled CORDIC algorithm which has an iterative structure to be implemented effectively.

Modern applications need accurate and flexible computing requirements. Hence, implemented CORDIC architecture must have the capability of delicate and flexible computing

ISBN: 978-1-4673-5613-8©2013 IEEE

like other digital systems. CORDIC architecture can not be achieved by the several digital systems due to the slowness of the system as well as the computational load the system required. An architectural design to meet the needs like CORDIC architecture's being able to produce accurate results and to operate collaterally while it is being realized on FPGA, must be devised [6,9].

Although there are many CORDIC architecture developed by using FPGA, CORDIC architecture is to be implemented by using the "IQ-Math" number system that Texas C28x DSP family firm runs or by using the IEEE 754 "Floating-Point Numbers" in order to achieve the requirement mentioned above [1 0,11 ].

[n this study, two architectures named FP-CORDIC and [Q­CORDIC have been compared according to execution time, process accuracy and hardware performance criteria on FPGA. Second section gives information about the number of format. In the third section CORDIC algorithm and this operating principle are mentioned. The fourth section presents that CORDIC algorithm implementation is based on FPGA. Section five concludes the work.

II. NUMBER SYSTEMS

A. IQ-Math Number Format

[Q-Math, fixed-point number format, used by the Firm Texas Instruments is shown in Figure 1. [t shows that 'S' represents the sign bit, 'I' represents the integer place of number and the fractional place of number is indicated by 'Q'. If the sign bit is '0', the number is positive; otherwise it is negative when the sign bit is '1'. Numbers are converted into positive by taking two's complement. For example, the transformation of the decimal numbers of 0.3 to the binary number system is shown below.

O.3xO.2=O.6 0 O.6xO.2=1.2 1 O.2xO.2=0.4 0 II

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QJ-- ---------- , ----------------- ,

: S I I I I ... I I I IiQ Q Q Q ... Q Q Q Q: --- �----�-----k-------�-------� Sign bit intege .. place dechl1al place

Fig. I Representation of the IQ-Math fixed-point number format

Equation (1) shows converting IQ- Math format number to decimal format.

K M N = _(2K+1) + I 2i 1 (i) + I rJ Q(j)

i�l i�l (1)

In equation (1), 'N' indicates the real number, 'K' indicates the bit of integer place and the bit of decimal place is indicated by 'M'.

1) Addition: The signal flow chart of the IQ- Math number system addition is shown in figure 2.

-/+

Fig. 2 The signal flow chart of the IQ- Math number system

Additive function in this number format operates according to the rules of the addition in binary format additive function. 'I' represent the integer place and 'Q' represents the fractional place. In figure 2, integer place is demonstrated on the left side, and decimal place is demonstrated on the right side for each input. Finally, the carry that is obtained from the sum of the variables 'Q (Qcany)' and 'I' variables values that is kept are added up. The results, two variables called 'Ians' and 'Qans' , are kept. Any overflow addition is not considered.

2) Multiplication: Basically IQ-Math number of the multiplication algorithm is the same fractional numbers multiplication. The signal flow chart of the IQ- Math number system multiplication is shown in figure 3.

ISBN: 978-1-4673-5613-8©2013 IEEE

yes 1._---< input2(31)=T >--_1

Fig. 3 The signal flow chart of the IQ- Math number system multiplication

In multiplication, the numbers given as input to the largest valance bit is checked. If this bit is logically value '1', the number is negative, otherwise positive. If the number is negative, two's inverse of the number as shown in figure 3 and it is made a positive number by adding ' 1 '. Then multiply the two numbers in base-2 numeral system. But the number of 64-bit occurs when the 32-bit two numbers in base-2 numeral system are multiplied. So that, 64-bit 'me' register is kept as a result of the multiplication. Value in register two's complements if any of the numbers from the input is negative. Finally, the most significant of the 32-bit number to 64-bit number for algorithms is taken and is given out as output.

B. 1EEE-754 Floating-Point Number Format

Implemented within the scope of previous studies, the IEEE-754 Floating-Point Number Format addition / subtraction and multiplication [12] has been optimized and used in this study. In equation (2) floating-point number format is provided. In this formula, it is demonstrated that 's' indicates sign bit, 'e' indicates exponent of number and 'f indicates multiplier expression.

N = (-1)' 2e-hias (1.f) (2)

The absolute number is determined firstly by the addition of the floating-point numbers and the small number with the upper part of number synchronized as equations (3).

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Nj = (_I)"2e,-biaS(I.!j) N 2 = (_1)'2 2e,-bia'(I.!2)2e,-e, (3)

The total value of two decimal numbers summation is obtained as in equation (4). If the sum of multiples is greater than or equal to 2, the total value is written as in equation (5). Subtractions are similar to addition.

(4)

(5)

Floating-point multiplication is given in equation (6). As in

An example of the operation mode of CORDIC Algorithm is shown in Table \ brietly.

Example: �=37.38° Qn=tan-1 (Tn) (n={O, 1,2 ... } � L +) .

TABLE I. ORDER OF PROCESS

tan(Qn) Lookup Table Process Steps TU=I 45 45.0 (> 37.38)

Tl=0.5 26.6 45.0-26.6= 18.4«37.38) 2-"=0.25 14.0 18.4 + 14.0 = 32.4 « 37.38) 2-J=0.125 7.1 32.4 + 7.1 = 39.5 (> 37.38)

2-4=0.0625 3.6 39.5 -3.6 = 35.9 « 37.38) 2-)=0.03125 1.8 35.9 + 1.8 = 37.7 (> 37.38)

T6=0.015625 0.9 37.7 -0.9 = 36.8 « 37.38)

the case of addition, if th: sum .of m�lti�les is �eater than or

IV. CORDIC ALGORITHM IMPLEMENTATION BASED ON equal to 2, the total value IS attamed hke m equatIOn (7).

FPGA

(6)

(7)

III. CORDIC ALGORITHM

CORDIC algorithm is a method of shifting the coordinate system of vectors until it is initialized at the angle between two vectors on the X-V axis. The angle is calculated by shifting and adding operations on the X-V axis. The operation mode of CORDIC Algorithm is shown in Figure 4.

Vj y

x

Fig. 4 CORDIC Algorithm

Angle value at each step can be calculated as follows. The sum of all the angles in steps should (9) give the angle of rotation 8.

1 On = arct an ( -) 2n

L SnOn = ° n=() (10)

Here, Sn = {-I, + I} and in accordance with the above equations, the value of tan 8n is; tan 8n = Sn Tn.

(I\ )

ISBN: 978-1-4673-5613-8©2013 IEEE

The first stage of implement CORDIC Algorithm on FPGA is to determine the number format to be used by the system [9].

Calculation of complex mathematical functions such as CORDIC usually needs a larger range of numbers. Furthermore, it is preferable to use tloating-point numbers due to their dynamic representation [\3]. However, despite their many advantages, applications implemented with tloating­point numbers work slower than the ones in fixed-point number.

In addition, applications implemented with tloating-point numbers format use quite a lot of hardware resources of FPGAs' [14]. In this study, CORDIC algorithm is tested with both number formats and the results are given in this section by comparison. The flow chart of the implementation of a CORDIC algorithm on FPGA using IQ-Math number format is given in Figure 5.

Fig. 5 The flow chart of the implementation of a CORDIC algorithm on FPGA using IQ-Math number format

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First, the angle is checked whether the value is positive. Then, it is determined to which region the value of the angle belongs in the x-y plane. Angle value is scrolled to the region I if it belongs to the region II, III or IV. Finally, the angle value is compared with epsilon values in the lookup tables. As a result of the comparison, the coordinate values of the angle are obtained. The coordinate values are obtained by the following formula:

inputi+l = inputi - di * epsilon(i -1)

Xi+1 = Xi - Yi * di * 2-i

Yi+l = YI - XI * di * 2-1

Here, d = +1 is taken if the input value IS positive, otherwise it is taken as d = -I.

The results of the implementation of a CORDIC algorithm on FPGA using Floating-point and IQ-Math number format and the part of values in Matlab are shown in Table 2 (a), Table 2 (b) and Table 2 (c).

TABLE II. THE RESULTS OF THE IMPLEMENT A TlON OF A CORDIC ALGORITHM ON FPGA AND MATLAB USING FLOATING-POINT AND IQ-MATH

NUMBER FORMAT

IEEE-754 (FPGA) Angle cos sin 61.25 0.4810 14043 0.876713037

146.60 -0.834836006 0.550498723 230.25 -0.639433562 -0.768846452 287.21 0.295843660 -0.955236494 360.00 0.9999997019 0.000012937

(a) IQ-Math(FPGA)

Angle cos sin 61.25 0.481013298 0.876713037

146.60 -0.834835290 0.550499200 230.25 -0.639433622 -0.768845796 287.21 0.295843124 -0.9552364349 360.00 0.999999761 -0.000013589

(b)

Matlab Angle cos sin 61.25 0.4810 140708 0.876712864

146.60 -0.834836074 0.550498602 230.25 -0.639433495 -0.768846400 287.21 0.295843696 -0.955236352 360.00 0.999999991 0.000012922

(c) According to the results obtained in the table above the

implementation of a CORDIC algorithm on FPGA using Floating-point number format has produced more delicate results than IQ-Math number format. In the study of IQ-Math, process accuracy is 2.3842E-007 whereas in the study of IEEE-754, process accuracy is 1.4E-45.

Table 3 presents the results of synthesis FPGA module implemented with 110Q22 number format and Floating-point number format. The application has developed with Xilinx ISE 10.1 software and it is implemented by using a

ISBN: 978-1-4673-5613-8©2013 IEEE

Xilinx XC3 S500E-5FG320 FPGA chip which belongs to the family of Spartan 3E.

TABLE III. THE RATES OF HARDWARE RECOURSES UTILIZATION THAT THE CORDIC ARCHITECTURE OF IQ-MATH AND FLOATING POINT USES ON

SPARTAN3E FPGA

Logic Utilization The table of Hardware Resource Utilization on FPGA(estimated

value) Used Utilization

IlOQ22/ IlOQ22/ IEEE754 IEEE-754

N umber of Slices 808/2726 %17/58 N umber of Slice 284/260 %3/2

Flip Flops Number of 4 input 1569/5081 %16/54

LUTs Number of 111 %4/4

GCLKs

TABLE IV. MEAN-SQUARE ERRORS (MSE) OBTAINED BY BEING COMPARED TO THE RESULTS BELONGING TO CORDIC ALGORITHM WITH THE

RESULTS OF IEEE-754 CORDIC ARCHITECTURE AND IQ-MATH CORDIC ARCHITECTURE CODED BY USING MA TLAB

Mean-Square Errors (MSE) IEEE-754 Cordie IQ-Math Cordie

Algorithm Algorithm cos I sin cos I sin

9.3408e-008 I 8.6507e-008 7.7376e-005 I 2.0431e-004

V. CONCLUSIONS

Importance of the number formats comes to the forefront when algorithms like CORDIC including complex mathematical are being implemented [9]. As can be seen in Table 3, when compared to the floating-point number format, architecture implemented with IQ-Math number format covers less space; therefore, less resource are used on FPGA. Additionally, architecture implemented with IQ-Math number format gives faster results in terms of processing time when compared to the floating-point numbers. But as shown in Table 4, the floating-point number format gives more accurate results when compared to IQ-Math number format.

[1]

[2]

[3]

[4]

[5]

REFERENCES

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[6] Y. Hu, "CORDIC-Based VLSI Architectures for Digital Signal Processing," IEEE Signal Processing Magazine , vol. 9, pp. 16-35, July 1992.

[7] K. D. Underwood, "FPGAs vs. CPUs: Trends in Peak Floating-Point Performance," Proceedings of the ACM International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2004.

[8] Y. Hu, "CORDIC-Based VLSI Architectures for Digital Signal Processing," IEEE Signal Processing Magazine, vol. 9, pp. 16-35, 1992.

[9] S. Sahin, S. Dikme�e, A. Kavak, "Which Number Format to Use for Baseband Wimax Modem Implementation on an FPGA ", Communication and Applications Conference, SIU, pp. 1-4,2008.

[10] A. Sahin, A. Kavak, Y. Becerikli, H. E. Demiray, "Implementation of floating point arithmetics using an FPGA," Mathematical Methods in Engineering, pp. 445-453, 2007.

[11] M. A. <;:avuslu, C. Karakuzu, S. Sahin, M. Yakut, "Neural network training based on FPGA with floating point number format and it's perfonnance," Neural Comput & Applic, pp. 195-202,2011.

[12] I. Az, S. Sahin, M. A. Cavuslu, "H1Zh Fourier Ve Ters H1Zh Fourier D6nii�iimlerinin Fpga'da Donalllmsal Olarak Gergeklenmesi ", SIU, IEEE 15th, pp. 1-4,2007.

[13] D. M. Munoz, D. F. Sanchez, C. H. Llanos, M. Ayala-Rinc6n, "Fpga Based Floating-Point Library for CORDIC Algorithms," Southern Conference on Programmable Logic - SPL, IEEE, pp. 55 - 60, 2010.

[14] R. Andraka, "A Survey of CORDIC Algorithms for FPGA Based Computers," ACM 0-89791-978-5/98/01, pp. 191-200, 1998.

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