fabrication of cmos integrated circuitseng.staff.alexu.edu.eg/~mmorsy/courses... · cmos...
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FABRICATION OF CMOS
INTEGRATED CIRCUITS
Dr. Mohammed M. Farag
Faculty of Engineering - Alexandria University
Overview of CMOS Fabrication Processes
The CMOS Fabrication Process Flow
Design Rules
Outline
EE 432 VLSI Modeling and Design 2
Faculty of Engineering - Alexandria University
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
CMOS Fabrication
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Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
Inverter Cross-section
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n+
p substrate
p+
n well
A
YGND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
Faculty of Engineering - Alexandria University
Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
Well and Substrate Taps
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n+
p substrate
p+
n well
A
YGND V
DD
n+p+
substrate tapwell
tap
n+ p+
Faculty of Engineering - Alexandria University
Transistors and wires are defined by masks
Cross-section taken along dashed line
Inverter Mask Set
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GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
Faculty of Engineering - Alexandria University
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Detailed Mask Views
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Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
Faculty of Engineering - Alexandria University
Overview of CMOS Fabrication Processes
The CMOS Fabrication Process Flow
Design Rules
Outline
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Faculty of Engineering - Alexandria University
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Fabrication
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Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
Faculty of Engineering - Alexandria University
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
Fabrication Steps
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p substrate
Faculty of Engineering - Alexandria University
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
Oxidation
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p substrate
SiO2
Faculty of Engineering - Alexandria University
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
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p substrate
SiO2
Photoresist
Faculty of Engineering - Alexandria University
Expose photoresist through n-well mask
Strip off exposed photoresist
Lithography
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p substrate
SiO2
Photoresist
Faculty of Engineering - Alexandria University
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Etch
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p substrate
SiO2
Photoresist
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Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
Strip Photoresist
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p substrate
SiO2
Faculty of Engineering - Alexandria University
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
n-well
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n well
SiO2
Faculty of Engineering - Alexandria University
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps
Strip Oxide
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p substrate
n well
Faculty of Engineering - Alexandria University
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
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Thin gate oxide
Polysilicon
p substraten well
Faculty of Engineering - Alexandria University
Use same lithography process to pattern polysilicon
Polysilicon Patterning
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Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Faculty of Engineering - Alexandria University
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
Self-Aligned Process
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p substraten well
Faculty of Engineering - Alexandria University
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
N-diffusion
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p substraten well
n+ Diffusion
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Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
N-diffusion cont.
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n wellp substrate
n+n+ n+
Faculty of Engineering - Alexandria University
Strip off oxide to complete patterning step
N-diffusion cont.
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n wellp substrate
n+n+ n+
Faculty of Engineering - Alexandria University
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
P-Diffusion
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p+ Diffusion
p substraten well
n+n+ n+p+p+p+
Faculty of Engineering - Alexandria University
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contacts
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p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
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Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metalization
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p substrate
Metal
Thick field oxide
n well
n+n+ n+p+p+p+
Metal
Faculty of Engineering - Alexandria University
Overview of CMOS Fabrication Processes
The CMOS Fabrication Process Flow
Design Rules
Outline
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Faculty of Engineering - Alexandria University
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
Layout
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Faculty of Engineering - Alexandria University
Design rules (DRs) are a set of geometrical specifications that dictate the design of the layout masks
Such rules provide numerical values for minimum dimensions, line spacing, and other geometrical quantities
DRs are derived from the limits on a specific processing line and must be followed to insure functional structures on the fabricated chip
There are given numerical values in the DR listing; violating these values may lead to failure. In our notationw = minimum width specifications
s = minimum spacing value
d = generic minimum distance
Design Rules
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Faculty of Engineering - Alexandria University
DRs have units of length (usually µm)
DRs change with the fabrication technology
The popularity of VLSI fabrications has introduced the concept of the silicon foundry
A foundry allows designers to submit designs using a state-of-the-art process
Most foundry operations allow the submission of designs using a simpler set of design rules that can be easily scaled to different processes
These are called lambda design rules where all DRs
are expressed in terms of lambda (𝜆 =1
2𝐿𝐺𝑎𝑡𝑒)
Design Rules (2)
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Faculty of Engineering - Alexandria University
Why do VLSI technology have Design Rules
fabrication process has minimum/maximum feature sizes that
can be produced for each layer
alignment between layers requires adequate separation (if
layers unconnected)or overlap (if layers connected)
proper device operation requires adequate separation
“Lambda” Design Rules
lambda, λ, = 1/2 minimum feature size, e.g., 0. 6μm process ->
λ=0.3μm
can define design rules in terms of lambdas
allows for “scalable” design using same rules
Why Design Rules
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Faculty of Engineering - Alexandria University
Basic Rules
minimum width
minimum spacing
Surround
Extension
Design Rule Types
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Faculty of Engineering - Alexandria University
Example of minimum spacing and width rules (poly)
Spacing and Width Design Rules
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Faculty of Engineering - Alexandria University
Example of a surround rule (an active contact)
This rule guards against a misaligned contact cut
patterns during the lithographic exposure setup
Surround Design Rules
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Faculty of Engineering - Alexandria University
The accuracy of photolithography is the main factor
that can lead to misalignment problems
Figure shows a potential problem with active
contacts due to misalignment
Surround Design Rules (2)
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Faculty of Engineering - Alexandria University
Extension-type design rules also rend to be based on
misalignment problems
Figure shows the extension distance rule for
polysilicon gate and a potential misalignment failure
Extension Design Rules
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Faculty of Engineering - Alexandria University
Some geometrical design rules originate from physical
considerations such as
The linewidth limitation of an imaging system
The reticle shadow projected to the surface of the photoresist does
not have sharp edges due to optical diffraction
For example, a lightwave with an optical wavelength of 𝜆 cannot
accurately image a feature size much less than 𝜆
The etching process introduces another type of problem as
shown in Figure
Physical Limitations
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Conservative rules to get you started
Simplified Design Rules
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Transistor dimensions specified as Width / Length
Minimum size is 4l / 2l, sometimes called 1 unit
In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
Inverter Layout
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Faculty of Engineering - Alexandria University
The lecture notes are developed using the Uyemura
VLSI book and Harris lecture notes of the CMOS
VLSI Design book.
About these Notes
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