ez-courseware state-of-the-art teaching tools from ams teaching tomorrow’s technology today
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EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today. New Trends in VLSI Design. Processor Performance. Why is Performance Improving?. Better circuit design More memory, cache and register More parallelism (wider data bus, pipelining, etc.) - PowerPoint PPT PresentationTRANSCRIPT
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EZ-COURSEWAREEZ-COURSEWARE
State-of-the-Art Teaching ToolsState-of-the-Art Teaching Tools
From AMSFrom AMS
Teaching Tomorrow’s Teaching Tomorrow’s Technology TodayTechnology Today
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New Trends in VLSI Design
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Processor Performance
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Why is Performance Improving?
• Better circuit design
• More memory, cache and register
• More parallelism (wider data bus, pipelining, etc.)
• Transistors are switching faster!!!!
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Simple ScalingParameter
Full Scaling
Constant Voltage Scaling
Dimensions:
width, length, oxide thickness1/S 1/S
Voltages:
supply, threshold1/S 1
Intrinsic gate delay 1/S 1/S2
Gate Capacitance 1/S 1/S
Current per device 1/S S
Power dissipation per gate 1/S2 S
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Chip AreaTechnology (m) 1.51.5 1.01.0 0.80.8 0.60.6 0.350.35 0.250.25
Intel 386 DXIntel 386 DX
Intel 486 DXIntel 486 DX
PentiumPentium
Pentium Pro &Pentium Pro &Pentium IIPentium II 1cm1cm22
Remark:Remark:m = mirconm = mircon
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Transistor Count vs. Year
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Average Transistor Price vs. Year
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Can Scaling Continue in Future?
• Scaling works well in the past
• In order to keep scaling to work in the future, many technical problems need to be solved.
Year 1989 1992 1995 1997 1999Technology
(m) 0.65 0.5 0.35 0.25 0.18
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The Roadmap
• National Technology Roadmap for Semiconductors (NTRS)
• Called ITRS (International TRS) since 4th Ed• Projection of future technology requirements for the next 15
years. Edition Year of Publication
1st 1992
2nd 1994
3rd 1997
4th 1999
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Roadmap Overview
• Focus Technology Working Groups– Design & Test– Process Integration, Devices & Structures– Front End Process– Lithography– Interconnect– Factory Integration– Assembly & Packaging
• Crosscut Technology Working Groups– Environment, Safety & Health– Defect Reduction– Metrology– Modeling & Simulation
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Technology CharacteristicsYear 1999 2001 2003 2006 2009 2012
Technology(m) 0.18 0.15 0.13 0.1 0.07 0.05
Density(#trans./cm2) 6.2M 10M 18M 39M 84M 180M
Chip size(cm2) 3.40 3.85 4.30 5.20 6.20 7.50
Power(W) 90 110 130 160 170 175
Frequency(MHz) 1250 1500 2100 3500 6000 10000
# routing layers 6-7 7 7 7-8 8-9 9
*Data for high-performance microprocessor*Data from 97 Edition of Roadmap
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Technical Problemswith Future VLSI Technology
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Too much transistors
• Design are too complicated
• No way to do it manually
• Solutions:– CAD– Design hierarchically– Design reuse
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Area, Performance, Power, Noise
• Important to keep area small.• How to achieve such a good performance?• Power consumption is huge.
Heat dissipation is also a problem.• Both Capacitive and Inductive Noises are not
ignorable now.
• Solutions:– Physical Design is an appropriate stage to handle all these.– Many research needs to be done.
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Interconnect Area
• Too many interconnects.• Occupy too much area.
• Solution:– More interconnect layers.– Made possible by Chemical-Mechanical Polishing (CMP).– Note that more layers doesn’t necessarily mean less
interconnect area.– Also, routing is no longer a 2-D problem.
Hence, new CAD algorithms needed.
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SEM Photo of Metal Layers
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Cross-Section of Metal Layers
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0
5
10
15
20
25
30
35
40
0.65 0.5 0.35 0.25 0.18 0.13 0.1
Del
ay (
ps)
Interconnect Delay
Gate Delay
Interconnect DelayInterconnect Delay
Technology Generation(m)1989 1992 1995 1998 2001 2004 2007
Source: SIA Roadmap 97
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Interconnect Delay
• Dominating factor in determining circuit performance nowadays.
• Solutions:– Copper wire– Low-k (dielectric constant) material– Interconnect Optimization at physical design
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Design Planning
• Need to plan ahead during the early stages of VLSI design cycle.
• Need to take physical design into consideration early.
• Many research needs to be done.
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Summary
• Technology Trend:– Transistors are smaller.– Transistors and Interconnects are denser.– Chip areas are larger.– Number of metal layers are more.
• Problems:– Design complexity.– Tradeoff of Area, Performance, Power, Noise.– Interconnect area and Interconnect delay.– Increasing planning requirements.
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