IEEE TRANSACTIONS ON APPLIED SUPERCONLWCTIVITY, VOL. 7, NO. 2, JUNE 1997 2747

with coarse quantization was implemented using a latching

Experimental Digital SQUID with Integrated Feedback Circuit

,z

U. Fath, R. Hundhausen, T. Fregin, P. Gerigk and W. Eschner Dornier GmbH, 88039 Friedrichshafen, Germany

A. Schindler and F. H. Uhlmann Technical University of Ilmenau, 98684 Ilmenau, Germany

ANALOG s - SIGNAL comparator and a write gate which acts in conjunction with COMPARATOR

I DIGITAL I FILTER

the pickup loop as an integrator. The digital data stream @F

INTEGRATOR was amplified at 4.2 K using a current amplifier stage, a vol- tage driver gate and a GaAs FET impedance transformer. ax

L/--

all 9 T- The analog input signal was reconstructed at room tempera- ture by integrating the data stream using a 17 bit up/down I OUTPUT L

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Analog Signal

Pick-up

400nH

600nH

Intermediate Circuit

Comparator

Comparator

Lco=lOpH

-p Clock

Voltage Driver

4.2 K

Output ' 300 K

' I ,I

Fig. 2. Lumped equivalent circuit of the experimental digital SQUID with integrated feedback circuit. The feedback circuit is shown at the left, the amplifiers to increase the output voltage level at the right.

carried out by adding or subtracting single flux quantum to the pickup loop by the write gate. The flux is accumulated in the superconducting pickup loop. An AND gate acts as a current amplifier. The ten series connected, two branches junction array serves as voltage driver. The last amplifier stage at 4.2 K is a GaAs FET impedance transformer. This design is similar to that of Fujimaki [7], except for the use of the pickup loop inductance to accumulate the flux quanta.

In order to couple the flux from the large pickup coil inductance Lpu to the small comparat,or inductance LCO a two transformer concept [8] has been adopted. The re- sulting flux transfer ratio TB determines the quantization step size A@:

where c is a numerical constant depending on the transfor- mer arrangement [7]. A@ was adjusted aiming at 1m@o, where @O = h/2e is the elementary flux quantum.

Line filters and clock distribution resistive networks (not shown in Fig. 2) have been implemented on a second chip respectively on the chip carrier which houses the GaAs FET impedance transformer, too.

Both the comparator and the write gate inductor are designed to form a second-order gradiometer. A micro- graph of the write gate layout is shown in Fig. 3. The design has been fabricated at Hypres Inc. on a standard 5 mm x 5 mm chip site. Because the chip size was restric- ted a small dummy pickup coil was used instead of a large sensitive coil arrangement. The main components of the sensor have been fabricated on a second chip (test chip) to be able to take measurements without interference of wiring.

Iv. MODELING AND SIMULATIONS

We have made extensive numerical simulations to sup- port the sensor design and the interpretation of measure- ments. In view of given technological constraints reasona-

Fig 3 Micrograph of a fabrirated write gate Four washers form a second order gradiometer. The size of the washer holes is 10 pm. The leads at the top are connected with the pickup loop. Two control lines and the leads from the comparator (in the centre) are located at the bottom

ble operation margins for the sensor components were ob- tained using circuit-orientated simulations. Transient noise simulations have been performed focused on the occasional switching behavior of the ac-biased latching comparator. Because of thermal noise the appearance of a positive (ne- I

gative) output pulse per clock is characterized by a certain probability P+ (P-). Deduced from simulations we intro- duced an analytical expression for the resulting switching probability PC = P+ - P- as comparator characteristics [9] considering various circuit parameters, the rms flux noise C T ~ and the working point adjusted by the clock amplitude f c ~ . In the presence of thermal noise Pc degrades from an ideal step function to a smooth curve with a finite li- near range @ L tl fit, as shown in Fig. 4. The slope dPC/d@ determines both sensitivity and bandwidth of the whole sensor.

2749 - ' ' - ' ' " ' ' ' ' 1 ' ' " " " 1 ' . ' I 100

- E 50

2 0

0

z a

3

e a m E ._ e 5 -50

I ._ -

-100 -20 -10 0 10 20

FIUX in Comparator QCo [m@,,]

Fig. 4. Switching probability Pc of the comparator for a bipolar harmonic clock. Simulations results (symbols) are in good agreement with a analytical approximations (solid lines) from [9].

6

5

1

0 0.0 1 .o 2.0 3.0 4.0 5.0

A @ h @

Fig. 5. Flux noise versus step size A@ in order of the rms noise level U+ as parameter (fc = 10 MHz; Ico = I c o , ~ ~ ~ ) .

The requirements for the working point adjustment and the influence of parasitic effects like quantization noise or bit errors were studied using a mathematical model of a delta modulator structure shown in Fig. 1. The com- parator operation is described by our specified model of switching probability combined with a pseudo-random ge- nerator. The integrator function for the feedback operation corresponds to a simple up/down counter [6] that produced bit errors for a given probability (BEP). This digital repre- sentation of the feedback loop enables studies of the sensor dynamics over millions of clock cycles in a more general way than a small signal analysis alone. We found some remarkable parameter dependencies in view of sensitivity and linearity, here characterized by the flux noise 6 and total harmonic distortion (THD).

One important question starting with the design of a di- gital SQUID is the choice of the quantization step size A@ in regarding to the rms flux noise g@. To obtain a high sensitivity of the signal to be measured the flux transfer ratio T@ should be as large as possible, however keeping in mind the limitation introduced by the inductance ratio

lo 10

I

Fig. 6. Total harmonic distortion is shown versus normalized sinu- soidal signal slew rate SN = m a x [ @ s ] / @ ~ (U+ =5 m@o; A@ = 1 m@O; fc = 10 MHz; 6s =O.l@o -+ SN =signal frequency/l6kHz ).

lo-' 7 16' I\

. . . . . . . . . . . . . 1 o3 1 o4 1 o5 1 . . . . . . I 4

10' 10' 1 o2 Frequency f [Hz]

Fig. 7. Flux noise spectrum of digital output with distortions from a sinusoidal 150 Hz input flux and bit errors in the feedback loop (fC=lOMHz; @s=O. l@o; Ico=l.02Zco,opt; BEP=3. lop5).

Lco/Lpu in (1). If the step size exceeds the rms noise band of the comparator: A@ >> G @ , the feedback loop be- come insensitive for small input signal changes. The flux noise is dominated by the quantization noise as shown in Fig. 5. The choice A@ 2: CT@ seems to be reasonable. Lower values of A@ (in our case of 1 m@o in regarding of the cal- culated rms flux noise CJ@ M 5 m3j0) result in a smaller feed- back loop slew rate and that is why the THD of the output signal could be higher [lo].

A similar effect is caused by deviations of the compa- rator clock amplitude from the optimum fco,opt which is characterizedAby switching probabilities P& = 50%. Small deviations AI,, of few per cent from the optimum cause nonlinear effects in the comparator switching behavior (see Fig. 4). In Fig. 6 the consequences for the THD are shown. The reduced bandwidth of the feedback loop is characteri- zed by a significant slope of the THD. Simulations shopred that the flux noise f i increases exponentially with A I o .

The effect of bit errors occurring in the feedback loop is illustrated in Fig. 7. In addition to the appearance

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time 5ms

time 5 m s

Fig. 8. Reconstructed and D/A converted signals. The sensor was operated in a) a magnetically shielded room, and b) without any shielding in the laboratory.

of higher harmonics from a sinusoidal 150 Hz signal and a reduced bandwidth the calculated noise spectral density shows the expected l/f2 like excess noise. Further simula- tions have shown that the flux noise caused by bit errors is proportional to A@.fc .BEP.

Possible reasons for the obtained differences between cal- culated and measured white noise levels are due to other possible noise sources and problems of comparator clock generation. Despite this it seems to be clear that the per- formance of the present SQUID sensor concept in view of sensitivity and linearity for low frequency applications de- mands a high clock frequency fc limited by the room tem- perature electronics, an exact adjustment of comparator clock amplitude, a good matching of step size A@ to the rms flux noise level and bit error probabilities as small as possible.

V. MEASUREMENTS

The characterization of the components has mainly been performed with the test chips. The designed inductances have been met quite well (Table I), except the write gate inductance. This result (3 pH) is difficult to explain. For one washer with a 10 pm hole an inductance of 16 pH has been estimated, consequently the inductance of four parallel connected washers should be at least a quarter of this value.

Sensor operation has been demonstrated by reconstruc- tion of sine and triangular input signals in a shielded room as well as in unshielded environment (Fig. 8). The clock

IO

Fig. 9. Shift of the comparator threshold curve versus unipolar clock pulses applied to the comparator.

frequency fc was 9.5 MHz. The step size A@ was measured by accumulating a well

known number of flux quanta in the pickup loop applying a low frequency unipolar comparator clock. The amplitude was set to force the comparator to switch to the voltage stage thus activating the write gate once for pulse. Before and after this procedure the thresh of the comparator was measured with a low bip frequency ( M 10 kHz). The shift of the threshold curve, shown in Fig. 9, was used to estimate A@. For small num- bers of accumulated flux quanta (M 5000), the shift of the curve was approximately proportional to the number of clock pulses. For flux quantum numbers exceeding x 7000 the write gate operation gets faulty - due to the working point shift - on a level which could be detected with the coarse measuring method described comparator with a bipolar clock an ding the maximum critical current should not change the flux quanta number in the pickup should add and subtract one flux period. However, as soon as the bi the measurement showed a decay cating that bit errors occurred in the comparator and/or the write gate operation.

The half-life period of the seconds and independent of red at the beginning. The re

TABLE I ESTIMATED AND MEASURED DATA OF THE SENSOR AND COMPONENTS

calculated measured

Comp. ind. M lOpH Write gate ind N 3pH Flux tr . ratio A@ O.9m@o 08ma.o

dPc/d@ 8O/@o Slew rate 7.6 k@o/s 6.6 k@,o/s Bandwidth 230 kHz < 30 kHz White noise 2 @ 0 / 6 N ~ O W @ O / I / &

I

2751

10.’

10”

1 o - ~

1 de 1 0” IO’ 1 0‘ 1 o3 1 o4

Frequency [Hz]

Fig. 10. Noise spectra of the digital SQUID in a magnetically shielded room with an additional superconducting shield around the sensor. A 100 Hz signal with an amplitude of 0.1 @a was applied taking (1). Noise within the magnetically shielded room but without supercon- ducting shield (2). Comparator only, with externally closed feedback loop (3).

tional to the number N of stored flux quanta respectively to the working point shift of the write gate:

B E P = ~ G ~ O - ~ . N . (2) Noise measurements have been taken in a well shielded

environment (Fig. 10) and without any shielding. For the first case the white noise level was about 30 ,U@*/&. The measurements of noise and bandwidth have not been taken simultaneously, because the working point adjustment was different. The low frequency noise at 1 Hz was quite high, about 3-6m@o/& with a l/f2 slope. We believe that this noise is caused by bit errors for the following reasons.

Measurements (not shown in Fig. 10) without using the amplifier chain and the impedance transformer, resulted in a higher low frequency noise.

The noise of the comparator was measured closing the feedback loop with the room temperature electronics [ l l ] . For this the D/A converted signal was applied to one con- trol line of the comparator. The write gate was deactivated shorting the test point. For this arrangement the contribu- tion of bit errors to the low frequency noise should be small because the errors will be corrected within some clock pul- ses. The measurements confirmed these assumptions. The low frequency noise was improved to about 30,u@o/& at 1 Hz, the white noise level was measured to be about

The measured decay of the stored flux described above. Simulations confirm a 1/f2 characteristic and bit error

probabilities of about 3 for the measured low fre- quency noise. A l/f like noise was measured without any shielding in the laboratory.

15 ,u@&ZG.

VI. DISCUSSION The measured white noise level (15 ,U%J/&) is about a

factor of 7 higher than the calculated level. The reduced bandwidth (Table I) is a consequence of the increased noise.

The reason for these deviations may be a slightly incorrect adjustment of the comparator clock amplitude. Further investigations on theory and measurement arrangement are necessary to clear up this point.

The excess low frequency noise is caused by bit errors. We believe that the write gate is the dominant source of error in our case. The damping resistances (R8, R9 in Fig. 2) of the write gate junctions have to be increased. In ad- dition a smaller inductance of this gate may enlarge the operation margin and therefore decrease bit error probabi- lity.

VII. CONCLUSION Based on modeling and simulations we have found rules

of thumb for the design of superconducting delta modula- tors. The quantization step size should be comparable to the rms noise level sensed by the comparator. The sensor performance is very sensitive to deviations from an opti- mum working point adjusted by the comparator clock am- plitude.

Noise measurements have demonstrated that attention has to be focused on bit errors. Excess low frequency noise is not acceptable for most of the SQUID applications. Very low bit error rates seem to be possible [12]. More investi- gations and improved designs are necessary to reach this goal.

REFERENCES [I] D.Drung, “Digital feedback loops for dc-SQUIDS,” Cryogenzcs,

[Z] N Fujimaki, H. Tamura, T. Imamura, and S. Hasuo, “A Single-Chip SQUID Magnetometer,” IEEE J.Solid-State Czr- cuzts Conf., WAM3.1, 1988

[3] K.K. Likharev and V.K. Semenov, “RSFQ Logic/Memory Family: A New Josephson Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems,” IEEE Trans.Appl.Supercond., vol. 1, no. 1, pp. 3-28, 1991 M. Radparvar, “A wide dynamic range single-chip SQUID mag- netometer,” IEEE Trans. Appl. Supercond., vol. 4, no. 2, pp. 87-91, 1994

[5] P. Yuh and S.V. Rylov, “An Experimental Digital SQUID with Large Dynamic Range and Low noise,” IEEE Trans.Appl.Supercond., vol. 5, no. 2, pp. 2139-2132, 1995

[6] J.C. Candy and G.C Temes, “Oversampling methods for A/D and D/A conversion,” in Ouersamplang Delta-Sigma Data Con- verters, J.C Candy and G.C. Temes (Eds.), 1992, pp. 1-25, IEEE Press N. Fujimaki, “Josephson Integrated Circuits 111: A Single-Chip SQUID Magnetometer,” Fujitsu Sci. Tech. J . , vol. 27, no. 1, pp. 59-83, Apr. 1991 J. Knuutila, M. Kajola, H. Seppa, R. Mutikainen, and J. Salmi, “Design, optimization and construction of a dc SQUID with complete flux transformer circuits,” J.Lou Temp. Phys., vol. 71, no. 5/6, pp. 369-392, 1988 A. Schindler, H. Uhlmann, and U. Fath, “Design and analysis of a digital SQUID magnetometer with integrated feedback cir- cuit,” in Applied Superconductivity 1995, D. Dew-Hughes (Ed.), 1995, Inst. of Physics Conf. Series no. 148 , pp. 1589-1592.

“Impact of Noise on Linearity of SQUID Feedback Loops at High Slew Rate,” IEEE Trans.AppZ.Supercond., vol. 3, no. 3, pp. 3054-3058, 1993

[ll] W. Eschner, U. Fath, G. Hofer, R. Hundhausen, H. Kratz, W. Ludwig, W. Rothmund, and M. Wulker, “Magnetic Field Sensors With Digital Feedback Read-out,“ IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 1824-1827, 1993

[12] T.V. Filippov, V.K. Semenov, and K.K. Likharev, “Signal Re- solution of RSFQ Comparators,” IEEE Trans. Appl.Supercond., vol. 5, no. 2, pp. 2240-2243, 1995

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